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RF21743V DCS Power Amplifier
RF2174
3V DCS POWER AMPLIFIER RoHS Compliant and Pb-Free Product Package: QFN, 16-Pin, 3x3
VCC2
VCC2
VCC2 14 8 VCC
GND
Features
Single 2.7V to 4.8V Supply Voltage +33dBm Output Power at 3.5V 27dB Gain with Analog Gain Control 51% Efficiency 1700MHz to 1950MHz Operation Supports DCS1800 and PCS1900
1 AT_EN 2 RF IN 3 GND1 4 5 VCC1
16
15
6 APC1
7 APC2
Applications
3V DCS1800 (PCN) Cellular Handsets 3V DCS1900 (PCS) Cellular Handsets 3V Dual-Band/Triple-Band Handsets Commercial and Consumer Systems Portable Battery-Powered Equipment GPRS Compatible
Functional Block Diagram
Product Description
The RF2174 is a high power, high efficiency power amplifier module offering high performance in GSM or GPRS applications. The device is manufactured on an advanced GaAs HBT process, and has been designed for use as the final RF amplifier in DCS1800/1900 hand-held digital cellular equipment and other applications in the 1700MHz to 2000MHz band. Onboard power control provides over 65dB of control range with an analog voltage input, and provides power down with a logic "low" for standby operation. The device is self-contained with 50W input and the output can be easily matched to obtain optimum power and efficiency characteristics. The RF2174 can be used together with the RF2173 for dual-band operation. The device is packaged in an ultra-small plastic package, minimizing the required board space.
Optimum Technology Matching(R) Applied
GaAs HBT GaAs MESFET InGaP HBT SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS Si BJT GaN HEMT RF MEMS
RF MICRO DEVICES(R), RFMD(R), Optimum Technology Matching(R), Enabling Wireless ConnectivityTM, PowerStar(R), POLARISTM TOTAL RADIOTM and UltimateBlueTM are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. (c)2006, RF Micro Devices, Inc.
Rev A8 DS060918
7628 Thorndike Road, Greensboro, NC 27409-9421 * For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
GND
2F0 13 12 RF OUT 11 RF OUT 10 RF OUT 9
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RF2174
Absolute Maximum Ratings Parameter
Supply Voltage Power Control Voltage (VAPC) Enable Voltage (VAT_EN) DC Supply Current Input RF Power Duty Cycle at Max Power Output Load VSWR Operating Case Temperature Storage Temperature
Rating
-0.5 to +6.0 -0.5 to +3.0 -0.5 to +3.0 1500 +13 50 10:1 -40 to +85 -55 to +150
Unit
VDC V V mA dBm % C C
Caution! ESD sensitive device.
Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maximum Rating conditions is not implied. RoHS status based on EUDirective2002/95/EC (at time of this document revision). The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice.
Parameter
Overall
Operating Frequency Range Usable Frequency Range Maximum Output Power
Min.
Specification Typ.
Max.
Unit
Condition
Temp=25 C, VCC =3.2V, VAPC =2.7V, PIN =+6dBm, Freq=1710MHz to 1910MHz, 25% Duty Cycle, pulse width=1154s
1710 to 1785 1850 to 1910 1700 to 2000 +32 +31.5 +33 +32.8 +31.5 +31 +29.5 +30 51 51 15 10
MHz MHz MHz dBm dBm dBm dBm dBm % % % % +9 -79 dBm dBm
See application schematic for tuning details. A different tuning is required. Temp=25 C, VCC =3.5V, VAPC =2.7V Temp=+25 C, VCC =3.2V, VAPC =2.7V Temp=+85 C, VCC =3.2V, VAPC =2.7V Temp=25 C, VCC =2.7V, VAPC =2.7V Temp=+85 C, VCC =2.7V, VAPC =2.7V At POUT,MAX, VCC =3.2V, Freq=1710MHz to 1785MHz At POUT,MAX, VCC =3.2V, Freq=1850MHz to 1910MHz POUT =+20dBm POUT =+10dBm RBW=100kHz, 1805MHz to 1880MHz and 1930MHz to 1990MHz, POUT,MIN Total Efficiency
45 42
Recommended Input Power Range Output Noise Power
+5
+7
Forward Isolation
-37 -37 -40
-30 -30 -35 -45 -50 -36
dBm dBm dBm dBc dBc dBm
Second Harmonic Third Harmonic All Other Non-Harmonic Spurious Input Impedance
-60 -65 50
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Rev A8 DS060918
RF2174
Parameter
Overall, cont.
Input VSWR Output Load VSWR Output Load Impedance 10:1 4.5-j3.9 2.6 0.2 2.5 0.2 61.5 0.5 2.6 0.5 68 100 10 4.5 5 10 AT_EN Input Current Turn On/Off Time 500 10 100 3.5 2.7 4.8 5.5 Power Supply Current 50 1 1 1.3 300 10 10 2.85 V V V V dB dB/V pF mA A A A ns V V V A mA A A Specifications Nominal operating limits, POUT <+33dBm With maximum output load VSWR 6:1, POUT <+33dBm DC Current at POUT,MAX Idle Current, PIN <-30dBm PIN <-30dBm, VAPC =0.2V PIN <-30dBm, VAPC =0.2V, Temp=+85C 2.2:1 3:1 POUT,MAX-5dBMin.
Specification Typ.
Max.
Unit
Condition
Power Control
Power Control "ON" Power Control "OFF" Attenuator Enable "ON" Attenuator Enable "OFF" Power Control Range Gain Control Slope APC Input Capacitance APC Input Current
Power Supply
Power Supply Voltage
Rev A8 DS060918
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RF2174
Pin 1 2 Function GND AT_EN Description
Internally connected to the ground slug. Control input for the PIN diode. The purpose of the PIN diode is to attenuate the RF input drive level when the VAPC is low. This serves both to reduce the leakage through the device cause by self biasing when driving with high level at the RF input, as well as to maintain a good input match when the bias of the input stage is turned off. When this pin is "high" the PIN diode control is turned on. See the Theory of Operation for more details. RF Input. This is a 50 input, but the actual impedance depends on the interstage matching network connected to pin 5. An external DC blocking capacitor is required if this port is connected to a DC path to ground or a DC voltage.
Interface Schematic
See pin 15.
T o P IN diode A T_E N 3k
GND1
3
RF IN
VCC1
RF IN PIN From Attn control circuit
GND 1
From Bias Stages
4
GND1
5
VCC1
6
APC1
Ground connection for the pre-amplifier stage. Keep traces physically short See pin 3. and connect immediately to the ground plane for best performance. It is important for stability that this pin has it's own vias to the groundplane, to minimize any common inductance. Power supply for the pre-amplifier stage and interstage matching. This pin See pin 3. forms the shunt inductance needed for proper tuning of the interstage match. Please refer to the application schematic for proper configuration, and note that position and value of the components are important. Power Control for the driver stage and pre-amplifier. When this pin is "low," A P C V C C all circuits are shut off. A "low" is typically 0.5V or less at room temperature. A shunt bypass capacitor is required. During normal operation this pin is the power control. Control range varies from about 1.0V for -10dBm to 2.6V for +33dBm RF output power. The maximum power that can be achieved depends on the actual output matching; see the application information for more details. The maximum current into this pin is 5mA when VAPC1 =2.6V, and 0mA when VAPC =0V.
GND GND
To RF S ta g e s
7 8 9 10
APC2 VCC GND RF OUT
Power Control for the output stage. See pin 6 for more details. Power supply for the bias circuits. Internally connected to the ground slug. RF Output and power supply for the output stage. Bias voltage for the final stage is provided through this wide output pin. An external matching network is required to provide the optimum load impedance.
See pin 6. See pin 6.
RF OUT
From Bias GND Stages PCKG BASE
11 12 13
RF OUT RF OUT 2F0
Same as pin 10. Same as pin 10. Connection for the second harmonic trap. This pin is internally connected to the RF OUT pins. The bonding wire together with an external capacitor form a series resonator that should be tuned to the second harmonic frequency in order to increase efficiency and reduce spurious outputs. Same as pin 15.
Same as pin 10. Same as pin 10. Same as pin 10.
14
VCC2
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Rev A8 DS060918
RF2174
Pin 15 Function VCC2 Description
Power supply for the driver stage and interstage matching. This pin forms the shunt inductance needed for proper tuning of the interstage match. Please refer to the application schematic for proper configuration, and note that position and value of the components are important.
Interface Schematic
VCC2
From Bias GND2 Stages
16 Pkg Base
VCC2 GND
Same as pin 15. Ground connection for the output stage. This pad should be connected to the groundplane by vias directly under the device. A short path is required to obtain optimum performance, as well as to provide a good thermal path to the PCB for maximum heat dissipation.
Same as pin 15.
Package Drawing
QFN, 16-Pin, 3x3
-B-
0.10 C B
0.10 C B
4.00 2.00
2 PLCS
3.75
2 PLCS
0.80
TYP
2 A
1.60
2 PLCS
3.75 0.75 0.50
INDEX AREA
1.50
SQ.
4.00
0.10 C A
2 PLCS
0.45 0.28 3.20
2 PLCS
2.00
0.10 C A
2 PLCS
0.10 M C A B
12 MAX 0.05 0.00
1.00 0.90 Dimensions in mm.
C
0.05
Shaded pin is lead 1.
0.75 0.65
Rev A8 DS060918
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RF2174
Theory of Operation and Application Information
The RF2174 is a three-stage device with 28 dB gain at full power. Therefore, the drive required to fully saturate the output is +5dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part requires only a single positive 3V supply to operate to full specification. Power control is provided through a single pin interface, with a separate Power Down control pin. The final stage ground is achieved through the large pad in the middle of the backside of the package. First and second stage grounds are brought out through separate ground pins for isolation from the output. These grounds should be connected directly with vias to the PCB ground plane, and not connected with the output ground to form a so called "local ground plane" on the top layer of the PCB. The output is brought out through the wide output pad, and forms the RF output signal path. The amplifier operates in near Class C bias mode. The final stage is "deep AB", meaning the quiescent current is very low. As the RF drive is increased, the final stage self-biases, causing the bias point to shift up and, at full power, draws about 1500mA. The optimum load for the output stage is approximately 4.5. This is the load at the output collector, and is created by the series inductance formed by the output bond wires, vias, and microstrip, and 2 shunt capacitors external to the part. The optimum load impedance at the RF Output pad is 4.5-j3.9. With this match, a 50 terminal impedance is achieved. The input is internally matched to 50 with just a blocking capacitor needed. This data sheet defines the configuration for GSM operation. The input is DC coupled; thus, a blocking cap must be inserted in series. Also, the first stage bias may be adjusted by a resistive divider with high value resistors on this pin to VPC and ground. For nominal operation, however, no external adjustment is necessary as internal resistors set the bias point optimally. When the device is driven at maximum input power self biasing would occur. This results in less isolation than one would expect, and the maximum output power would be about -15dBm. If the drive power to the PA is turned on before the GSM ramp-up, higher isolation is required. In order to meet the GSM system specs under those conditions, a PIN diode attenuator connected to the input can be turned on. The figure below shows how the attenuator and its controls are connected.
VCC RF IN 750 5 k APC 2 k AT_EN 500 PIN From Bia Stages
The current through the PIN diode is controlled by two signals: AT_EN and APC. The AT_EN signal allows current through the PIN diode and is an on/off function. The APC signal controls the amount of current through the PIN diode. Normally, the AT_EN signal will be derived from the VCO ENABLE signal available in most GSM handset designs. If maximum isolation is needed before the ramp-up, the AT_EN signal needs to be turned on before the RF power is applied to the device input. The current into this pin is not critical, and can be reduced to a few hundred micro amps with an external series resistor. Without the resistor, the pin will draw about 700A.
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Rev A8 DS060918
RF2174
Because of the inverting stage at the APC input, the current through the PIN diode is inverted from the APC voltage. Thus, when VAPC is high for maximum output power, the attenuator is turned off to obtain maximum drive level for the first RF stage. When VAPC is low for maximum isolation, the attenuator is be turned on to reduce the drive level and to avoid self-biasing. The PIN diode is dimensioned such that a low VAPC the impedance of the diode is about 50 Ohm. Since the input impedance of the first RF stage become very high when the bias is turned off, this topology will maintain a good input impedance over the entire VAPC control range. VCC1 and VCC2 provide supply voltage to the first and second stage, as well as provides some frequency selectivity to tune to the operating band. Essentially, the bias is fed to this pin through a short microstrip. A bypass capacitor sets the inductance seen by the part, so placement of the bypass cap can affect the frequency of the gain peak. This supply should be bypassed individually with 100pF capacitors before being combined with VCC for the output stage to prevent feedback and oscillations. The RF OUT pin provides the output power. Bias for the final stage is fed to this output line, and the feed must be capable of supporting the approximately 1.5A of current required. Care should be taken to keep the losses low in the bias feed and output components. A narrow microstrip line is recommended because DC losses in a bias choke will degrade efficiency and power. While the part is safe under CW operation, maximum power and reliability will be achieved under pulsed conditions. The data shown in this data sheet is based on a 12.5% duty cycle and a 600s pulse, unless specified otherwise. The part will operate over a 3.0V to 5.0V range. Under nominal conditions, the power at 3.5V will be greater than +32dBm at +85C. As the voltage is increased, however, the output power will increase. Thus, in a system design, the ALC (Automatic Level Control) Loop will back down the power to the desired level. This must occur during operation, or the device may be damaged from too much power dissipation. At 5.0V, over +36dBm may be produced; however, this level of power is not recommended, and can cause damage to the device. The HBT breakdown voltage is >20V, so there is no issue with overvoltage. However, under worst-case conditions, with the RF drive at full power during transmit, and the output VSWR extremely high, a low load impedance at the collector of the output transistors can cause currents much higher than normal. Due to the bipolar nature of the devices, there is no limitation on the amount of current the device will sink, and the safe current densities could be exceeded. High current conditions are potentially dangerous to any RF device. High currents lead to high channel temperatures and may force early failures. The RF2174 includes temperature compensation circuits in the bias network to stabilize the RF transistors, thus limiting the current through the amplifier and protecting the devices from damage. The same mechanism works to compensate the currents due to ambient temperature variations. To avoid excessively high currents it is important to control the VAPC when operating at supply voltages higher than 4.0V, such that the maximum output power is not exceeded.
Rev A8 DS060918
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RF2174
Application Schematic
VCC 12 pF 1 nF
Very close to pin 15/16 Instead of a stripline, an inductor of ~6 nH can be used
VCC 15 pF
1.0 pF 1 AT_EN RF IN 33 pF 4
Distance between edge of device and capacitor is 0.240" to improve the "off" isolation
16
15
14
13 12 11 10 3.6 pF
Instead of a stripline, an inductor of 2.2 nH can be used
2 3
Quarter wave length 50 strip 4.3 pF
Note 1
33 pF RF OUT 1.3 pF 1.3 pF
Note 1
5 VCC
6
7
8
9 VCC
Distance between edge of device and capacitor is 0.080" Distance center to center of capacitors 0.220"
15 pF
15 pF
15 pF
15 pF
APC
Note: All capacitors are standard 0402 multi layer chip Note 1: Using a hi-Q capacitor will increase efficiency slightly
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Rev A8 DS060918
RF2174
Internal Schematic
VCC1 VCC2 RF OUT
RF IN
APC1
VCC
APC2
VCC
VCC
750
500 320
500
200
APC1
5k
AT_EN
3k 2.5k 2.5k 1.5k
1.5k GND1 PKG BASE PKG BASE
Rev A8 DS060918
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RF2174
Evaluation Board Schematic
VEN + VCC P1-1 P1 1 2 C7 3.3 uF + C10 1 pF C8 1 nF C9 33 pF P1-3 P1-4 3 4 5 CON5 VEN GND VCC VCC GND
C22 1 nF
C19 3.3 uF C6 1 nF C5 12 pF
C21 1 nF J1 RF IN 50 strip C1 33 pF +
1 2 3 4 5
16
15
14
13 12 11 10
Quarter Wave Length
50 strip C3 3.6 pF
2174400-
C2 33 pF C27 1.5 pF
VCC C20 3.3 uF C12 1 nF C11 27 pF 6 7 8 9
C26 4.3 pF
C4 1.3 pF
J2 RF OUT
C23 10 nF
C16 1 nF
C13 33 pF
C14 33 pF VCC C17 1 nF C24 10 nF 50 strip C15 33 pF C25 10 nF C18 3.3 uF +
J3 VAPC
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Rev A8 DS060918
RF2174
Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.032"; Board Material FR-4; Multi-Layer
Rev A8 DS060918
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RF2174
Typical Test Setup
Power Supply V- S- S+ V+
RF Generator Spectrum Analyzer 3dB Buffer x1 OpAmp Pulse Generator
A buffer amplifier is recommended because the current into the VAPC changes with voltage. As an alternative, the voltage may be monitored with an oscilloscope.
10dB/5W
Notes about testing the RF2174
The test setup shown above includes two attenuators. The 3dB pad at the input is to minimize the effects that the switching of the input impedance of the PA has on the signal generator. When VAPC is switched quickly, the resulting input impedance change can cause the signal generator to vary its output signal, either in output level or in frequency. Instead of an attenuator an isolator may also be used. The attenuator at the output is to prevent damage to the spectrum analyzer, and should be able to handle the power. It is important not to exceed the rated supply current and output power. When testing the device at higher than nominal supply voltage, the VAPC should be adjusted to avoid the output power exceeding +36dBm. During load-pull testing at the output it is important to monitor the forward power through a directional coupler. The forward power should not exceed +36dBm, and VAPC needs to be adjusted accordingly. This simulates the behavior for the power control loop in this respect. To avoid damage, it is recommended to set the power supply to limiting the current during the burst, not to exceed the maximum current rating.
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Rev A8 DS060918
RF2174
PCB Design Requirements
PCB Surface Finish The PCB surface finish used for RFMD's qualification process is Electroless Nickel, immersion Gold. Typical thickness is 3inch to 8inch Gold over 180inch Nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern
A = 0.51 x 0.89 (mm) Typ. B = 0.89 x 0.51 (mm) Typ. C = 1.52 (mm) Sq. 3.20 (mm) Typ. 0.81 (mm) Typ.
Pin 1
A 1.73 (mm) Typ. 0.81 (mm) Typ.
A
A
A
A
B B B C
B 0.81 (mm) Typ. B B 1.60 (mm)
0.94 (mm) Typ. A A 1.60 (mm) Typ. 1.73 (mm) Typ. A A A
Figure 1. PCB Metal Land Pattern (Top View)
Rev A8 DS060918
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RF2174
PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the PCB Metal Land Pattern with a 3mil expansion to accommodate solder mask registration clearance around all pads. The centergrounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.71 x 1.09 (mm) Typ. B = 1.09 x 0.71 (mm) Typ. C = 1.73 (mm) Sq. 3.20 (mm) Typ. 0.81 (mm) Typ.
Pin 1
A 1.73 (mm) Typ. 0.81 (mm) Typ.
A
A
A
A
B B B C
B 0.81 (mm) Typ. B B 1.60 (mm)
0.94 (mm) Typ. A A 1.60 (mm) Typ. 1.73 (mm) Typ. A A A
Figure 2. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern shown has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 3. shows the via pattern used for the RFMD qualification design.
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Rev A8 DS060918
RF2174
0.508 (mm) Grid
Via 0.305 (mm) Finished Hole
Figure 3. Thermal Pad and Via Design (RF2173)
Rev A8 DS060918
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RF2174
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Rev A8 DS060918

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