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PCI EXPRESSTM JITTER ATTENUATOR
ICS874003-02
GENERAL DESCRIPTION
The ICS874003-02 is a high performance DifIC S ferential-to-LVDS Jitter Attenuator designed for HiPerClockSTM use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003-02 has a bandwidth of 400kHz. The 400kHz provides an intermediate bandwidth that can easily track tr iangular spread profiles, while providing good jitter attenuation. The ICS874003-02 uses IDT's 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.
FEATURES
* Three Differential LVDS output pairs * One Differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 98MHz - 320MHz * Input frequency range: 98MHz - 128MHz * VCO range: 490MHz - 640MHz * Cycle-to-cycle jitter: 35ps (maximum) * Supports PCI-Express Spread-Spectrum Clocking * The 400kHz bandwidth mode allows the system designer to make jitter attenuation/tracking skew design trade-offs * 3.3V operating supply * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
F_SEL[2:0] FUNCTION TABLE
F_SEL2 0 1 0 1 0 1 Inputs F_SEL1 0 0 1 1 0 0 1 1 F_SEL0 0 0 0 0 1 1 1 1 Outputs QA0/nQA0, QA0/nQA0 /2 /5 /4 /2 /2 /5 /4 /4 QB0/nQB0 /2 /2 /2 /4 /5 /4 /5 /4
BLOCK DIAGRAM
OEA Pullup F_SEL2:0 Pulldown
3
0 1
PIN ASSIGNMENT
QA0
/5 /4 /2 (default)
CLK Pulldown nCLK Pullup
nQA0 QA1
Phase Detector
VCO
490 - 640MHz
3
nQA1
QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA
M = /5 (fixed)
/5 /4 /2 (default)
QB0
ICS874003-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
nQB0
MR Pulldown Pullup OEB
G Package Top View
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ICS874003-02 PCI EXPRESSTM JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number 1, 20 2, 19 3, 4 5 6, 9, 16 7 8 10 11 12 13 14 15 17, 18 Name QA1, nQA1 VDDO QA0, nQA0 MR F_SEL0, F_SEL1, F_SEL2 nc VDDA VDD OEA CLK nCLK GN D OE B nQB0, QB0 Power Output Input Type Output Description Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown Frequency select pin for QAx/nQAx and QBx0/nQB0 outputs. LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels.
Input Unused Power Power Input Input Input Power Input Output
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3. OUTPUT ENABLE FUNCTION TABLE
Inputs OEA 0 1 OEB 0 1 HiZ Enabled Outputs QA0/nQA0, QA1/nQA1 QB0/nQB0 HiZ Enabled
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.12 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 75 12 75 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V A A A A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = VIN = 3.465V -150 0.15 1.3 V V 5 15 0 A Minimum Typical Maximum 15 0 Units A
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD - 0.85 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is VDD + 0.3V.
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TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.2 1.35 Test Conditions Minimum 275 Typical 375 Maximum 485 50 1.5 50 Units mV mV V mV
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX Parameter Output Frequency Cycle-to-Cycle Jitter, NOTE 1 Output Skew; NOTE 2, 3 Bank Skew; NOTE 1, 4 Output Rise/Fall Time Bank A 20% to 80% 275 Test Conditions Minimum 98 Typical Maximum 320 35 145 55 725 53 Units MHz ps ps ps ps %
tjit(cc) tsk(o) tsk(b)
tR / tF
odc Output Duty Cycle 47 NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
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PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDD, VDDO
Qx
VDDA
nCLK
V
PP
LVDS
nQx
Cross Points
V
CMR
CLK
GND
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQA0, nQA1, nQB0 QA0, QA1, QB0
nQx Qx
tcycle n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
nQXx QXx nQXy QXy
nQA0, nQA1, nQB0 QA0, QA1, QB0
tsk(b)
Where X = A or B
BANK SKEW
IDT TM / ICSTM PCI EXPRESSTM JITTER ATTENUATOR
tcycle n+1
nQy Qy
tsk(o)
OUTPUT SKEW
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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VDD out
80% Clock Outputs
80% VSW I N G
DC Input
LVDS
out
20% tR tF
20%
VOS/ VOS
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD

out
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS874003-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
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LVDS DRIVER TERMINATION
A general LVDS inteface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V LVDS_Driv er + R1 100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874003-02. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS874003-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
* *
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (75mA + 12mA) = 301.45mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.87mW
Total Power_MAX = 301.45mW + 259.87mW = 561.32mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.561W * 66.6C/W = 107.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 20-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS874003-02 is: 1408
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PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153
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TABLE 8. ORDERING INFORMATION
Part/Order Number ICS874003AG-02 ICS874003AG-02T ICS874003AG-02LF ICS874003AG-02LFT Marking 874003A02 874003A02 74003A02L 74003A02L Package 20 Lead TSSOP 20 Lead TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Europe
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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