View CYRF69213_4164792.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CYRF69213
Programmable Radio on Chip Low Power
PRoCTM LP Features
* Single Device, Two Functions -- 8-bit, Flash based USB peripheral MCU function and 2.4 GHz radio transceiver function in a single device * Flash-based Microcontroller Function -- M8C based 8-bit CPU, optimized for Human Interface Devices (HID) applications -- 256 Bytes of SRAM -- 8 Kbytes of Flash memory with EEPROM emulation -- In-System reprogrammable through D+/D- pins. -- 16-bit free running timer -- Low power wake up timer -- 12-bit Programmable Interval Timer with interrupts -- Watchdog timer * Industry-Leading 2.4 GHz Radio Transceiver Function -- Operates in the unlicensed worldwide Industrial, Scientific and Medical (ISM) band (2.4 GHz-2.483 GHz) -- DSSS data rates of up to 250 Kbps -- GFSK data rate of 1 Mbps -- -97 dBm receive sensitivity -- Programmable output power of up to +4 dBm -- Auto Transaction Sequencer (ATS) -- Framing CRC and Auto ACK * -- Received Signal Strength Indication (RSSI) -- Automatic Gain Control (AGC) Component Reduction -- Integrated 3.3V regulator -- Integrated pull up on D- -- GPIOs that require no external components -- Operates off a single crystal Flexible I/O -- High current drive on GPIO pins. Configurable 8-mA or 50-mA/pin current sink on designated pins -- Each GPIO pin supports high-impedance inputs, configurable pull up, open-drain output, CMOS/TTL inputs and CMOS output -- Maskable intrrupts on all I/O pins USB Specification Compliance -- Conforms to USB Specification Version 2.0 -- Conforms to USB HID Specification Version 1.1 -- Supports one Low Speed USB device address -- Supports one control endpoint and two data end points -- Integrated USB Transceiver Operating voltage from 4.0V to 5.5V DC Operating temperature from 0 to 70C Lead-free 40-lead QFN package Advanced development tools based on Cypress's PSoC(R) Tools
*
*
* * * *
PRoCTM LP CYRF69213 Block Diagram
Vbus MOSI 4.7uF 1-2 uF SCK nSS 470nF
VBat1
VBat3
RST
VBat2
VReg
VCC1
VCC2
VDD_MICRO
P1.2 / VReg
VCC3 VSS
RFbias RFp RFn
P0_2:4,7 4 P1_6:7 2 P2_0:1 2 D+/D2
Microcontroller Function
P1.5/MOSI P1.4/SCK P1.3/nSS RESV
Radio Function
IRQ/GPIO MISO/GPIO XOUT/GPIO PACTL/GPIO GND GND
.....
12MHz
.......
GND
Xtal
Cypress Semiconductor Corporation Document #: 001-07552 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 20, 2007
[+] Feedback
VIO 470nF
CYRF69213
Applications
The CYRF69213 PRoC LP Low Speed is targeted for the following applications: * USB Bridge for Human Interface Devices (HID) -- Wireless mice -- Wireless keyboards -- Remote controls -- Gaming applications * USB Bridge for General Purpose Applications -- Consumer electronics -- Industrial applications -- White goods -- Home automation -- Personal health
Data Transmission Modes The radio supports four different data transmission modes: * In GFSK mode, data is transmitted at 1 Mbps without any DSSS * In 8DR mode, 1 byte is encoded in each PN code symbol transmitted * In DDR mode, 2 bits are encoded in each PN code symbol transmitted * In SDR mode, a single bit is encoded in each PN code symbol transmitted Both 64-chip and 32-chip data PN codes are supported. The four data transmission modes apply to the data after the Start of Packet (SOP). In particular, the packet length, data and CRC are all sent in the same mode. USB Microcontroller Function The microcontroller function is based on the powerful CYRF69213 microcontroller. It is an 8-bit Flash programmable microcontroller with integrated low speed USB interface. The microcontroller has up to 14 GPIO pins to support USB, PS/2 and other applications. Each GPIO port supports high-impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. The microcontroller features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (24 MHz 1.5%). The PRoC LP has up to 8 Kbytes of Flash for user's firmware code and up to 256 bytes of RAM for stack space and user variables. The PRoC LP includes a Watchdog timer, a vectored interrupt controller, a 12-bit programmable interval timer with configurable 1-ms interrupt and a 16-bit free running timer with capture registers.
Functional Description
PRoC LP devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution. Communication between the microcontroller and the radio is via the SPI interface between both functions.
Functional Overview
The CYRF69213 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69213 is designed to implement low-cost wireless systems operating in the worldwide 2.4-GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz-2.4835 GHz). 2.4 GHz Radio Function The radio meets the following world-wide regulatory requirements: * Europe -- ETSI EN 301 489-1 V1.4.1 -- ETSI EN 300 328-1 V1.3.1 * North America -- FCC CFR 47 Part 15 * Japan -- ARIB STD-T66
Document #: 001-07552 Rev. *B
Page 2 of 85
[+] Feedback
CYRF69213
Pinout
Pin 1 2 3, 7, 16 4 5 6, 9, 39 8 10 11 12 13 14, 17, 18, 20, 36 15 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Name P0.4 Xtal_in VCC P0.3 P0.1 Vbat P2.1 RF Bias RFp GND RFn NC P2.0 RESV D+ D- VDD_micro P1.2 / VREG P1.3 / nSS P1.4 / SCK IRQ P1.5 / MOSI MISO XOUT PACTL P1.6 VIO Reset GPIO. Port 2 Bit 0 Reserved. Must connect to GND Low-speed USB IO Low-speed USB IO 4.0-5.5 for 12 MHz CPU/4.75-5.5 for 24 MHz CPU Must be configured as 3.3V output. It must have a 1-2 F output capacitor Slave select SPI Pin Serial Clock Pin from MCU function to radio function Interrupt output, configure high/low or GPIO Master Out Slave In. Master In Slave Out, from radio function.Can be configured as GPIO Bufferd CLK, PACTL_n or GPIO Control for external PA or GPIO GPIO. Port 1 Bit 6 I/O interface voltage. Connected to pin 24 via 0.047 F Radio Reset. Connected to VDD via 0.47 F Capacitor or to microcontroller GPIO pin. Must have a RESET = HIGH event the very first time power is applied to the radio otherwise the state of the radio function control registers is unknown. GPIO. Port 1 Bit 7 Regulated logic bypass. Connected via 0.47 F to GND Connected to GND GPIO. Port 0 Bit 7 Connected to pin 24 Connected to GND Individually configured GPIO 12 MHz Crystal. External Clock in Connected to pin 24 via 0.047-F Capacitor. Individually configured GPIO Individually configured GPIO Connected to pin 24 via 0.047-Fshunt capacitor GPIO. Port 2 Bit 1 RF pin voltage reference Differential RF input to/from antenna Ground Differential RF to/from antenna Function
35 36 37 38 40 41
P1.7 VDD_1.8 L/D P0.7 Vreg E-pad
Document #: 001-07552 Rev. *B
Page 3 of 85
[+] Feedback
CYRF69213
Pinout Diagram
Figure 1. Pinout 40-Lead QFN 7 x 7 mm LF48A
PACTL / GPIO 31
VDD_1.8
VREG 40
P1.7 35
P0.7 38
P1.6 32
RST 34
VBAT 39
L/D 37
Corner tabs
VIO
36
33
P0.4 XTAL VCC P0.3 P0.1 VBAT VCC P2.1 VBAT
1 2 3 4 5 6 7 8 9
* E-PAD Bottom Side
30 XOUT / GPIO 29 MISO / GPIO
CYRF69213 WirelessUSB LP
28 P1.5 / MOSI 27 IRQ / GPIO 26 P1.4 / SCK 25 P1.3 / SS 24 P1.2 / VREG 23 VDD_Micro 22 D21 D+
RFBIAS 10 11 RFP 12 GND 13 RFN 14 NC 15 P2.0 16 VCC 17 NC 18 NC 19 RESV 20 NC
PRoC LP Functional Overview
The SoC is designed to implement wireless device links operating in the worldwide 2.4-GHz ISM frequency band. It is intended for systems compliant with world-wide regulations covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry Canada) and TELEC ARIB_T66_March, 2003 (Japan). The SoC contains a 2.4-GHz 1-Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1-MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). In DSSS modes the baseband performs DSSS spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK) the baseband performs Start of Frame (SOF), End of Frame (EOF) detection and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except SDR, enabling the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low-moderate interference environment,
and change to lower data rates at longer distances and/or in high interference environments. The MCU function is an 8-bit Flash-programmable microcontroller with integrated low-speed USB interface. The instruction set has been optimized specifically for USB operations, although it can be used for a variety of other embedded applications. The MCU function has up to eight Kbytes of Flash for user's code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free-Running Timer, and 12-bit Programmable Interrupt Timer. The MCU function supports in-system programming by using the D+ and D- pins as the serial programming mode interface. The programming protocol is not USB. Backward Compatibility The CYRF69213 IC is fully interoperable with the main modes of other Cypress radios CYWUSB6934 and CYRF6936. The 62.5-kbps mode is supported by selecting 32-chip DATA_CODE_ADR codes, DDR mode, and disabling the SOP, length, and CRC16 fields. Similarly, the 15.675-kHz mode is supported by selecting 64-chip DATA_CODE_ADR codes and SDR mode. In this way, a suitably configured CYRF69213 IC device may transmit data to and/or receive data from a first generation device.
Document #: 001-07552 Rev. *B
Page 4 of 85
[+] Feedback
CYRF69213
Functional Block Overview
All the blocks that make up the PRoC LP are presented here. 2.4-GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power and range/robustness. The radio employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in 7 steps. The supply current of the device is reduced as the RF output power is reduced. Table 1. Internal PA Output Power Step Table PA Setting 7 6 5 4 3 2 1 0 Frequency Synthesizer Before transmission or reception may commence, it is necessary for the frequency synthesizer to settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. The `fast channels' (<100-s settling time) are every third frequency, starting at 2400 MHz up to and including 2472 MHz (for example, 0,3,6,9.......69 & 72). Baseband and Framer The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception and CRC16 generation and checking, as well as EOP detection and length field. Data Rates and Data Transmission Modes The SoC supports four different data transmission modes: * In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. * In 8DR mode, 8 bits are encoded in each DATA_CODE_ADR derived code symbol transmitted. * In DDR mode, 2-bits are encoded in each DATA_CODE_ADR derived code symbol transmitted. (As in the CYWUSB6934 DDR mode). * In SDR mode, 1 bit is encoded in each DATA_CODE_ADR derived code symbol transmitted. (As in the CYWUSB6934 standard modes.) Both 64-chip and 32-chip DATA_CODE_ADR codes are supported. The four data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all Typical Output Power (dBm) +4 0 -5 -10 -15 -20 -25 -30
sent in the same mode. In general, lower data rates reduces packet error rate in any given environment. By combining the DATA_CODE_ADR code lengths and data transmission modes described above, the CYRF69213 IC supports the following data rates: * 1000-kbps (GFSK) * 250-kbps (32-chip 8DR) * 125-kbps (64-chip 8DR) * 62.5-kbps (32-chip DDR) * 31.25-kbps (64-chip DDR) * 15.625-kbps (64-chip SDR) Lower data rates typically provide longer range and/or a more robust link. Link Layer Modes The CYRF69213 IC device supports the following data packet framing features: SOP - Packets begin with a 2-symbol Start of Packet (SOP) marker. This is required in GFSK and 8DR modes, but is optional in DDR mode and is not supported in SDR mode; if framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the `body' of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. EOP - There are two options for detecting the end of a packet. If SOP is enabled, then a packet length field may be enabled. GFSK and 8DR must enable the length field. This is the first 8 bits after the SOP symbol, and is transmitted at the payload data rate. If the length field is enabled, an End of Packet (EOP) condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16 (if enabled--see below). The alternative to using the length field is to infer an EOP condition from a configurable number of successive non-correlations; this option is not available in GFSK mode and is only recommended when using SDR mode. CRC16 - The device may be configured to append a 16-bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver will verify the calculated CRC16 for the payload data against the received value in the CRC16 field. The starting value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 will be checked against both the configured and zero CRC16 seeds. CRC16 detects the following errors: * Any one bit in error * Any two bits in error (no matter how far apart, which column, and so on) * Any odd number of bits in error (no matter where they are) * An error burst as wide as the checksum itself Figure 2 shows an example packet with SOP, CRC16 and lengths fields enabled.
Document #: 001-07552 Rev. *B
Page 5 of 85
[+] Feedback
CYRF69213
Figure 2. Example Default Packet Format
Preamble n x 16us 2nd Framing Symbol*
P
SOP 1
1st Framing Symbol*
SOP 2
Length
Packet length 1 Byte Period
Payload Data
CRC 16
*Note:32 or 64us
Packet Buffers Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet. Configuration registers are provided to allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and others. Packet Buffers All data transmission and reception uses the 16-byte packet buffers--one for transmission and one for reception. The transmit buffer allows a complete packet of up to 16 bytes of payload data to be loaded in one burst SPI transaction, and then transmitted with no further MCU intervention. Similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete. The CYRF69213 IC supports packet length of up to 40 bytes; interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU function must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. Auto Transaction Sequencer (ATS) The CYRF69213 IC provides automated support for transmission and reception of acknowledged data packets. When transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the packet in the transmit buffer, and then automatically switches to receive mode and waits for a handshake packet--and then automatically reverts to sleep mode or idle mode when either an ACK packet is received, or a timeout period expires. Similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, then automatically transitions to transmit mode, transmits an ACK packet, and then switches back to receive mode to await the next packet. The contents of the packet buffers are not affected by the transmission or reception of ACK packets. In each case, the entire packet transaction takes place without any need for MCU firmware action; to transmit data the MCU simply needs to load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware simply needs to retrieve Below are the requirements for the crystal to be directly Document #: 001-07552 Rev. *B
the fully received packet in response to an interrupt request indicating reception of a packet. Interrupts The radio function provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active high or active low, and be either a CMOS or open drain output. The IRQ pin can be multiplexed on the SPI if routed to an external pin. The radio function features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes. If more than one radio interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without making use of the IRQ pin by polling the status register(s) to wait for an event, rather than using the IRQ pin. The microcontroller function supports 23 maskable interrupts in the vectored interrupt controller. Interrupt sources include a USB bus reset, LVR/POR, a programmable interval timer, a 1.024-ms output from the Free Running Timer, three USB endpoints, two capture timers, five GPIO Ports, three GPIO pins, two SPI, a 16-bit free running timer wrap, an internal wake-up timer, and a bus active interrupt. The wake-up timer causes periodic interrupts when enabled. The USB endpoints interrupt after a USB transaction complete is on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling. Clocks The radio function has a 12-MHz crystal (30-ppm or better) directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. connected to XTAL pin and GND: Page 6 of 85
[+] Feedback
CYRF69213
* * * * * * *
Nominal Frequency: 12 MHz Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: 30 ppm Series Resistance: <60 ohms Load Capacitance: 10 pF Drive Level: 10 W-100 W
Figure 3. Power Management From Internal Regulator
0.047F
0.047F 0.047F
0.047F 0.047F 0.047F 0.047F 0.047F
VBat2
VBat3
VCC1
VCC2
VBat1
GPIO Interface The MCU function features up to 20 general-purpose I/O (GPIO) pins to support USB, PS/2, and other applications. The I/O pins are grouped into five ports (Port 0 to 4). The pins on Port 0 and Port 1 may each be configured individually while the pins on Ports 2, 3, and 4 may only be configured as a group. Each GPIO port supports high-impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output with up to five pins that support programmable drive strength of up to 50-mA sink current. GPIO Port 1 features four pins that interface at a voltage level of 3.3 volts. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has three dedicated pins that have independent interrupt vectors (P0.2-P0.4). Power-On Reset/Low-Voltage Detect The power-on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. When power falls below a programmable trip voltage, it generates reset or may be configured to generate interrupt. There is a low-voltage detect circuit that detects when VCC drops below a programmable trip voltage. It may be configurable to generate an LVD interrupt to inform the processor about the low-voltage event. POR and LVD share the same interrupt. There is not a separate interrupt for each. The Watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. Power Management The device draws its power supply from the USB Vbus line. The Vbus supplies power to the MCU function, which has an internal 3.3 V regulator. This 3.3 V is supplied to the radio function via P1.2/VREG after proper filtering as shown in Figure 3.
P1.2 / VReg
VBUS VDD_MICRO
PRoC LP
0.1F
Timers The free-running 16-bit timer provides two interrupt sources: the programmable interval timer with 1-s resolution and the 1.024-ms outputs. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. USB Interface The MCU function includes an integrated USB serial interface engine (SIE) that allows the chip to easily interface to a USB host. The hardware supports one USB device address with three endpoints. Low Noise Amplifier (LNA) and Received Signal Strength Indication (RSSI) The gain of the receiver may be controlled directly by clearing the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of the RX_CFG_ADR register. When the LNA bit is cleared, the receiver gain is reduced by approximately 20 dB, allowing accurate reception of very strong received signals (for example when operating a receiver very close to the transmitter). An additional 20 dB of receiver attenuation can be added by setting the Attenuation (ATT) bit; this allows data reception to be limited to devices at very short ranges. Disabling AGC and enabling LNA is recommended unless receiving from a device using external PA. The RSSI register returns the relative signal strength of the on-channel signal power. When receiving, the device may be configured to automatically measure and store the relative strength of the signal being received as a 5-bit value. When enabled, an RSSI reading is taken and may be read through the SPI interface.
Document #: 001-07552 Rev. *B
L/D
Page 7 of 85
VCC3
VIO
VReg
The MCU function features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (24 MHz 1.5%). The clock generator provides the 12-MHz and 24-MHz clocks that remain internal to the microcontroller.
[+] Feedback
CYRF69213
An RSSI reading is taken automatically when the start of a packet is detected. In addition, a new RSSI reading is taken every time the previous reading is read from the RSSI register, allowing the background RF energy level on any given channel to be easily measured when RSSI is read when no signal is being received. A new reading can occur as fast as once every 12 s.
SPI Interface
The SPI interface between the MCU function and the radio function is a 3-wire SPI Interface. The three pins are MOSI (Master Out Slave In), SCK (Serial Clock), SS (Slave Select). There is an alternate 4-wire MISO Interface that requires the connection of two external pins. The SPI interface is controlled by configuring the SPI Configure Register (SICR Address: 0x3D). 3-Wire SPI Interface The radio function receives a clock from the MCU function on the SCK pin. The MOSI pin is multiplexed with the MISO pin. Bidirectional data transfer takes place between the MCU function and the radio function through this multiplexed MOSI pin. When using this mode the user firmware should ensure that the MOSI pin on the MCU function is in a high impedance state, except when the MCU is actively transmitting data. Firmware must also control the direction of data flow and switch directions between MCU function and radio function by setting the SWAP bit [Bit 7] of the SPI Configure Register. The SS pin is asserted prior to initiating a data transfer between the MCU function and the radio function. The IRQ function may be optionally multiplexed with the MOSI pin; when this option is enabled the IRQ function is not available while the SS pin is low. When using this configuration, user firmware should ensure that the MOSI function on MCU function is in a high-impedance state whenever SS is high. Figure 4. 3-Wire SPI Mode
MOSI SCK nSS
The device receives SCK from the MCU function on the SCK pin. Data from the MCU function is shifted in on the MOSI pin. Data to the MCU function is shifted out on the MISO pin. The active low SS pin must be asserted for the two functions to communicate. The IRQ function may be optionally multiplexed with the MOSI pin; when this option is enabled the IRQ function is not available while the SS pin is low. When using this configuration, user firmware should ensure that the MOSI function on MCU function is in a high-impedance state whenever SS is high. Figure 5. 4-WIRE SPI Mode
MOSI SCK nSS
MCU Function
Radio Function
P1.5/MOSI
MOSI
P1.6/MISO
P1.4/SCK
SCK
MISO
P1.3/nSS
nSS
This connection is external to the PRoC LP Chip
SPI Communication and Transactions The SPI transactions can be single byte or multi-byte. The MCU function initiates a data transfer through a Command/Address byte. The following bytes are data bytes. The SPI transaction format is shown in Figure 6. The DIR bit specifies the direction of data transfer. 0 = Master reads from slave. 1 = Master writes to slave. The INC bit helps to read or write consecutive bytes from contiguous memory locations in a single burst mode operation.
MCU Function
P1.5/MOSI
MOSI/MISO multiplexed on one MOSI pin
Radio Function
MOSI
If Slave Select is asserted and INC = 1, then the master MCU function reads a byte from the radio, the address is incremented by a byte location, and then the byte at that location is read, and so on. If Slave Select is asserted and INC = 0, then the MCU function reads/writes the bytes in the same register in burst mode, but if it is a register file then it reads/writes the bytes in that register file. The SPI interface between the radio function and the MCU is not dependent on the internal 12-MHz oscillator of the radio. Therefore, radio function registers can be read from or written into while the radio is in sleep mode. SPI IO Voltage References The SPI interfaces between MCU function and the radio and the IRQ and RST have a separate voltage reference VIO, enabling the radio function to directly interface with the MCU Page 8 of 85
P1.4/SCK
SCK
P1.3/nSS
nSS
4-Wire SPI Interface The 4-wire SPI communications interface consists of MOSI, MISO, SCK, and SS.
Document #: 001-07552 Rev. *B
[+] Feedback
CYRF69213
function, which operates at higher supply voltage. The internal SPIO pins between the MCU function and radio function should be connected with a regulated voltage of 3.3V (by setting [bit4] of Registers P13CR, P14CR, P15CR, and P16CR of the MCU function) and the internal 3.3V regulator of the MCU function should be turned on.
SPI Connects to External Devices The three SPI wires, MOSI, SCK, and SS are also drawn out of the package as external pins to allow the user to interface their own external devices (such as optical sensors and others) through SPI. The radio function also has its own SPI wires MISO and IRQ, which can be used to send data back to the MCU function or send an interrupt request to the MCU function. They can also be configured as GPIO pins.
Figure 6. SPI Transaction Format
Byte 1 Bit# Bit Name 7 DIR 6 INC [5:0] Address Byte 1+N [7:0] Data
CPU Architecture
This family of microcontrollers is based on a high-performance, 8-bit, Harvard-architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. Table 2. CPU Registers and Register Names Register Flags Program Counter Accumulator Stack Pointer Index Register Name CPU_F CPU_PC CPU_A CPU_SP CPU_X
The Accumulator Register (CPU_A) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. The Index Register (CPU_X) holds an offset value that is used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It can also be affected by the SWAP and ADD instructions. The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] is used to globally enable or disable interrupts. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (for example, AND, OR, XOR). See Table 19.
The 16-bit Program Counter Register (CPU_PC) allows for direct addressing of the full eight Kbytes of program memory space.
CPU Registers
Flags Register
The Flags Register can only be set or reset with logical instruction. Table 3. CPU Flags Register (CPU_F) [R/W]
Bit # Field Read/Write Default
- 0
7
6
Reserved - 0
5
- 0
4
XIO R/W 0
3
Super R 0
2
Carry RW 0
1
Zero RW 1
0
Global IE RW 0
Document #: 001-07552 Rev. *B
Page 9 of 85
[+] Feedback
CYRF69213
Table 3. CPU Flags Register (CPU_F) [R/W]
Bits 7:5 Bit 4 Reserved XIO Set by the user to select between the register banks 0 = Bank 0 1 = Bank 1 Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.) 0 = User Code 1 = Supervisor Code Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation 0 = No Carry 1 = Carry Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = Not Equal to Zero 1 = Equal to Zero Global IE Determines whether all interrupts are enabled or disabled 0 = Disabled 1 = Enabled
Bit 3
Bit 2
Bit 1
Bit 0
Note CPU_F register is only readable with explicit register address 0xF7. The OR F, expr and AND F, expr instructions must be used to set and clear the CPU_F bits
Accumulator Register Table 4. CPU Accumulator Register (CPU_A)
Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0
CPU Accumulator [7:0]
Bits 7:0 CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode
Index Register Table 5. CPU X Register (CPU_X)
Bit # Field Read/Write Default - 0 - 0 - 0 - 0 7 6 5 4 X [7:0] - 0 - 0 - 0 - 0 3 2 1 0
Bits 7:0 X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode
Stack Pointer Register Table 6. CPU Stack Pointer Register (CPU_SP)
Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 3 2 1 0
Stack Pointer [7:0] - 0 - 0 - 0 - 0 - 0
Document #: 001-07552 Rev. *B
Page 10 of 85
[+] Feedback
CYRF69213
Table 6. CPU Stack Pointer Register (CPU_SP)
Bits 7:0 Stack Pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack
CPU Program Counter High Register Table 7. CPU Program Counter High Register (CPU_PCH)
Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 3 2 1 0
Program Counter [15:8] - 0 - 0 - 0 - 0 - 0
Bits 7:0 Program Counter [15:8] 8-bit data value holds the higher byte of the program counter
CPU Program Counter Low Register Table 8. CPU Program Counter Low Register (CPU_PCL)
Bit # Field Read/Write Default - 0 - 0 - 0 7 6 5 4 3 2 1 0
Program Counter [7:0] - 0 - 0 - 0 - 0 - 0
Bits 7:0 Program Counter [7:0] 8-bit data value holds the lower byte of the program counter
Addressing Modes
Examples of the different addressing modes are discussed in this section and example code is given. Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources. Instructions using this addressing mode are two bytes in length. Table 9. Source Immediate Opcode Instruction Examples
ADD A, 7 ;In this case, the immediate value ;of 7 is added with the Accumulator, ;and the result is placed in the ;Accumulator. ;In this case, the immediate value ;of 8 is moved to the X register. ;In this case, the immediate value ;of 9 is logically ANDed with the F ;register and the result is placed ;in the F register.
Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 10.Source Direct Opcode Instruction Operand 1 Immediate Value Examples
ADD A, [7] ;In this case, the value in ;the RAM memory location at ;address 7 is added with the ;Accumulator, and the result ;is placed in the Accumulator. ;In this case, the value in ;the register space at address ;8 is moved to the X register.
Operand 1 Source Address
MOV
X,
REG[8]
MOV AND
X, F,
8 9
Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is
Document #: 001-07552 Rev. *B
Page 11 of 85
[+] Feedback
CYRF69213
specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 11.Source Indexed Opcode Instruction Examples
ADD A, [X+7] ;In this case, the value in ;the memory location at ;address X + 7 is added with ;the Accumulator, and the ;result is placed in the ;Accumulator. ;In this case, the value in ;the register space at ;address X + 8 is moved to ;the X register.
the instruction is the A register. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. Table 13.Destination Indexed Opcode Instruction Operand 1 Destination Index
Operand 1 Source Index Example
ADD [X+7], A ;In this case, the value in the ;memory location at address X+7 ;is added with the Accumulator, ;and the result is placed in ;the memory location at address ;x+7. The Accumulator is ;unchanged.
Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. Table 14.Destination Direct Immediate Opcode Instruction Examples
ADD [7], 5 ;In this case, value in the mem;ory location at address 7 is ;added to the immediate value of ;5, and the result is placed in ;the memory location at address 7. ;In this case, the immediate ;value of 6 is moved into the ;register space location at ;address 8.
MOV
X,
REG[X+8]
Destination Direct The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Table 12.Destination Direct Opcode Instruction Examples
ADD [7], A ;In this case, the value in ;the memory location at ;address 7 is added with the ;Accumulator, and the result ;is placed in the memory ;location at address 7. The ;Accumulator is unchanged. ;In this case, the Accumula;tor is moved to the regis;ter space location at ;address 8. The Accumulator ;is unchanged.
Operand 1 Destination Address
Operand 2 Immediate Value
Operand 1 Destination Address
MOV REG[8], 6
Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 15.Destination Indexed Immediate Opcode Instruction Operand 1 Destination Index Operand 2 Immediate Value
MOV
REG[8],
A
Destination Indexed The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for
Document #: 001-07552 Rev. *B
Page 12 of 85
[+] Feedback
CYRF69213
Examples
ADD [X+7], 5 ;In this case, the value in ;the memory location at ;address X+7 is added with ;the immediate value of 5, ;and the result is placed ;in the memory location at ;address X+7. ;In this case, the immedi;ate value of 6 is moved ;into the location in the ;register space at ;address X+8.
bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. Table 17.Source Indirect Post Increment Opcode Instruction Example
MVI A, [8] ;In this case, the value in the ;memory location at address 8 is ;an indirect address. The memory ;location pointed to by the indi;rect address is moved into the ;Accumulator. The indirect ;address is then incremented.
Operand 1 Source Address Address
MOV
REG[X+8],
6
Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Table 16.Destination Direct Source Direct Opcode Instruction Example
MOV [7], [8] ;In this case, the value in the ;memory location at address 8 is ;moved to the memory location at ;address 7.
Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Table 18.Destination Indirect Post Increment Opcode Instruction Example Operand 1 Destination Address Address
Operand 1 Destination Address
Operand 2 Source Address
Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two
MVI
[8],
A
;In this case, the value in ;the memory location at ;address 8 is an indirect ;address. The Accumulator is ;moved into the memory loca;tion pointed to by the indi;rect address. The indirect ;address is then incremented.
Document #: 001-07552 Rev. *B
Page 13 of 85
[+] Feedback
CYRF69213
Instruction Set Summary
The instruction set is summarized in Table 19 numerically and serves as a quick reference. If more information is needed, the
Opcode Hex Opcode Hex
Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the www.cypress.com web site).
Table 19.Instruction Set Summary Sorted Numerically by Opcode Order[1, 2]
Opcode Hex Cycles Cycles Cycles Bytes Bytes Instruction Format Flags Instruction Format Flags Bytes Instruction Format Flags
00 15 01 02 03 04 05 06 08 09 0A 0B 0C 0D 0E 10 11 12 13 14 15 16 18 19 1A 1B 1C 1D 1E 20 21 22 23 24 25 26 4 6 7 7 8 9 4 4 6 7 7 8 9 4 4 6 7 7 8 9 5 4 6 7 7 8 9 5 4 6 7 7 8 9
1 SSC 2 ADD A, expr 2 ADD A, [expr] 2 ADD A, [X+expr] 2 ADD [expr], A 2 ADD [X+expr], A 3 ADD [expr], expr 3 ADD [X+expr], expr 1 PUSH A 2 ADC A, expr 2 ADC A, [expr] 2 ADC A, [X+expr] 2 ADC [expr], A 2 ADC [X+expr], A 3 ADC [expr], expr 3 ADC [X+expr], expr 1 PUSH X 2 SUB A, expr 2 SUB A, [expr] 2 SUB A, [X+expr] 2 SUB [expr], A 2 SUB [X+expr], A 3 SUB [expr], expr 3 SUB [X+expr], expr 1 POP A 2 SBB A, expr 2 SBB A, [expr] 2 SBB A, [X+expr] 2 SBB [expr], A 2 SBB [X+expr], A 3 SBB [expr], expr 3 SBB [X+expr], expr 1 POP X 2 AND A, expr 2 AND A, [expr] 2 AND A, [X+expr] 2 AND [expr], A 2 AND [X+expr], A 3 AND [expr], expr 3 AND [X+expr], expr 1 ROMX 2 OR A, expr 2 OR A, [expr] 2 OR A, [X+expr] 2 OR [expr], A Z Z Z Z Z Z Z Z Z Z Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z
2D 2E 30 31 32 33 34 35 36 38 39 3A 3B 3C 3D
8 9 9 4 6 7 7 8 9 5 5 7 8 8 9
2 OR [X+expr], A 3 OR [expr], expr 3 OR [X+expr], expr 1 HALT 2 XOR A, expr 2 XOR A, [expr] 2 XOR A, [X+expr] 2 XOR [expr], A 2 XOR [X+expr], A 3 XOR [expr], expr 3 XOR [X+expr], expr 2 ADD SP, expr 2 CMP A, expr 2 CMP A, [expr] 2 CMP A, [X+expr] 3 CMP [expr], expr 3 CMP [X+expr], expr 2 MVI A, [ [expr]++ ] 2 MVI [ [expr]++ ], A 1 NOP 3 AND reg[expr], expr 3 AND reg[X+expr], expr 3 OR reg[expr], expr 3 OR reg[X+expr], expr 3 XOR reg[expr], expr 3 XOR reg[X+expr], expr 3 TST [expr], expr 3 TST [X+expr], expr 3 TST reg[expr], expr 3 TST reg[X+expr], expr 1 SWAP A, X 2 SWAP A, [expr] 2 SWAP X, [expr] 1 SWAP A, SP 1 MOV X, SP 2 MOV A, expr 2 MOV A, [expr] 2 MOV A, [X+expr] 2 MOV [expr], A 2 MOV [X+expr], A 3 MOV [expr], expr 3 MOV [X+expr], expr 2 MOV X, expr 2 MOV X, [expr] 2 MOV X, [X+expr]
Z Z Z Z Z Z Z Z Z Z
5A 5B 5C 5D 5E 60 61 62 63 64 65 66 67
5 4 4 6 7 5 6 8 9 4 7 8 4 7 8 4 7 8 4 7 8 4 4 4 4 4 4 7 8 4 4 7 8 7 8 5 5 5 5 5 7
2 MOV [expr], X 1 MOV A, X 1 MOV X, A 2 MOV A, reg[expr] 2 MOV A, reg[X+expr] 3 MOV [expr], [expr] 2 MOV reg[expr], A 2 MOV reg[X+expr], A 3 MOV reg[expr], expr 3 MOV reg[X+expr], expr 1 ASL A 2 ASL [expr] 2 ASL [X+expr] 1 ASR A 2 ASR [expr] 2 ASR [X+expr] 1 RLC A 2 RLC [expr] 2 RLC [X+expr] 1 RRC A 2 RRC [expr] 2 RRC [X+expr] 2 AND F, expr 2 OR F, expr 2 XOR F, expr 1 CPL A 1 INC A 1 INC X 2 INC [expr] 2 INC [X+expr] 1 DEC A 1 DEC X 2 DEC [expr] 2 DEC [X+expr] 3 LCALL 3 LJMP 1 RETI 1 RET 2 JMP 2 CALL 2 JZ 2 JNZ 2 JC 2 JNC 2 JACC 2 INDEX Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z Z Z
2F 10
5F 10
07 10
37 10
if (A=B) Z=1 if (A68 69 6A
0F 10
3E 10 3F 10 40 41 43 45 47 48 49 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 4 9 9 9 8 9 9 5 7 7 5 4 4 5 6 5 6 8 9 4 6 7
Z
6B 6C 6D
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7D 7F 8x Ax Bx Cx Dx Ex
42 10 44 10 46 10
17 10
4A 10
1F 10
7C 13 7E 10
27 10 28 11 29 2A 2B 2C 4 6 7 7
9x 11
Fx 13
Notes 1. Interrupt routines take 13 cycles before execution resumes at interrupt vector table. 2. The number of cycles required by an instruction is increased by one for instructions that span 256-byte boundaries in the Flash memory space.
Document #: 001-07552 Rev. *B
Page 14 of 85
[+] Feedback
CYRF69213
Memory Organization
Flash Program Memory Organization Figure 7. Program Memory Space with Interrupt Vector Table after reset 16-bit PC Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 Program execution begins here after a reset POR/LVD INT0 SPI Transmitter Empty SPI Receiver Full GPIO Port 0 GPIO Port 1 INT1 EP0 EP1 EP2 USB Reset USB Active 1-ms Interval Timer Programmable Interval Timer Reserved Reserved 16-bit Free Running Timer Wrap INT2 Reserved GPIO Port 2 Reserved Reserved Reserved Reserved Sleep Timer Program Memory begins here (if below interrupts not used, program memory can start lower)
0x1FFF
8 KB ends here
Document #: 001-07552 Rev. *B
Page 15 of 85
[+] Feedback
CYRF69213
Data Memory Organization The MCU function has 256 bytes of data RAM Figure 8. Data Memory Organization after reset 8-bit PSP Address 0x00 Stack begins here and grows upward.
Top of RAM Memory Flash
0xFF SROM The SROM holds code that is used to boot the part, calibrate circuitry, and perform Flash operations. (Table 20 lists the SROM functions.) The functions of the SROM may be accessed in normal user code or operating from Flash. The SROM exists in a separate memory space from user code. The SROM functions are accessed by executing the Supervisory System Call instruction (SSC), which has an opcode of 00h. Prior to executing the SSC, the M8C's accumulator needs to be loaded with the desired SROM function code from Table 20. Undefined functions will cause a HALT if called from user code. The SROM functions are executing code with calls; therefore, the functions require stack space. With the exception of Reset, all of the SROM functions have a parameter block in SRAM that must be configured before executing the SSC. Table 21 lists all possible parameter block variables. The meaning of each parameter, with regards to a specific SROM function, is described later in this section. Table 20.SROM Function Codes Function Code 00h 01h 02h 03h 05h 06h 07h Function Name SWBootReset ReadBlock WriteBlock EraseBlock EraseAll TableRead CheckSum Stack Space 0 7 10 9 11 3 3
This section describes the Flash block of the CYRF69213. Much of the user-visible Flash functionality, including programming and security, are implemented in the M8C Supervisory Read Only Memory (SROM). CYRF69213 Flash has an endurance of 1000 cycles and 10-year data retention. Flash Programming and Security All Flash programming is performed by code in the SROM. The registers that control the Flash programming are only visible to the M8C CPU when it is executing out of SROM. This makes it impossible to read, write, or erase the Flash by bypassing the security mechanisms implemented in the SROM. Customer firmware can only program the Flash via SROM calls. The data or code images can be sourced by way of any interface with the appropriate support firmware. This type of programming requires a `boot-loader'--a piece of firmware resident on the Flash. For safety reasons this boot-loader should not be overwritten during firmware rewrites. The Flash provides four auxiliary rows that are used to hold Flash block protection flags, boot time calibration values, configuration tables, and any device values. The routines for accessing these auxiliary rows are documented in the SROM section. The auxiliary rows are not affected by the device erase function. In-System Programming Most designs that include an CYRF69213 part will have a USB connector attached to the USB D+/D- pins on the device. These designs require the ability to program or reprogram a part through these two pins alone. CYRF69213 device enables this type of in-system programming by using the D+ and D- pins as the serial programming mode interface. This allows an external controller to cause the CYRF69213 part to enter serial programming mode and then to use the test queue to issue Flash access functions in the SROM. The programming protocol is not USB.
Two important variables that are used for all functions are KEY1 and KEY2. These variables are used to help discriminate between valid SSCs and inadvertent SSCs. KEY1 must always have a value of 3Ah, while KEY2 must have the same value as the stack pointer when the SROM function begins execution. This would be the Stack Pointer value when the SSC opcode is executed, plus three. If either of the keys do
Document #: 001-07552 Rev. *B
Page 16 of 85
[+] Feedback
CYRF69213
not match the expected values, the M8C will halt (with the exception of the SWBootReset function). The following code puts the correct value in KEY1 and KEY2. The code starts with a halt, to force the program to jump directly into the setup code and not run into it. halt SSCOP: mov [KEY1], 3ah mov X, SP mov A, X add A, 3 mov [KEY2], A Table 21.SROM Function Parameters Variable Name Key1/Counter/Return Code Key2/TMP BlockID Pointer Clock Mode Delay PCL SRAM Address 0,F8h 0,F9h 0,FAh 0,FBh 0,FCh 0,FDh 0,FEh 0,FFh
SWBootReset Function The SROM function, SWBootReset, is the function that is responsible for transitioning the device from a reset state to running user code. The SWBootReset function is executed whenever the SROM is entered with an M8C accumulator value of 00h; the SRAM parameter block is not used as an input to the function. This will happen, by design, after a hardware reset, because the M8C's accumulator is reset to 00h or when user code executes the SSC instruction with an accumulator value of 00h. The SWBootReset function will not execute when the SSC instruction is executed with a bad key value and a nonzero function code. A CYRF69213 device will execute the HALT instruction if a bad value is given for either KEY1 or KEY2. The SWBootReset function verifies the integrity of the calibration data by way of a 16-bit checksum, before releasing the M8C to run user code. ReadBlock Function The ReadBlock function is used to read 64 contiguous bytes from Flash--a block. The first thing this function does is to check the protection bits and determine if the desired BLOCKID is readable. If read protection is turned on, the ReadBlock function will exit, setting the accumulator and KEY2 back to 00h. KEY1 will have a value of 01h, indicating a read failure. If read protection is not enabled, the function will read 64 bytes from the Flash using a ROMX instruction and store the results in SRAM using an MVI instruction. The first of the 64 bytes will be stored in SRAM at the address indicated by the value of the POINTER parameter. When the ReadBlock completes successfully, the accumulator, KEY1, and KEY2 will all have a value of 00h. Table 23.ReadBlock Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h 0,FAh 0,FBh 3Ah Stack Pointer value, when SSC is executed Flash block number First of 64 addresses in SRAM where returned data should be stored Description
The SROM also features Return Codes and Lockouts. Return Codes Return codes aid in the determination of success or failure of a particular function. The return code is stored in KEY1's position in the parameter block. The CheckSum and TableRead functions do not have return codes because KEY1's position in the parameter block is used to return other data. Table 22.SROM Return Codes Return Code 00h 01h 02h 03h Success Function not allowed due to level of protection on block Software reset without hardware reset Fatal error, SROM halted Description
BLOCKID POINTER
WriteBlock Function Read, write, and erase operations may fail if the target block is read or write protected. Block protection levels are set during device programming. The EraseAll function overwrites data in addition to leaving the entire user Flash in the erase state. The EraseAll function loops through the number of Flash macros in the product, executing the following sequence: erase, bulk program all zeros, erase. After all the user space in all the Flash macros are erased, a second loop erases and then programs each protection block with zeros. SROM Function Descriptions All SROM functions are described in the following sections. The WriteBlock function is used to store data in the Flash. Data is moved 64 bytes at a time from SRAM to Flash using this function. The first thing the WriteBlock function does is to check the protection bits and determine if the desired BLOCKID is writable. If write protection is turned on, the WriteBlock function will exit, setting the accumulator and KEY2 back to 00h. KEY1 will have a value of 01h, indicating a write failure. The configuration of the WriteBlock function is straightforward. The BLOCKID of the Flash block, where the data is stored, must be determined and stored at SRAM address FAh. The SRAM address of the first of the 64 bytes to be stored in Flash must be indicated using the POINTER variable in the parameter block (SRAM address FBh). Finally, the CLOCK
Document #: 001-07552 Rev. *B
Page 17 of 85
[+] Feedback
CYRF69213
and DELAY values must be set correctly. The CLOCK value determines the length of the write pulse that will be used to store the data in the Flash. The CLOCK and DELAY values are dependent on the CPU speed. Refer to `Clocking' Section for additional information. Table 24.WriteBlock Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h 3Ah Stack Pointer value, when SSC is executed 8-KB Flash block number (00h-7Fh) 4-KB Flash block number (00h-3Fh) 3-KB Flash block number (00h-2Fh) First of 64 addresses in SRAM, where the data to be stored in Flash is located prior to calling WriteBlock Clock divider used to set the write pulse width For a CPU speed of 12 MHz set to 56h Description
ability to perform external reads and writes. For internal writes, IW is used. Internal reading is always permitted by way of the ROMX instruction. The ability to read by way of the SROM ReadBlock function is indicated by SR. The protection level is stored in two bits according to Table 26. These bits are bit packed into the 64 bytes of the protection block. Therefore, each protection block byte stores the protection level for four Flash blocks. The bits are packed into a byte, with the lowest numbered block's protection level stored in the lowest numbered bits. The first address of the protection block contains the protection level for blocks 0 through 3; the second address is for blocks 4 through 7. The 64th byte will store the protection level for blocks 252 through 255. Table 26.Protection Modes Mode 00b 01b 10b 11b Settings Description Marketing Unprotected Factory upgrade
BLOCKID 0,FAh
POINTER 0,FBh
SR ER EW IW Unprotected SR ER EW IW Read protect
CLOCK DELAY
0,FCh 0,FEh
SR ER EW IW Disable external Field upgrade write SR ER EW IW Disable internal write 6 5 4 3 2 Full protection
EraseBlock Function The EraseBlock function is used to erase a block of 64 contiguous bytes in Flash. The first thing the EraseBlock function does is to check the protection bits and determine if the desired BLOCKID is writable. If write protection is turned on, the EraseBlock function will exit, setting the accumulator and KEY2 back to 00h. KEY1 will have a value of 01h, indicating a write failure. The EraseBlock function is only useful as the first step in programming. Erasing a block will not cause data in a block to be one hundred percent unreadable. If the objective is to obliterate data in a block, the best method is to perform an EraseBlock followed by a WriteBlock of all zeros. To set up the parameter block for the EraseBlock function, correct key values must be stored in KEY1 and KEY2. The block number to be erased must be stored in the BLOCKID variable and the CLOCK and DELAY values must be set based on the current CPU speed. Table 25.EraseBlock Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h 3Ah Stack Pointer value when SSC is executed Flash block number (00h-7Fh) Clock divider used to set the erase pulse width For a CPU speed of 12 MHz set to 56h Description 7
1
0
Block n+3
Block n+2
Block n+1
Block n
The level of protection is only decreased by an EraseAll, which places zeros in all locations of the protection block. To set the level of protection, the ProtectBlock function is used. This function takes data from SRAM, starting at address 80h, and ORs it with the current values in the protection block. The result of the OR operation is then stored in the protection block. The EraseBlock function does not change the protection level for a block. Because the SRAM location for the protection data is fixed and there is only one protection block per Flash macro, the ProtectBlock function expects very few variables in the parameter block to be set prior to calling the function. The parameter block values that must be set, besides the keys, are the CLOCK and DELAY values. Table 27.ProtectBlock Parameters Name KEY1 KEY2 CLOCK DELAY Address 0,F8h 0,F9h 0,FCh 0,FEh 3Ah Stack Pointer value when SSC is executed Clock divider used to set the write pulse width For a CPU speed of 12 MHz set to 56h Description
BLOCKID 0,FAh CLOCK DELAY 0,FCh 0,FEh
EraseAll Function ProtectBlock Function The CYRF69213 device offers Flash protection on a block-by-block basis. Table 26 lists the protection modes available. In the table, ER and EW are used to indicate the The EraseAll function performs a series of steps that destroy the user data in the Flash macros and resets the protection block in each Flash macro to all zeros (the unprotected state). The EraseAll function does not affect the three hidden blocks above the protection block in each Flash macro. The first of Page 18 of 85
Document #: 001-07552 Rev. *B
[+] Feedback
CYRF69213
these four hidden blocks is used to store the protection table for its eight Kbytes of user data. The EraseAll function begins by erasing the user space of the Flash macro with the highest address range. A bulk program of all zeros is then performed on the same Flash macro, to destroy all traces of the previous contents. The bulk program is followed by a second erase that leaves the Flash macro in a state ready for writing. The erase, program, erase sequence is then performed on the next lowest Flash macro in the address space if it exists. Following the erase of the user space, the protection block for the Flash macro with the highest address range is erased. Following the erase of the protection block, zeros are written into every bit of the protection table. The next lowest Flash macro in the address space then has its protection block erased and filled with zeros. The end result of the EraseAll function is that all user data in the Flash is destroyed and the Flash is left in an unprogrammed state, ready to accept one of the various write commands. The protection bits for all user data are also reset to the zero state. The parameter block values that must be set, besides the keys, are the CLOCK and DELAY values. Table 28.EraseAll Parameters Name KEY1 KEY2 CLOCK DELAY Address 0,F8h 0,F9h 0,FCh 0,FEh 3Ah Stack Pointer value when SSC is executed Clock divider used to set the write pulse width For a CPU speed of 12 MHz set to 56h Description
The Revision ID is hard coded into the SROM. The Revision ID is discussed in more detail later in this section. An internal table holds alternate trim values for the device and returns a one-byte internal revision counter. The internal revision counter starts out with a value of zero and is incremented each time one of the other revision numbers is not incremented. It is reset to zero each time one of the other revision numbers is incremented. The internal revision count is returned in the CPU_A register. The CPU_X register will always be set to FFh when trim values are read. The BLOCKID value, in the parameter block, is used to indicate which table should be returned to the user. Only the three least significant bits of the BLOCKID parameter are used by the TableRead function for the CYRF69213. The upper five bits are ignored. When the function is called, it transfers bytes from the table to SRAM addresses F8h-FFh. The M8C's A and X registers are used by the TableRead function to return the die's Revision ID. The Revision ID is a 16-bit value hard coded into the SROM that uniquely identifies the die's design. Checksum Function The Checksum function calculates a 16-bit checksum over a user specifiable number of blocks, within a single Flash macro (Bank) starting from block zero. The BLOCKID parameter is used to pass in the number of blocks to calculate the checksum over. A BLOCKID value of 1 will calculate the checksum of only block 0, while a BLOCKID value of 0 will calculate the checksum of all 256 user blocks. The 16-bit checksum is returned in KEY1 and KEY2. The parameter KEY1 holds the lower eight bits of the checksum and the parameter KEY2 holds the upper eight bits of the checksum. The checksum algorithm executes the following sequence of three instructions over the number of blocks times 64 to be checksummed. romx add [KEY1], A adc [KEY2], 0 Table 30.Checksum Parameters Name KEY1 KEY2 BLOCKID Address 0,F8h 0,F9h 0,FAh 3Ah Stack Pointer value when SSC is executed Number of Flash blocks to calculate checksum on Description
TableRead Function The TableRead function gives the user access to part-specific data stored in the Flash during manufacturing. It also returns a Revision ID for the die (not to be confused with the Silicon ID). Table 29.Table Read Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h 3Ah Stack Pointer value when SSC is executed Table number to read Description
BLOCKID 0,FAh
Clocking
The CYRF69213 internal oscillator outputs two frequencies, the Internal 24-MHz Oscillator and the 32-KHz Low-power Oscillator. The Internal 24-MHz Oscillator is designed such that it may be trimmed to an output frequency of 24 MHz over temperature and voltage variation. With the presence of USB traffic, the Internal 24-MHz Oscillator can be set to precisely tune to USB timing requirements (24 MHz 1.5%). Without USB traffic, the Internal 24-MHz Oscillator accuracy is 24 MHz 5% (between
The table space for the CYRF69213 is simply a 64-byte row broken up into eight tables of eight bytes. The tables are numbered zero through seven. All user and hidden blocks in the CYRF69213 parts consist of 64 bytes. An internal table holds the Silicon ID and returns the Revision ID. The Silicon ID is returned in SRAM, while the Revision ID is returned in the CPU_A and CPU_X registers. The Silicon ID is a value placed in the table by programming the Flash and is controlled by Cypress Semiconductor Product Engineering.
Document #: 001-07552 Rev. *B
Page 19 of 85
[+] Feedback
CYRF69213
0-70C). No external components are required to achieve this level of accuracy. The internal low-speed oscillator of nominally 32 KHz provides a slow clock source for the CYRF69213 in suspend mode, particularly to generate a periodic wake-up interrupt and also to provide a clock to sequential logic during power-up and power-down events when the main clock is stopped. In addition, this oscillator can also be used as a clocking source for the Interval Timer clock (ITMRCLK) and Capture Timer clock (TCAPCLK). The 32-KHz Low-power Oscillator can operate in low-power mode or can provide a more accurate clock in normal mode. The Internal 32-KHz Low-power Oscillator accuracy ranges (between 0 - 70 C) as follows: 5V Normal mode: -8% to + 16% 5V LP mode: +12% to + 48% When using the 32-KHz oscillator the PITMRL/H should be read until two consecutive readings match before sending/receiving data. The following firmware example assumes the developer is interested in the lower byte of the PIT.
Read_PIT_counter: mov A, reg[PITMRL] mov [57h], A mov A, reg[PITMRL] mov [58h], A mov [59h], A mov A, reg{PITMRL] mov [60h], A ;;;Start comparison mov A, [60h] mov X, [59h] sub A, [59h] jz done mov A, [59h] mov X, [58h] sub A, [58h] jz done mov X, [57h] ;;;correct data is in memory location 57h done: mov [57h], X ret
Document #: 001-07552 Rev. *B
Page 20 of 85
[+] Feedback
CYRF69213
Figure 9. Clock Block Diagram
CPUCLK SEL
CLK_EXT MUX CLK_24MHz SCALE (divide by 2n, n = 0-5,7) CPU_CLK
EXT MUX 24 MHz CLK_USB
SEL
SCALE
SEL 0 0 1 1
SCALE X X 1 1
OUT 12 MHz 12 MHz EXT/2 EXT
LP OSC 32 KHz
CLK_32 KHz
Clock Architecture Description The CYRF69213 clock selection circuitry allows the selection of independent clocks for the CPU, USB, Interval Timers, and Capture Timers. The CPU clock, CPUCLK, can be sourced from the external crystal oscillator or the Internal 24-MHz Oscillator. The selected clock source can optionally be divided by 2n where n is 0-5,7 (see Table 34). USBCLK, which must be 12 MHz for the USB SIE to function properly, can be sourced by the Internal 24-MHz Oscillator or the external crystal oscillator. An optional divide-by-two allows the use of the 24-MHz source. The Interval Timer clock (ITMRCLK), can be sourced from the external crystal oscillator, the Internal 24-MHz Oscillator, the Document #: 001-07552 Rev. *B
Internal 32-KHz Low-power Oscillator, or from the timer capture clock (TCAPCLK). A programmable prescaler of 1, 2, 3, 4 then divides the selected source. The Timer Capture clock (TCAPCLK) can be sourced from the external crystal oscillator, Internal 24-MHz Oscillator, or the Internal 32-KHz Low-power Oscillator. When it is not being used by the external crystal oscillator, the CLKOUT pin can be driven from one of many sources. This is used for test and can also be used in some applications. The sources that can drive the CLKOUT are: * CLKIN after the optional EFTB filter * Internal 24-MHz Oscillator * Internal 32-KHz Low-power Oscillator * CPUCLK after the programmable divider Page 21 of 85
[+] Feedback
CYRF69213
Table 31.IOSC Trim (IOSCTR) [0x34] [R/W]
Bit # Field Read/Write Default R/W 0 7 6 foffset[2:0] R/W 0 R/W 0 R/W D R/W D 5 4 3 2 Gain[4:0] R/W D R/W D R/W D 1 0
The IOSC Calibrate register is used to calibrate the internal oscillator. The reset value is undefined, but during boot the SROM writes a calibration value that is determined during manufacturing test. This value should not require change during normal use. This is the meaning of `D' in the Default field Bits 7:5 foffset [2:0] This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and will be zero. Setting each of these bits causes the appropriate fine offset in oscillator frequency foffset bit 0 = 7.5 KHz foffset bit 1 = 15 KHz foffset bit 2 = 30 KHz Bits 4:0 Gain [4:0] The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases the gain of the offset input. This value sets the size of each offset step for the internal oscillator. Nominal gain change (KHz/offsetStep) at each bit, typical conditions (24-MHz operation): Gain bit 0 = -1.5 KHz Gain bit 1 = -3.0 KHz Gain bit 2 = -6 KHz Gain bit 3 = -12 KHz Gain bit 4 = -24 KHz
Table 32.LPOSC Trim (LPOSCTR) [0x36] [R/W]
Bit # Field Read/Write Default 7 32-KHz Low Power R/W 0 6 Reserved - D 5 4 3 2 1 0
32-KHz Bias Trim [1:0] R/W D R/W D R/W D
32-KHz Freq Trim [3:0] R/W D R/W D R/W D
This register is used to calibrate the 32-KHz Low-speed Oscillator. The reset value is undefined, but during boot the SROM writes a calibration value that is determined during manufacturing test. This value should not require change during normal use. This is the meaning of `D' in the Default field. If the 32-KHz Low-power bit needs to be written, care should be taken not to disturb the 32-KHz Bias Trim and the 32-KHz Freq Trim fields from their factory calibrated values Bit 7 32-KHz Low Power 0 = The 32-KHz Low-speed Oscillator operates in normal mode 1 = The 32-KHz Low-speed Oscillator operates in a low-power mode. The oscillator continues to function normally but with reduced accuracy Bit 6 Bits 5:4 Reserved 32-KHz Bias Trim [1:0] These bits control the bias current of the low-power oscillator. 0 0 = Mid bias 0 1 = High bias 1 0 = Reserved 1 1 = Reserved
Important Note Do not program the 32-KHz Bias Trim [1:0] field with the reserved 10b value, as the oscillator does not oscillate at all corner conditions with this setting Bits 3:0 32-KHz Freq Trim [3:0] These bits are used to trim the frequency of the low-power oscillator
Document #: 001-07552 Rev. *B
Page 22 of 85
[+] Feedback
CYRF69213
Table 33.CPU/USB Clock Config CPUCLKCR) [0x30] [R/W]
Bit # Field Read/Write Default Bit 7 Bit 6 - 0 Reserved USB CLK/2 Disable This bit only affects the USBCLK when the source is the external crystal oscillator. When the USBCLK source is the Internal 24-MHz Oscillator, the divide by two is always enabled 0 = USBCLK source is divided by two. This is the correct setting to use when the Internal 24-MHz Oscillator is used, or when the external source is used with a 24-MHz clock 1 = USBCLK is undivided. Use this setting only with a 12-MHz external clock USB CLK Select This bit controls the clock source for the USB SIE 0 = Internal 24-MHz Oscillator. With the presence of USB traffic, the Internal 24-MHz Oscillator can be trimmed to meet the USB requirement of 1.5% tolerance (see Table 35) 1 = External clock--Internal Oscillator is not trimmed to USB traffic. Proper USB SIE operation requires a 12-MHz or 24-MHz clock accurate to <1.5% Reserved 7 Reserved 6 USB CLK/2 Disable R/W 0 5 USB CLK Select R/W 0 - 0 - 0 4 3 Reserved - 0 - 0 2 1 0 CPUCLK Select R/W 0
Bit 5
Bits 4:1 Bit 0
CPU CLK Select 0 = Internal 24-MHz Oscillator 1 = External clock--External clock at CLKIN (P0.0) pin Note The CPU speed selection is configured using the OSC_CR0 Register (Table 34)
Document #: 001-07552 Rev. *B
Page 23 of 85
[+] Feedback
CYRF69213
Table 34.OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Bit # Field Read/Write Default
7 Reserved - 0 Reserved
6 - 0
5 No Buzz R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 CPU Speed [2:0] R/W 0
0 R/W 0
Sleep Timer [1:0]
Bits 7:6 Bit 5
No Buzz During sleep (the Sleep bit is set in the CPU_SCR Register--Table 38), the LVD and POR detection circuit is turned on periodically to detect any POR and LVD events on the VCC pin (the Sleep Duty Cycle bits in the ECO_TR are used to control the duty
cycle--Table 42). To facilitate the detection of POR and LVD events, the No Buzz bit is used to force the LVD and POR detection circuit to be continuously enabled during sleep. This results in a faster response to an LVD or POR event during sleep at the expense of a slightly higher than average sleep current 0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle 1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below Bits 4:3 Sleep Timer [1:0]
Sleep Timer Clock Frequency (Nominal) 512 Hz 64 Hz 8 Hz 1 Hz Sleep Period (Nominal) 1.95 ms 15.6 ms 125 ms 1 sec Watchdog Period (Nominal) 6 ms 47 ms 375 ms 3 sec
Sleep Timer [1:0] 00 01 10 11
Note Sleep intervals are approximate Bits 2:0 CPU Speed [2:0] The CYRF69213 may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the default CPU speed is one-eighth of the internal 24 MHz, or 3 MHz Regardless of the CPU Speed bit's setting, if the actual CPU speed is greater than 12 MHz, the 24-MHz operating requirements apply. An example of this scenario is a device that is configured to use an external clock, which is supplying a frequency of 20 MHz. If the CPU speed register's value is 0b011, the CPU clock will be 20 MHz. Therefore the supply voltage requirements for the device are the same as if the part was operating at 24 MHz. The operating voltage requirements are not relaxed until the CPU speed is at 12 MHz or less
CPU when Internal Oscillator is selected 3 MHz (Default) 6 MHz 12 MHz 24 MHz 1.5 MHz 750 KHz 187 KHz Reserved External Clock Clock In/8 Clock In/4 Clock In/2 Clock In/1 Clock In/16 Clock In/32 Clock In/128 Reserved
CPU Speed [2:0] 000 001 010 011 100 101 110 111
Important Note Correct USB operations require the CPU clock speed be at least 1.5 MHz or not less than USB clock/8. If the two clocks have the same source then the CPU clock divider should not be set to divide by more than 8. If the two clocks have different sources, care must be taken to ensure that the maximum ratio of USB Clock/CPU Clock can never exceed 8 across the full specification range of both clock sources
Document #: 001-07552 Rev. *B
Page 24 of 85
[+] Feedback
CYRF69213
Table 35.USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W]
Bit # Field Read/Write Default - 0 - 0 - 0 - 0 - 0 - 0 7 6 5 Reserved 4 3 2 1 Fine Tune Only R/W 0 0 USB Osclock Disable R/W 0
This register is used to trim the Internal 24-MHz Oscillator using received low-speed USB packets as a timing reference. The USB Osclock circuit is active when the Internal 24-MHz Oscillator provides the USB clock Bits 7:2 Reserved Bit 1 Fine Tune Only 0 = Enable 1 = Disable the oscillator lock from performing the course-tune portion of its retuning. The oscillator lock must be allowed to perform a course tuning in order to tune the oscillator for correct USB SIE operation. After the oscillator is properly tuned this bit can be set to reduce variance in the internal oscillator frequency that would be caused by course tuning USB Osclock Disable 0 = Enable. With the presence of USB traffic, the Internal 24-MHz Oscillator precisely tunes to 24 MHz 1.5% 1 = Disable. The Internal 24-MHz Oscillator is not trimmed based on USB packets. This setting is useful when the internal oscillator is not sourcing the USBSIE clock
Bit 0
Table 36.Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Bit # Field Read/Write Default Bits 7:6 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 1 2 R/W 1 1 R/W 0 0 R/W 0
TCAPCL Divider
TCAPCLK Select
ITMRCLK Divider
ITMRCLK Select
TCAPCLK Divider TCAPCLK Divider controls the TCAPCLK divisor 00 = Divide by 2 01 = Divide by 4 10 = Divide by 6 11 = Divide by 8 TCAPCLK Select The TCAPCLK Select field controls the source of the TCAPCLK 0 0 = Internal 24-MHz Oscillator 0 1 = External crystal oscillator--external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled, CLKIN input if the external crystal oscillator is disabled (the XOSC Enable bit of the CLKIOCR Register is cleared--Table 37) 1 0 = Internal 32-KHz Low-power Oscillator 1 1 = TCAPCLK Disabled
Bits 5:4
Note The 1024-s interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency will cause a corresponding change in the 1024-s interval timer frequency Bits 3:2 ITMRCLK Divider ITMRCLK Divider controls the ITMRCLK divisor. 0 0 = Divider value of 1 0 1 = Divider value of 2 1 0 = Divider value of 3 1 1 = Divider value of 4 Bits 1:0 ITMRCLK Select 0 0 = Internal 24-MHz Oscillator 0 1 = External crystal oscillator - external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled, CLKIN input if the external crystal oscillator is disabled 1 0 = Internal 32-KHz Low-power Oscillator 1 1 = TCAPCLK
Document #: 001-07552 Rev. *B
Page 25 of 85
[+] Feedback
CYRF69213
Interval Timer Clock (ITMRCLK) The Interval Timer Clock (ITMRCLK) can be sourced from the external crystal oscillator, the Internal 24-MHz oscillator, the internal 32-KHz low-power oscillator, or the timer capture clock. A programmable prescaler of 1, 2, 3, or 4 then divides the selected source. The 12-bit Programmable Interval Timer is a simple down counter with a programmable reload value. It provides a 1-s resolution by default. When the down counter reaches zero, the next clock is spent reloading. The reload value can be read and written while the counter is running, but care should be taken to ensure that the counter does not unintentionally reload while the 12-bit reload value is only partially stored--for example, between the two writes of the 12-bit value. The programmable interval timer generates an interrupt to the CPU on each reload. The parameters to be set will appear on the device editor view of PSoC Designer once you place the CYRF69213 Timer User Module. The parameters are PITIMER_Source and PITIMER_Divider. The PITIMER_Source is the clock to the
timer and the PITMER_Divider is the value the clock is divided by. The interval register (PITMR) holds the value that is loaded into the PIT counter on terminal count. The PIT counter is a down counter. The Programmable Interval Timer resolution is configurable. For example: TCAPCLK divide by x of CPU clock (for example TCAPCLK divide by 2 of a 24-MHz CPU clock will give a frequency of 12 MHz) ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 s) Timer Capture Clock (TCAPCLK) The Timer Capture clock can be sourced from the external crystal oscillator, internal 24-MHz oscillator or the Internal 332-KHz low-power oscillator. A programmable prescaler of 2, 4, 6, or 8 then divides the selected source.
Figure 10. Programmable Interval Timer Block Diagram
S y s te m C lo c k
C o n fig u ra tio n S ta tu s a n d C o n tro l
1 2 -b it re lo a d v a lu e
C lo c k T im e r
1 2 -b it d o w n c o u n te r
1 2 -b it re lo a d c o u n te r
In te rru p t C o n tro lle r
Document #: 001-07552 Rev. *B
Page 26 of 85
[+] Feedback
CYRF69213
Figure 11. Timer Capture Block Diagram
S yste m C lo ck
C o n fig u ra tio n S ta tu s a n d C o n tro l
C a p tim e r C lo ck
1 6 -b it co u n te r
P re sca le M u x
C a p tu re R e g iste rs
1m s tim e r
O ve rflo w In te rru p t C a p tu re 0 In t C a p tu re 1 In t
In te rru p t C o n tro lle r
Table 37.Clock I/O Config (CLKIOCR) [0x32] [R/W]
Bit # Field Read/Write Default Bits 7:2 Bits 1:0 - 0 Reserved CLKOUT Select 0 0 = Internal 24-MHz Oscillator 0 1 = External crystal oscillator - external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled, CLKIN input if the external oscillator is disabled 1 0 = Internal 32-KHz Low-power Oscillator 1 1 = CPUCLK - 0 - 0 7 6 5 Reserved 0 0 0 4 3 2 1 R/W 0 0 R/W 0
CLKOUT Select
CPU Clock During Sleep Mode When the CPU enters sleep mode the CPUCLK Select (Bit [0], Table 33) is forced to the internal oscillator, and the oscillator is stopped. When the CPU comes out of sleep mode it is running on the internal oscillator. The internal oscillator recovery time is three clock cycles of the Internal 32-KHz Low-power Oscillator. If the system requires the CPU to run off the external clock after awakening from sleep mode, firmware will need to switch the clock source for the CPU.
initiated, all registers are restored to their default states and all interrupts are disabled. The occurrence of a reset is recorded in the System Status and Control Register (CPU_SCR). Bits within this register record the occurrence of POR and WDR Reset respectively. The firmware can interrogate these bits to determine the cause of a reset. The microcontroller resumes execution from Flash address 0x0000 after a reset. The internal clocking mode is active after a reset, until changed by user firmware. Note The CPU clock defaults to 3 MHz (Internal 24-MHz Oscillator divide-by-8 mode) at POR to guarantee operation at the low VCC that might be present during the supply ramp.
Reset
The microcontroller supports two types of resets: Power-on Reset (POR) and Watchdog Reset (WDR). When reset is
Document #: 001-07552 Rev. *B
Page 27 of 85
[+] Feedback
CYRF69213
Table 38.System Status and Control Register (CPU_SCR) [0xFF] [R/W]
Bit # Field Read/Write Default Bit 7 7 GIES R 0 6 Reserved - 0 5 WDRS R/C[3] 0 4 PORS R/C[3] 1 3 Sleep R/W 0 - 0 2 Reserved - 0 1 0 Stop R/W 0
The bits of the CPU_SCR register are used to convey status and control of events for various functions of an CYRF69213 device GIES The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged. The GIES bit is a legacy bit, which was used to provide the ability to read the GIE bit of the CPU_F register. However, the CPU_F register is now readable. When this bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn, indicates that the microprocessor will service interrupts 0 = Global interrupts disabled 1 = Global interrupt enabled Reserved WDRS The WDRS bit is set by the CPU to indicate that a WDR event has occurred. The user can read this bit to determine the type of reset that has occurred. The user can clear but not set this bit 0 = No WDR 1 = A WDR event has occurred PORS The PORS bit is set by the CPU to indicate that a POR event has occurred. The user can read this bit to determine the type of reset that has occurred. The user can clear but not set this bit 0 = No POR 1 = A POR event has occurred. (Note that WDR events will not occur until this bit is cleared) SLEEP Set by the user to enable CPU sleep state. CPU will remain in sleep mode until any interrupt is pending. The Sleep bit is covered in more detail in the Sleep Mode section 0 = Normal operation 1 = Sleep Reserved STOP This bit is set by the user to halt the CPU. The CPU will remain halted until a reset (WDR, POR, or external reset) has taken place. If an application wants to stop code execution until a reset, the preferred method would be to use the HALT instruction rather than writing to this bit 0 = Normal CPU operation 1 = CPU is halted (not recommended)
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2:1 Bit 0
Power-on Reset POR occurs every time the power to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typically 50 mV of hysteresis during the power-on transient. Bit 4 of the System Status and Control Register (CPU_SCR) is set to record this event (the register contents are set to 00010000 by the POR). After a POR, the microprocessor is held off for approximately 20 ms for the VCC supply to stabilize before executing the first instruction at address 0x00 in the Flash. If the VCC voltage drops below the POR downward supply trip point, POR is reasserted. The VCC supply needs to ramp linearly from 0 to 4V in 0 to 200 ms. Important The PORS status bit is set at POR and can only be cleared by the user. It cannot be set by firmware. Watchdog Timer Reset The user has the option to enable the WDT. The WDT is enabled by clearing the PORS bit. Once the PORS bit is
cleared, the WDT cannot be disabled. The only exception to this is if a POR event takes place, which will disable the WDT. The sleep timer is used to generate the sleep time period and the Watchdog time period. The sleep timer is clocked by the Internal 32-KHz Low-power Oscillator system clock. The user can program the sleep time period using the Sleep Timer bits of the OSC_CR0 Register (Table 34). When the sleep time elapses (sleep timer overflows), an interrupt to the Sleep Timer Interrupt Vector will be generated. The Watchdog Timer period is automatically set to be three counts of the Sleep Timer overflows. This represents between two and three sleep intervals depending on the count in the Sleep Timer at the previous WDT clear. When this timer reaches three, a WDR is generated. The user can either clear the WDT, or the WDT and the Sleep Timer. Whenever the user writes to the Reset WDT Register (RES_WDT), the WDT will be cleared. If the data that is written is the hex value 0x38, the Sleep Timer will also be cleared at the same time.
Note 3. C = Clear. This bit can only be cleared by the user and cannot be set by firmware
Document #: 001-07552 Rev. *B
Page 28 of 85
[+] Feedback
CYRF69213
Table 39.Reset Watchdog Timer (RESWDT) [0xE3] [W]
Bit # Field Read/Write Default Bits 7:0 W 0 W 0 W 0 7 6 5 4 W 0 3 W 0 2 W 0 1 W 0 0 W 0 Reset Watchdog Timer [7:0]
Any write to this register will clear Watchdog Timer, a write of 0x38 will also clear the Sleep Timer Reset Watchdog Timer [7:0]
Sleep Mode
The CPU can only be put to sleep by the firmware. This is accomplished by setting the Sleep bit in the System Status and Control Register (CPU_SCR). This stops the CPU from executing instructions, and the CPU will remain asleep until an interrupt comes pending, or there is a reset event (either a Power-on Reset, or a Watchdog Timer Reset). The Low-voltage Detection circuit (LVD) drops into fully functional power-reduced states, and the latency for the LVD is increased. The actual latency can be traded against power consumption by changing the Sleep Duty Cycle field of the ECO_TR Register. The Internal 32-KHz Low-speed Oscillator remains running. Prior to entering suspend mode, firmware can optionally configure the 32-KHz Low-speed Oscillator to operate in a low-power mode to help reduce the overall power consumption (using Bit 7, Table 32). This will help save approximately 5 A; however, the trade off is that the 32-KHz Low-speed Oscillator will be less accurate. All interrupts remain active. Only the occurrence of an interrupt will wake the part from sleep. The Stop bit in the System Status and Control Register (CPU_SCR) must be cleared for a part to resume out of sleep. The Global Interrupt Enable bit of the CPU Flags Register (CPU_F) does not have any effect. Any unmasked interrupt will wake the system up. As a result, any interrupts not intended for waking must be disabled through the Interrupt Mask Registers. When the CPU enters sleep mode the CPUCLK Select (Bit 1, Table 33) is forced to the Internal Oscillator. The internal oscillator recovery time is three clock cycles of the Internal 32-KHz Low-power Oscillator. The Internal 24-MHz Oscillator restarts immediately on exiting Sleep mode. If an external clock is used, firmware will need to switch the clock source for the CPU. On exiting sleep mode, once the clock is stable and the delay time has expired, the instruction immediately following the
sleep instruction is executed before the interrupt service routine (if enabled). The Sleep interrupt allows the microcontroller to wake up periodically and poll system components while maintaining very low average power consumption. The Sleep interrupt may also be used to provide periodic interrupts during non-sleep modes. Sleep Sequence The SLEEP bit is an input into the sleep logic circuit. This circuit is designed to sequence the device into and out of the hardware sleep state. The hardware sequence to put the device to sleep is shown in Figure 12 and is defined as follows. 1. Firmware sets the SLEEP bit in the CPU_SCR0 register. The Bus Request (BRQ) signal to the CPU is immediately asserted. This is a request by the system to halt CPU operation at an instruction boundary. The CPU samples BRQ on the positive edge of CPUCLK. 2. Due to the specific timing of the register write, the CPU issues a Bus Request Acknowledge (BRA) on the following positive edge of the CPU clock. The sleep logic waits for the following negative edge of the CPU clock and then asserts a system-wide Power Down (PD) signal. In Figure 12 the CPU is halted and the system-wide power down signal is asserted. 3. The system-wide PD (power down) signal controls several major circuit blocks: The Flash memory module, the internal 24-MHz oscillator, the EFTB filter and the bandgap voltage reference. These circuits transition into a zero power state. The only operational circuits on chip are the Low Power oscillator, the bandgap refresh circuit, and the supply voltage monitor (POR/LVD) circuit. Note To achieve the lowest possible power consumption during suspend/sleep, the following conditions must be observed in addition to considerations for the sleep timer. * All GPIOs must be set to outputs and driven low * The USB pins P1.0 and P1.1 should be configured as inputs with their pull ups enabled.
Document #: 001-07552 Rev. *B
Page 29 of 85
[+] Feedback
CYRF69213
Figure 12. Sleep Timing
Firmware write to SCR SLEEP bit causes an immediate BRQ
CPU captures BRQ on next CPUCLK edge
CPU responds with a BRA
On the falling edge of CPUCLK, PD is asserted. The 24/48 MHz system clock is halted; the Flash and bandgap are powered down
CPUCLK IOW SLEEP BRQ BRA PD
Wakeup Sequence Once asleep, the only event that can wake the system up is an interrupt. The global interrupt enable of the CPU flag register does not need to be set. Any unmasked interrupt will wake the system up. It is optional for the CPU to actually take the interrupt after the wakeup sequence. The wakeup sequence is synchronized to the 32-KHz clock for purposes of sequencing a startup delay, to allow the Flash memory module enough time to power up before the CPU asserts the first read access. Another reason for the delay is to allow the oscillator, Bandgap, and LVD/POR circuits time to settle before actually being used in the system. As shown in Figure 13, the wakeup sequence is as follows: 1. The wakeup interrupt occurs and is synchronized by the negative edge of the 32-KHz clock. 2. At the following positive edge of the 32-KHz clock, the system-wide PD signal is negated. The Flash memory module, internal oscillator, EFTB, and bandgap circuit are all powered up to a normal operating state. 3. At the following positive edge of the 32-KHz clock, the current values for the precision POR and LVD have settled and are sampled. 4. At the following negative edge of the 32-KHz clock (after about 15 s nominal), the BRQ signal is negated by the sleep logic circuit. On the following CPUCLK, BRA is negated by the CPU and instruction execution resumes. Note that in Figure 13 fixed function blocks, such as Flash, internal oscillator, EFTB, and bandgap, have about 15 s start up. The wakeup times (interrupt to CPU operational) will range from 75 s to 105 s.
Document #: 001-07552 Rev. *B
Page 30 of 85
[+] Feedback
CYRF69213
Figure 13. Wakeup Timing
Sleep Timer or GPIO interrupt occurs
Interrupt is double sampled by 32K clock and PD is negated to system
CPU is restarted after 90 ms (nominal)
CLK32K INT SLEEP PD BANDGAP LVD PPOR ENABLE SAMPLE SAMPLE LVD/POR CPUCLK/ 24MHz (Not to Scale) BRQ BRA CPU
Document #: 001-07552 Rev. *B
Page 31 of 85
[+] Feedback
CYRF69213
Low-Voltage Detect Control
Table 40.Low-voltage Control Register (LVDCR) [0x1E3] [R/W]
Bit # Field Read/Write Default Bits 7:6 Bits 5:4 - 0 Reserved PORLEV[1:0] This field controls the level below which the precision power-on-reset (PPOR) detector generates a reset 0 0 = 2.7V Range (trip near 2.6V) 0 1 = 3V Range (trip near 2.9V) 1 0 = 5V Range, >4.75V (trip near 4.65V) 1 1 = PPOR will not generate a reset, but values read from the Voltage Monitor Comparators Register (Table 41) give the internal PPOR comparator state with trip point set to the 3V range setting Reserved VM[2:0] This field controls the level below which the low-voltage-detect trips--possibly generating an interrupt and the level at which the Flash is enabled for operation. LVD Trip Point (V) VM[2:0]
000 001 010 011 100 101 110 111
7 Reserved
6 - 0
5 PORLEV[1:0] R/W 0
4 R/W 0
3 Reserved - 0
2 R/W 0
1 VM[2:0] R/W 0
0 R/W 0
This register controls the configuration of the Power-on Reset/Low-voltage Detection block
Bit 3 Bits 2:0
Min.
2.681 2.892 2.991 3.102 4.439 4.597 4.680 4.766
Typical
2.70 2.92 3.02 3.13 4.48 4.64 4.73 4.82
Max.
2.735 2.950 3.053 3.164 4.528 4.689 4.774 4.862
POR Compare State Table 41.Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]
Bit # Field Read/Write Default Bits 7:2 Bit 1 - 0 Reserved LVD This bit is set to indicate that the low-voltage-detect comparator has tripped, indicating that the supply voltage has gone below the trip point set by VM[2:0] (See Table 40) 0 = No low-voltage-detect event 1 = A low-voltage-detect has tripped PPOR This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is below the trip point set by PORLEV[1:0] 0 = No precision-power-on-reset event 1 = A precision-power-on-reset event has tripped - 0 - 0 7 6 5 Reserved - 0 - 0 - 0 4 3 2 1 LVD R 0 0 PPOR R 0
This read-only register allows reading the current state of the Low-voltage-Detection and Precision-Power-On-Reset comparators
Bit 0
Document #: 001-07552 Rev. *B
Page 32 of 85
[+] Feedback
CYRF69213
ECO Trim Register Table 42.ECO (ECO_TR) [0x1EB] [R/W]
Bit # Field Read/Write Default Bits 7:6 7 R/W 0 6 R/W 0 5 - 0 4 - 0 3 Reserved - 0 - 0 - 0 - 0 2 1 0
Sleep Duty Cycle [1:0]
This register controls the ratios (in numbers of 32-KHz clock periods) of `on' time versus `off' time for LVD and POR detection circuit Sleep Duty Cycle [1:0] 0 0 = 128 periods of the Internal 32-KHz Low-speed Oscillator 0 1 = 512 periods of the Internal 32-KHz Low-speed Oscillator 1 0 = 32 periods of the Internal 32-KHz Low-speed Oscillator 1 1 = 8 periods of the Internal 32-KHz Low-speed Oscillator
General-Purpose I/O Ports
The general-purpose I/O ports are discussed in the following sections. Port Data Registers Table 43.P0 Data Register (P0DATA)[0x00] [R/W]
Bit # Field Read/Write Default 7 P0.7 R/W 0 6 Reserved R/W 0 5 Reserved R/W 0 4 P0.4/INT2 R/W 0 3 P0.3/INT1 R/W 0 2 P0.2/INT0 R/W 0 1 Reserved R/W 0 0 Reserved R/W 0
This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 0 pins Bit 7 P0.7 Data Bits 6:5 Bits 4:2 Reserved The use of the pins as the P0.6-P0.5 GPIOs and the alternative functions exist in the CYRF69213 P0.4-P0.2 Data/INT2 - INT0 In addition to their use as the P0.4-P0.2 GPIOs, these pins can also be used for the alternative functions as the Interrupt pins (INT0-INT2). To configure the P0.4-P0.2 pins, refer to the P0.2/INT0-P0.4/INT2 Configuration Register (Table 46) The use of the pins as the P0.4-P0.2 GPIOs and the alternative functions exist in the CYRF69213 Reserved Reserved
Bit 1 Bit 0
Table 44.P1 Data Register (P1DATA) [0x01] [R/W]
Bit # Field Read/Write Default 7 P1.7 R/W 0 6 P1.6/SMISO R/W 0 5 P1.5/SMOSI R/W 0 4 P1.4/SCLK R/W 0 3 P1.3/SSEL R/W 0 2 P1.2/VREG R/W 0 1 P1.1/D- R/W 0 0 P1.0/D+ R/W 0
Document #: 001-07552 Rev. *B
Page 33 of 85
[+] Feedback
CYRF69213
Table 44.P1 Data Register (P1DATA) [0x01] [R/W]
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 1 pins Bit 7 P1.7 Data Bits 6:3 P1.6-P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL) In addition to their use as the P1.6-P1.3 GPIOs, these pins can also be used for the alternative function as the SPI interface pins. To configure the P1.6-P1.3 pins, refer to the P1.3-P1.6 Configuration Register (Table 51) The use of the pins as the P1.6-P1.3 GPIOs and the alternative functions exist in all the CYRF69213 parts P1.2/VREG A 1-F min, 2-F max capacitor is required on VREG output. P1.1-P1.0/D- and D+ When USB mode is disabled (Bit 7 in Table 76 is clear), the P1.1 and P1.0 bits are used to control the state of the P1.0 and P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D- and D+ pins, respectively. If the USB Force State bit (Bit 0 in Table 74) is set, the state of the D- and D+ pins can be controlled by writing to the D- and D+ bits
Bit 2 Bits 1:0
Table 45.P2 Data Register (P2DATA) [0x02] [R/W]
Bit # Field Read/Write Default 0 0 0 7 6 5 Reserved 0 0 0 R/W 0 4 3 2 1 P2.1-P2.0 R/W 0 0
This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 2 pins Bits 7:2 Reserved Data [7:2] Bits 1:0 P2 Data [1:0]
GPIO Port Configuration All the GPIO configuration registers have common configuration controls. The following are the bit definitions of the GPIO configuration registers. Int Enable When set, the Int Enable bit allows the GPIO to generate interrupts. Interrupt generate can occur regardless of whether the pin is configured for input or output. All interrupts are edge sensitive, however for any interrupt that is shared by multiple sources (that is, Ports 2, 3, and 4) all inputs must be deasserted before a new interrupt can occur. When clear, the corresponding interrupt is disabled on the pin. It is possible to configure GPIOs as outputs, enable the interrupt on the pin and then to generate the interrupt by driving the appropriate pin state. This is useful in test and may have value in applications as well. Int Act Low When set, the corresponding interrupt is active on the falling edge. When clear, the corresponding interrupt is active on the rising edge. TTL Thresh When set, the input has TTL threshold. When clear, the input has standard CMOS threshold. High Sink When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA. On the CYRF69213, only the P1.7-P1.3 have 50-mA sink drive capability. Other pins have 8-mA sink drive capability. Open Drain When set, the output on the pin is determined by the Port Data Register. If the corresponding bit in the Port Data Register is set, the pin is in high-impedance state. If the corresponding bit in the Port Data Register is clear, the pin is driven low. When clear, the output is driven LOW or HIGH. Pull-up Enable When set the pin has a 7K pull up to VCC (or VREG for ports with V3.3 enabled). When clear, the pull up is disabled. Output Enable When set, the output driver of the pin is enabled. When clear, the output driver of the pin is disabled. For pins with shared functions there are some special cases. VREG Output/SPI Use The P1.2 (VREG), P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6 (SMISO) pins can be used for their dedicated functions or for GPIO. To enable the pin for GPIO, clear the corresponding VREG Output or SPI Use bit. The SPI function controls the output enable for its dedicated function pins when their GPIO enable bit is clear.
Document #: 001-07552 Rev. *B
Page 34 of 85
[+] Feedback
CYRF69213
3.3V Drive The P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6 (SMISO) pins have an alternate voltage source from the voltage regulator. If the 3.3V Drive bit is set a high level is driven from the voltage regulator instead of from VCC.
Setting the 3.3V Drive bit does not enable the voltage regulator. That must be done explicitly by setting the VREG Enable bit in the VREGCR Register (Table 75).
Figure 14. Block Diagram of a GPIO
VE RG 3.3V D rive
VC C
P ull-U E p nable O utput E nable VE RG O pen D rain PD ort ata VC C RP U DO ata ut G IO P P IN
HS igh ink
VE GD RG N D In ata T LT T hreshold
Table 46.P0.2/INT0-P0.4/INT2 Configuration (P02CR-P04CR) [0x07-0x09] [R/W]
Bit # Field Read/Write Default - 0 7 Reserved - 0 6 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 Reserved - 0
V CG D N C
2 Open Drain R/W 0
1 R/W 0
0 R/W 0
Pull-up Enable Output Enable
These registers control the operation of pins P0.2-P0.4, respectively. These pins are shared between the P0.2-P0.4 GPIOs and the INT0-INT2. These registers exist in all CYRF69213 parts. The INT0-INT2 interrupts are different than all the other GPIO interrupts. These pins are connected directly to the interrupt controller to provide three edge-sensitive interrupts with independent interrupt vectors. These interrupts occur on a rising edge when Int act Low is clear and on a falling edge when Int act Low is set. These pins are enabled as interrupt sources in the interrupt controller registers (Table 72 and Table 70) To use these pins as interrupt inputs configure them as inputs by clearing the corresponding Output Enable. If the INT0-INT2 pins are configured as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the P0.2, P0.3 and P0.4 data bits in the P0 Data Register Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and Pull-up Enable bits control the behavior of the pin The P0.2/INT0-P0.4/INT2 pins are individually configured with the P02CR (0x07), P03CR (0x08), and P04CR (0x09), respectively. Note Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these interrupt sources, it is best to follow the following procedure: 1. Disable interrupt source 2. Configure interrupt source 3. Clear any pending interrupts from the source 4. Enable interrupt source
Document #: 001-07552 Rev. *B
Page 35 of 85
[+] Feedback
CYRF69213
Table 47.P0.7 Configuration (P07CR) [0x0C] [R/W]
Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 Reserved - 0 2 Open Drain R/W 0 1 R/W 0 0 R/W 0
Pull-up Enable Output Enable
This register controls the operation of pin P0.7.
Table 48.P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
Bit # Field Read/Write Default 7 Reserved R/W 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 - 0 4 3 Reserved - 0 - 0 2 1 Reserved - 0 0 Output Enable R/W 0
This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as a PS2 interface or a GPIO. See Table 76 for information on enabling USB. When USB is enabled, none of the controls in this register have any effect on the P1.0 pin Note The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high Bit 1 PS/2 Pull-up Enable 0 = Disable the 5K-ohm pull-up resistors 1 = Enable 5K-ohm pull-up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D-) pins as a PS2 style interface
Table 49.P1.1/D- Configuration (P11CR) [0x0E] [R/W]
Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 - 0 4 Reserved - 0 3 2 Open Drain R/W 0 1 Reserved - 0 0 Output Enable R/W 0
This register controls the operation of the P1.1 (D-) pin when the USB interface is not enabled, allowing the pin to be used as a PS2 interface or a GPIO. See Table 76 for information on enabling USB. When USB is enabled, none of the controls in this register have any effect on the P1.1 pin. When USB is disabled, the 5-Kohm pull-up resistor on this pin can be enabled by the PS/2 Pull-up Enable bit of the P10CR Register (Table 48) Note There is no 2-mA sourcing capability on this pin. The pin can only sink 5 mA at VOL3
Table 50.P1.2 Configuration (P12CR) [0x0F] [R/W]
Bit # Field Read/Write Default Bit 7 7 CLK Output R/W 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Threshold R/W 0 3 Reserved - 0 2 Open Drain R/W 0 1 R/W 0 0 R/W 0
Pull-up Enable Output Enable
This register controls the operation of the P1.2 CLK Output 0 = The internally selected clock is not sent out onto P1.2 pin 1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin
Document #: 001-07552 Rev. *B
Page 36 of 85
[+] Feedback
CYRF69213
Table 51.P1.3 Configuration (P13CR) [0x10] [R/W]
Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 3.3V Drive R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 R/W 0 0 R/W 0
Pull-up Enable Output Enable
This register controls the operation of the P1.3 pin. This register exists in all CYRF69213 parts The P1.3 GPIO's threshold is always set to TTL When the SPI hardware is enabled, the output enable and output state of the pin is controlled by the SPI circuitry. When the SPI hardware is disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain, and Pull-up Enable control the behavior of the pin The 50-mA sink drive capability is only available in the CY7C638xx.
Table 52.P1.4-P1.6 Configuration (P14CR-P16CR) [0x11-0x13] [R/W]
Bit # Field Read/Write Default 7 SPI Use R/W 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 3.3V Drive R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 R/W 0 0 R/W 0
Pull-up Enable Output Enable
These registers control the operation of pins P1.4-P1.6, respectively The P1.4-P1.6 GPIO's threshold is always set to TTL When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by the SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain, and Pull-up Enable control the behavior of the pin Bit 7 SPI Use 0 = Disable the SPI alternate function. The pin is used as a GPIO 1 = Enable the SPI function. The SPI circuitry controls the output of the pin Important Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 56) When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input/output direction of pins P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input
Table 53. P1.7 Configuration (P17CR) [0x14] [R/W]
Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 R/W 1 0 R/W 0
Pull-up Enable Output Enable
This register controls the operation of pin P1.7. This register only exists in CY7C638xx The 50-mA sink drive capability is only available in the CY7C638xx. The P1.7 GPIO's threshold is always set to TTL
Table 54.P2 Configuration (P2CR) [0x15] [R/W]
Bit # Field Read/Write Default 7 Reserved - 0 6 Int Enable R/W 0 5 Int Act Low R/W 0 4 TTL Thresh R/W 0 3 High Sink R/W 0 2 Open Drain R/W 0 1 R/W 0 0 R/W 0
Pull-up Enable Output Enable
This register only exists in CY7C638xx. This register controls the operation of pins P2.0-P2.1. In the CY7C638xx, only 8-mA sink drive capability is available on this pin regardless of the setting of the High Sink bit
Document #: 001-07552 Rev. *B
Page 37 of 85
[+] Feedback
CYRF69213
Serial Peripheral Interface (SPI)
The SPI Master/Slave Interface core logic runs on the SPI clock domain, making its functionality independent of system clock speed. SPI is a four pin serial interface comprised of a clock, an enable and two data pins. Figure 15. SPI Block Diagram
Register Block SCK Speed Sel SCK Clock Generation
Master/Slave Sel
SCK Clock Select
SCK_OE
SCK Polarity SCK Phase
SCK Clock Phase/Polarity Select SCK
SCK
Little Endian Sel
LE_SEL GPIO Block SS_N SS_N
SPI State Machine SS_N Data (8 bit) Load Empty Master/Slave Set SCK LE_SEL Shift Buffer MISO/MOSI Crossbar Output Shift Buffer
SS_N_OE
MISO_OE
MISO
MOSI_OE
MOSI Data (8 bit) Load Full Input Shift Buffer
Sclk Output Enable Slave Select Output Enable Master IN, Slave Out OE Master Out, Slave In, OE
SCK_OE SS_N_OE MISO_OE MOSI_OE
Document #: 001-07552 Rev. *B
Page 38 of 85
[+] Feedback
CYRF69213
SPI Data Register Table 55.SPI Data Register (SPIDATA) [0x3C] [R/W]
Bit # Field Read/Write Default Bits 7:0 R/W 0 SPI Data [7:0] R/W 0 R/W 0 0 7 6 5 4 SPIData[7:0] R/W R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register
When an interrupt occurs to indicate to firmware that a byte of receive data is available, or the transmitter holding register is empty, firmware has 7 SPI clocks to manage the buffers--to empty the receiver buffer, or to refill the transmit holding register. Failure to meet this timing requirement will result in incorrect data transfer. SPI Configure Register Table 56.SPI Configure Register (SPICR) [0x3D] [R/W]
Bit # Field Read/Write Default Bit 7 7 Swap R/W 0 6 LSB First R/W 0 0 5 Comm Mode R/W R/W 0 4 3 CPOL R/W 0 2 CPHA R/W 0 0 1 SCLK Select R/W R/W 0 0
Swap 0 = Swap function disabled 1 = The SPI block swaps its use of SMOSI and SMISO. Among other things, this can be useful in implementing single wire SPI-like communications LSB First 0 = The SPI transmits and receives the MSB (Most Significant Bit) first 1 = The SPI transmits and receives the LSB (Least Significant Bit) first. Comm Mode [1:0] 0 0: All SPI communication disabled 0 1: SPI master mode 1 0: SPI slave mode 1 1: Reserved CPOL This bit controls the SPI clock (SCLK) idle polarity 0 = SCLK idles low 1 = SCLK idles high CPHA The Clock Phase bit controls the phase of the clock on which data is sampled. Table 57 shows the timing for the various combinations of LSB First, CPOL, and CPHA SCLK Select This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK
Bit 6
Bits 5:4
Bit 3
Bit 2
Bits 1:0
Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave): When configured for SPI, (SPI Use = 1--Table 52), the input/output direction of pins P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input
Document #: 001-07552 Rev. *B
Page 39 of 85
[+] Feedback
CYRF69213
Table 57.SPI Mode Timing vs. LSB First, CPOL and CPHA LSB First CPHA CPOL 0 0 0
SCLK SSEL D AT A
X
MSB B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 LSB
Diagram
X
0
0
1
SC LK SSEL DAT A
X
MSB B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 LSB
X
0
1
0
SC LK SSEL DAT A
X
MSB B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 LS B
X
0
1
1
SC L K SSEL D AT A
X
MS B B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 LS B
X
1
0
0
SCLK SSEL DAT A
X
LSB B it 2 B it 3 B it 4 B it 5 B it 6 B it 7 MS B
X
1
0
1
SCLK SSEL DAT A
X
LSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MSB
X
1
1
0
SCLK SSEL DAT A
X
LSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MSB
X
1
1
1
SC LK SSEL DAT A
X
LSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MSB
X
Document #: 001-07552 Rev. *B
Page 40 of 85
[+] Feedback
CYRF69213
Table 58.SPI SCLK Frequency SCLK Select 00 01 10 11 CPUCLK Divisor 6 12 48 96 SCLK Frequency when CPUCLK = 12 MHz 2 MHz 1 MHz 250 KHz 125 KHz 24 MHz 4 MHz 2 MHz 500 KHz 250 KHz
Registers Free-Running Counter The 16-bit free-running counter is clocked by a 4/6-MHz source. It can be read in software for use as a general-purpose time base. When the low order byte is read, the high order byte is registered. Reading the high order byte reads this register allowing the CPU to read the 16-bit value atomically (loads all bits at one time). The free-running timer generates an interrupt at a 1024-s rate. It can also generate an interrupt when the free-running counter overflow occurs--every 16.384 ms. This allows extending the length of the timer in software.
Timer Registers
All timer functions of the CYRF69213 are provided by a single timer block. The timer block is asynchronous from the CPU clock.
Figure 16. 16-Bit Free-Running Counter Block Diagram
O verflow Interrupt
Tim er C apture C lock
16-bit F ree R unning C ounter
1024-s T im er Interrupt
Table 59.Free-Running Timer Low-Order Byte (FRTMRL) [0x20] [R/W]
Bit # Field Read/Write Default Bits 7:0 R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Free-running Timer [7:0]
Free-running Timer [7:0]
This register holds the low-order byte of the 16-bit free-running timer. Reading this register causes the high-order byte to be moved into a holding register allowing an automatic read of all 16 bits simultaneously. For reads, the actual read occurs in the cycle when the low order is read. For writes, the actual time the write occurs is the cycle when the high order is written When reading the free-running timer, the low-order byte should be read first and the high-order second. When writing, the low-order byte should be written first then the high-order byte
Table 60.Free-Running Timer High-Order Byte (FRTMRH) [0x21] [R/W]
Bit # Field Read/Write Default Bits 7:0 R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Free-running Timer [15:8]
Free-running Timer [15:8]
When reading the free-running timer, the low-order byte should be read first and the high-order second. When writing, the low-order byte should be written first then the high-order byte
Document #: 001-07552 Rev. *B
Page 41 of 85
[+] Feedback
CYRF69213
Table 61.Programmable Interval Timer Low (PITMRL) [0x26] [R]
Bit # Field Read/Write Default Bits 7:0 R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
Prog Interval Timer [7:0]
`Prog Interval Timer [7:0]
This register holds the low-order byte of the 12-bit programmable interval timer. Reading this register causes the high-order byte to be moved into a holding register allowing an automatic read of all 12 bits simultaneously
Table 62.Programmable Interval Timer High (PITMRH) [0x27] [R]
Bit # Field Read/Write Default Bits 7:4 Bits 3:0 - 0 Reserved Prog Internal Timer [11:8] - 0 7 6 Reserved - 0 - 0 R 0 5 4 3 2 R 0 1 R 0 0 R 0
Prog Interval Timer [11:8]
This register holds the high-order nibble of the 12-bit programmable interval timer. Reading this register returns the high-order nibble of the 12-bit timer at the instant that the low-order byte was last read
Table 63.Programmable Interval Reload Low (PIRL) [0x28] [R/W]
Bit # Field Read/Write Default Bits 7:0 R/W 0 Prog Interval [7:0] R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Prog Interval [7:0]
This register holds the lower 8 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble
Table 64.Programmable Interval Reload High (PIRH) [0x29] [R/W]
Bit # Field Read/Write Default Bits 7:4 Bits 3:0 - 0 Reserved Prog Interval [11:8] - 0 7 6 Reserved - 0 - 0 R/W 0 5 4 3 2 R/W 0 1 R/W 0 0 R/W 0
Prog Interval[11:8]
This register holds the higher 4 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble
Document #: 001-07552 Rev. *B
Page 42 of 85
[+] Feedback
CYRF69213
Figure 17. 16-Bit Free-Running Counter Loading Timing Diagram
clk_sys write
valid addr write data FRT reload ready Clk Timer 12b Prog Timer 12b reload interrupt 12-bit programmable timer load timing Capture timer clk 16b free running counter load 16b free running counter
00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0
16-bit free running counter loading timing
Figure 18. Memory Mapped Registers Read/Write Timing Diagram
clk_sys rd_wrn
Valid Addr rdata wdata Memory mapped registers Read/Write timing diagram
Document #: 001-07552 Rev. *B
Page 43 of 85
[+] Feedback
CYRF69213
Interrupt Controller
The interrupt controller and its associated registers allow the user's code to respond to an interrupt from almost every functional block in the CYRF69213 devices. The registers associated with the interrupt controller allow interrupts to be disabled either globally or individually. The registers also provide a mechanism by which a user may clear all pending and posted interrupts, or clear individual posted or pending interrupts. The following table lists all interrupts and the priorities that are available in the CYRF69213. Table 65.Interrupt Numbers, Priorities, Vectors Interrupt Priority 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Interrupt Address 0000h 0004h 0008h 000Ch 0010h 0014h 0018h 001Ch 0020h 0024h 0028h 002Ch 0030h 0034h 0038h 003Ch 0040h Reset POR/LVD INT0 SPI Transmitter Empty SPI Receiver Full GPIO Port 0 GPIO Port 1 INT1 EP0 EP1 EP2 USB Reset USB Active 1-ms Interval timer Programmable Interval Timer Reserved Reserved Name
Table 65.Interrupt Numbers, Priorities, Vectors (continued) Interrupt Priority 17 18 19 20 21 22 23 24 25 Interrupt Address 0044h 0048h 004Ch 0050h 0054h 0058h 005Ch 0060h 0064h INT2 Reserved GPIO Port 2 Reserved Reserved Reserved Reserved Sleep Timer Name 16-bit Free Running Timer Wrap
Architectural Description An interrupt is posted when its interrupt conditions occur. This results in the flip-flop in Figure 19 clocking in a `1'. The interrupt will remain posted until the interrupt is taken or until it is cleared by writing to the appropriate INT_CLRx register. A posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate INT_MSKx register). All pending interrupts are processed by the Priority Encoder to determine the highest priority interrupt which will be taken by the M8C if the Global Interrupt Enable bit is set in the CPU_F register. Disabling an interrupt by clearing its interrupt mask bit (in the INT_MSKx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. It simply prevents a posted interrupt from becoming pending. Nested interrupts can be accomplished by re-enabling interrupts inside an interrupt service routine. To do this, set the IE bit in the Flag Register. A block diagram of the CYRF69213 Interrupt Controller is shown in Figure 19.
Figure 19. Interrupt Controller Block Diagram
Interrupt Taken or INT_CLRx Write Posted Interrupt Pending Interrupt
Priority Encoder
Interrupt Vector
Interrupt Request M8C Core
R 1 Interrupt Source (Timer, GPIO, etc.) INT_MSKx Mask Bit Setting D Q
... ...
CPU_F[0] GIE
Document #: 001-07552 Rev. *B
Page 44 of 85
[+] Feedback
CYRF69213
Interrupt Processing The sequence of events that occur during interrupt processing is as follows: 1. An interrupt becomes active, either because: a. The interrupt condition occurs (for example, a timer expires). b. A previously posted interrupt is enabled through an update of an interrupt mask register. c. An interrupt is pending and GIE is set from 0 to 1 in the CPU Flag register. 2. The current executing instruction finishes. 3. The internal interrupt is dispatched, taking 13 cycles. During this time, the following actions occur: a. The MSB and LSB of Program Counter and Flag registers (CPU_PC and CPU_F) are stored onto the program stack by an automatic CALL instruction (13 cycles) generated during the interrupt acknowledge process. b. The PCH, PCL, and Flag register (CPU_F) are stored onto the program stack (in that order) by an automatic CALL instruction (13 cycles) generated during the interrupt acknowledge process. c. The CPU_F register is then cleared. Since this clears the GIE bit to 0, additional interrupts are temporarily disabled d. The PCH (PC[15:8]) is cleared to zero. e. The interrupt vector is read from the interrupt controller and its value placed into PCL (PC[7:0]). This sets the program counter to point to the appropriate address in the interrupt table (for example, 0004h for the POR/LVD interrupt). 4. Program execution vectors to the interrupt table. Typically, a LJMP instruction in the interrupt table sends execution to the user's Interrupt Service Routine (ISR) for this interrupt. 5. The ISR executes. Note that interrupts are disabled since GIE = 0. In the ISR, interrupts can be re-enabled if desired Table 66. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]
Bit # Field Read/Write Default 7 GPIO Port 1 R/W 0 6 Sleep Timer R/W 0 5 INT1 R/W 0 4
by setting GIE = 1 (care must be taken to avoid stack overflow). 6. The ISR ends with a RETI instruction which restores the Program Counter and Flag registers (CPU_PC and CPU_F). The restored Flag register re-enables interrupts, since GIE = 1 again. 7. Execution resumes at the next instruction, after the one that occurred before the interrupt. However, if there are more pending interrupts, the subsequent interrupts will be processed before the next normal program instruction. Interrupt Latency The time between the assertion of an enabled interrupt and the start of its ISR can be calculated from the following equation. Latency = Time for current instruction to finish + Time for internal interrupt routine to execute + Time for LJMP instruction in interrupt table to execute. For example, if the 5-cycle JMP instruction is executing when an interrupt becomes active, the total number of CPU clock cycles before the ISR begins would be as follows: (1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine) + (7 cycles for LJMP) = 21 to 25 cycles. In the example above, at 24 MHz, 25 clock cycles take 1.042 s. Interrupt Registers The Interrupt Registers are discussed it the following sections. Interrupt Clear Register The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources' ability to clear posted interrupts. When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore, reading these registers gives the user the ability to determine all posted interrupts.
3 SPI Receive R/W 0
2 SPI Transmit R/W 0
1 INT0 R/W 0
0 POR/LVD R/W 0
GPIO Port 0 R/W 0
When reading this register, 0 = There's no posted interrupt for the corresponding hardware 1 = Posted interrupt for the corresponding hardware present Writing a `0' to the bits will clear the posted interrupts for the corresponding hardware. Writing a `1' to the bits AND to the ENSWINT (Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt
Document #: 001-07552 Rev. *B
Page 45 of 85
[+] Feedback
CYRF69213
Table 67. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
Bit # Field Read/Write Default R/W 0 7 Reserved 6 Prog Interval Timer R/W 0 5 1-ms Timer R/W 0 4 USB Active R/W 0 3 USB Reset R/W 0 2 USB EP2 R/W 0 1 USB EP1 R/W 0 0 USB EP0 R/W 0
When reading this register, 0 = There's no posted interrupt for the corresponding hardware 1 = Posted interrupt for the corresponding hardware present Writing a `0' to the bits will clear the posted interrupts for the corresponding hardware. Writing a `1' to the bits AND to the ENSWINT (Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt Bit 7 Reserved
Table 68.Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 Reserved 6 Reserved 5 Reserved 4 GPIO Port 2 3 Reserved 2 INT2 1 16-bit Counter Wrap R/W 0 0 Reserved R/W 0
When reading this register, 0 = There's no posted interrupt for the corresponding hardware 1 = Posted interrupt for the corresponding hardware present Writing a `0' to the bits will clear the posted interrupts for the corresponding hardware. Writing a `1' to the bits AND to the ENSWINT (Bit 7 of the INT_MSK3 Register) will post the corresponding hardware interrupt Bits 7,6,5,3,0 Reserved
Interrupt Mask Registers The Interrupt Mask Registers (INT_MSKx) are used to enable the individual interrupt sources' ability to create pending interrupts. There are four Interrupt Mask Registers (INT_MSK0, INT_MSK1, INT_MSK2, and INT_MSK3), which may be referred to in general as INT_MSKx. If cleared, each bit in an INT_MSKx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). However, an interrupt can still post even if its mask bit is zero. All INT_MSKx bits are independent of all other INT_MSKx bits. If an INT_MSKx bit is set, the interrupt source associated with that mask bit may generate an interrupt that will become a pending interrupt. Table 69.Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]
Bit # Field Read/Write Default Bit 7 7 ENSWINT R/W 0 - 0 - 0 - 0 6 5 4
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7] determines the way an individual bit value written to an INT_CLRx register is interpreted. When is cleared, writing 1's to an INT_CLRx register has no effect. However, writing 0's to an INT_CLRx register, when ENSWINT is cleared, will cause the corresponding interrupt to clear. If the ENSWINT bit is set, any 0's written to the INT_CLRx registers are ignored. However, 1's written to an INT_CLRx register, while ENSWINT is set, will cause an interrupt to post for the corresponding interrupt. Software interrupts can aid in debugging interrupt service routines by eliminating the need to create system level interactions that are sometimes necessary to create a hardware-only interrupt.
3 Reserved - 0
2 - 0
1 - 0
0 - 0
Enable Software Interrupt (ENSWINT) 0 = Disable. Writing 0's to an INT_CLRx register, when ENSWINT is cleared, will cause the corresponding interrupt to clear 1 = Enable. Writing 1's to an INT_CLRx register, when ENSWINT is set, will cause the corresponding interrupt to post Reserved
Bits 6:0
Document #: 001-07552 Rev. *B
Page 46 of 85
[+] Feedback
CYRF69213
Table 70.Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]
Bit # 7 Reserved Field Read/Write Default Bit 7 Bit 6 Bit 5 Bit 4 - 0 Reserved Reserved Reserved GPIO Port 2 Interrupt Enable 0 = Mask GPIO Port 2 interrupt 1 = Unmask GPIO Port 2 interrupt Reserved INT2 Interrupt Enable 0 = Mask INT2 interrupt 1 = Unmask INT2 interrupt 16-bit Counter Wrap Interrupt Enable 0 = Mask 16-bit Counter Wrap interrupt 1 = Unmask 16-bit Counter Wrap interrupt Reserved R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 Reserved 5 Reserved 4 GPIO Port 2 Int Enable 3 Reserved 2 INT2 Int Enable 1 16-bit Counter Wrap Int Enable R/W 0 0 Reserved
R/W 0
Bit 3 Bit 2
Bit 1
Bit 0
Table 71.Interrupt Mask 1 (INT_MSK1) [0xE1] [R/W]
Bit # 7 Reserved Field Read/Write Default Bit 7 Bit 6 R/W 0 Reserved Prog Interval Timer Interrupt Enable 0 = Mask Prog Interval Timer interrupt 1 = Unmask Prog Interval Timer interrupt 1-ms Timer Interrupt Enable 0 = Mask 1-ms interrupt 1 = Unmask 1-ms interrupt USB Active Interrupt Enable 0 = Mask USB Active interrupt 1 = Unmask USB Active interrupt USB Reset Interrupt Enable 0 = Mask USB Reset interrupt 1 = Unmask USB Reset interrupt USB EP2 Interrupt Enable 0 = Mask EP2 interrupt 1 = Unmask EP2 interrupt USB EP1 Interrupt Enable 0 = Mask EP1 interrupt 1 = Unmask EP1 interrupt USB EP0 Interrupt Enable 0 = Mask EP0 interrupt 1 = Unmask EP0 interrupt 6 Prog Interval Timer Int Enable R/W 0 5 1-ms Timer Int Enable R/W 0 4 USB Active Int Enable R/W 0 3 USB Reset Int Enable R/W 0 2 USB EP2 Int Enable R/W 0 1 USB EP1 Int Enable R/W 0 0 USB EP0 Int Enable R/W 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Document #: 001-07552 Rev. *B
Page 47 of 85
[+] Feedback
CYRF69213
Table 72. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W]
Bit # Field Read/Write Default Bit 7 7 GPIO Port 1 Int Enable R/W 0 6 Sleep Timer Int Enable R/W 0 5 INT1 Int Enable R/W 0 4 GPIO Port 0 Int Enable R/W 0 3 SPI Receive Int Enable R/W 0 2 SPI Transmit Int Enable R/W 0 1 INT0 Int Enable R/W 0 0 POR/LVD Int Enable R/W 0
GPIO Port 1 Interrupt Enable 0 = Mask GPIO Port 1 interrupt 1 = Unmask GPIO Port 1 interrupt Sleep Timer Interrupt Enable 0 = Mask Sleep Timer interrupt 1 = Unmask Sleep Timer interrupt INT1 Interrupt Enable 0 = Mask INT1 interrupt 1 = Unmask INT1 interrupt GPIO Port 0 Interrupt Enable 0 = Mask GPIO Port 0 interrupt 1 = Unmask GPIO Port 0 interrupt SPI Receive Interrupt Enable 0 = Mask SPI Receive interrupt 1 = Unmask SPI Receive interrupt SPI Transmit Interrupt Enable 0 = Mask SPI Transmit interrupt 1 = Unmask SPI Transmit interrupt INT0 Interrupt Enable 0 = Mask INT0 interrupt 1 = Unmask INT0 interrupt POR/LVD Interrupt Enable 0 = Mask POR/LVD interrupt 1 = Unmask POR/LVD interrupt
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Interrupt Vector Clear Register Table 73.Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Pending Interrupt [7:0]
The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and when written will clear all pending interrupts Bits 7:0 Pending Interrupt [7:0] 8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register will clear all pending interrupts
Document #: 001-07552 Rev. *B
Page 48 of 85
[+] Feedback
CYRF69213
USB Transceiver
USB Transceiver Configuration Table 74.USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
Bit # Field Read/Write Default Bit 7 7 USB Pull-up Enable R/W 0 - 0 - 0 - 0 6 5 4 Reserved - 0 - 0 - 0 3 2 1 0 USB Force State R/W 0
USB Pull-up Enable 0 = Disable the pull-up resistor on D- 1 = Enable the pull-up resistor on D-. This pull-up is to VCC IF VREG is not enabled or to the internally generated 3.3V when VREG is enabled Reserved USB Force State This bit allows the state of the USB I/O pins DP and D+ to be forced to a state while USB is enabled 0 = Disable USB Force State 1 = Enable USB Force State. Allows the D- and D+ pins to be controlled by P1.1 and P1.0 respectively when the USBIO is in USB mode. Refer to Table 44 for more information
Bits 6:1 Bit 0
Note The USB transceiver has a dedicated 3.3V regulator for USB signalling purposes and to provide for the 1.5K D- pull up. Unlike the other 3.3V regulator, this regulator cannot be controlled/accessed by firmware. When the device is suspended, this regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the D- line is pulled up to 5V through an alternate 6.5K resistor. During wakeup following a suspend, the band gap and the regulator are switched on in any order. Under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator and the band gap turn on in that particular order, there is possibility of a glitch/low pulse occurring on the D- line. The host can misinterpret this as a deattach condition. This condition, although rare, can be avoided by keeping the bandgap circuitry enabled during sleep. This is achieved by setting the `No Buzz' bit, bit[5] in the OSC_CR0 register. This is an issue only if the device is put to sleep during a bus reset condition
VREG Control Table 75.VREG Control Register (VREGCR) [0x73] [R/W]
Bit # Field Read/Write Default Bits 7:2 Bit 1 - 0 Reserved Keep Alive Keep Alive when set allows the voltage regulator to source up to 20 A of current when voltage regulator is disabled, P12CR[0],P12CR[7] should be cleared. 0 = Disabled 1 = Enabled VREG Enable This bit turns on the 3.3V voltage regulator. The voltage regulator only functions within specifications when VCC is above 4.35V. This block should not be enabled when VCC is below 4.35V--although no damage or irregularities will occur if it is enabled below 4.35V 0 = Disable the 3.3V voltage regulator output on the VREG/P1.2 pin 1 = Enable the 3.3V voltage regulator output on the VREG/P1.2 pin. GPIO functionality of P1.2 is disabled - 0 - 0 7 6 5 Reserved - 0 - 0 - 0 4 3 2 1 Keep Alive R/W 0 0 VREG Enable R/W 0
Bit 0
Note Use of the alternate drive on pins P1.3-P1.6 requires that the VREG Enable bit be set to enable the regulator and provide the alternate voltage
Document #: 001-07552 Rev. *B
Page 49 of 85
[+] Feedback
CYRF69213
USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the USB host at low-speed data rates (1.5 Mbps). The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller: * Translating the encoded received data and formatting the data to be transmitted on the bus * CRC checking and generation. Flagging the microcontroller if errors exist during transmission * Address checking. Ignoring the transactions not addressed to the device * Sending appropriate ACK/NAK/STALL handshakes
* Identifying token type (SETUP, IN, or OUT). Setting the appropriate token bit once a valid token is received * Placing valid received data in the appropriate endpoint FIFOs * Sending and updating the data toggle bit (Data1/0) * Bit stuffing/unstuffing. Firmware is required to handle the rest of the USB interface with the following tasks: * Coordinate enumeration by decoding USB device requests * Fill and empty the FIFOs * Suspend/Resume coordination * Verify and select Data toggle values
USB Device
Table 76.USB Device Address (USBCR) [0x40] [R/W]
Bit # Field Read/Write Default Bit 7 7 USB Enable R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 Device Address[6:0] R/W 0 R/W 0 R/W 0 R/W 0 2 1 0
The content of this register is cleared when a USB Bus Reset condition occurs USB Enable This bit must be enabled by firmware before the serial interface engine (SIE) will respond to USB traffic at the address specified in Device Address [6:0]. When this bit is cleared, the USB transceiver enters power-down state. User's firmware should clear this bit prior to entering sleep mode to save power 0 = Disable USB device address and put the USB transceiver into power-down state 1 = Enable USB device address and put the USB transceiver into normal operating mode Device Address [6:0] These bits must be set by firmware during the USB enumeration process (for example, SetAddress) to the non-zero address assigned by the USB host
Bits 6:0
Table 77.Endpoint 0, 1, and 2 Count (EP0CNT-EP2CNT) [0x41, 0x43, 0x45] [R/W]
Bit # Field Read/Write Default Bit 7 7 Data Toggle R/W 0 6 Data Valid R/W 0 R/W 0 5 Reserved R/W 0 R/W 0 4 3 2 R/W 0 1 R/W 0 0 R/W 0
Byte Count[3:0]
Data Toggle This bit selects the DATA packet's toggle state. For IN transactions, firmware must set this bit to the select the transmitted Data Toggle. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit. 0 = DATA0 1 = DATA1 Data Valid This bit is used for OUT and SETUP tokens only. This bit is cleared to `0' if CRC, bitstuff, or PID errors have occurred. This bit does not update for some endpoint mode settings 0 = Data is invalid. If enabled, the endpoint interrupt will occur even if invalid data is received 1 = Data is valid Reserved Byte Count Bit [3:0] Byte Count Bits indicate the number of data bytes in a transaction: For IN transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8 inclusive. For OUT or SETUP transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values are 2-10 inclusive.
Bit 6
Bits 5:4 Bits 3:0
For Endpoint 0 Count Register, whenever the count updates from a SETUP or OUT transaction, the count register locks and cannot be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on it
Document #: 001-07552 Rev. *B
Page 50 of 85
[+] Feedback
CYRF69213
Endpoint 0 Mode Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers the SIE provides an interlocking mechanism to prevent accidental overwriting of data. Table 78.Endpoint 0 Mode (EP0MODE) [0x44] [R/W]
Bit # Field Read/Write Default Bit 7 7 Setup Received R/C[3] 0 6 IN Received R/C[3] 0 5 4
When the SIE writes to these registers they are locked and the processor cannot write to them until after it has read them. Writing to this register clears the upper four bits regardless of the value written.
3
2 Mode[3:0]
1
0
OUT Received ACK'd Trans R/C[3] 0 R/C[3] 0 R/W 0 R/W 0
R/W 0
R/W 0
SETUP Received This bit is set by hardware when a valid SETUP packet is received. It is forced HIGH from the start of the data packet phase of the SETUP transactions until the end of the data phase of a control write transfer and cannot be cleared during this interval. While this bit is set to `1', the CPU cannot write to the EP0 FIFO. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data This bit is cleared by any non-locked writes to the register 0 = No SETUP received 1 = SETUP received IN Received This bit, when set, indicates a valid IN packet has been received. This bit is updated to `1' after the host acknowledges an IN data packet.When clear, it indicates that either no IN has been received or that the host didn't acknowledge the IN data by sending an ACK handshake This bit is cleared by any non-locked writes to the register. 0 = No IN received 1 = IN received OUT Received This bit, when set, indicates a valid OUT packet has been received and ACKed. This bit is updated to `1' after the last received packet in an OUT transaction. When clear, it indicates no OUT received This bit is cleared by any non-locked writes to the register 0 = No OUT received 1 = OUT received ACK'd Transaction The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with a ACK packet This bit is cleared by any non-locked writes to the register 1 = The transaction completes with an ACK 0 = The transaction does not complete with an ACK Mode [3:0] The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode controls how the USB SIE responds to traffic and how the USB SIE will change the mode of that endpoint as a result of host packets to the endpoint
Bit 6
Bit 5
Bit 4
Bits 3:0
Document #: 001-07552 Rev. *B
Page 51 of 85
[+] Feedback
CYRF69213
Table 79.Endpoint 1 and 2 Mode (EP1MODE - EP2MODE) [0x45, 0x46] [R/W]
Bit # Field Read/Write Default Bit 7 R/W 0 R/W 0 7 Stall 6 Reserved 5 NAK Int Enable R/W 0 4 ACK'd Transaction R/C (Note 3) 0 R/W 0 R/W 0 3 2 Mode[3:0] R/W 0 R/W 0 1 0
Stall When this bit is set the SIE will stall an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE will stall an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes Reserved NAK Int Enable This bit, when set, causes an endpoint interrupt to be generated even when a transfer completes with a NAK. Unlike enCoRe, CYRF69213 family members do not generate an endpoint interrupt under these conditions unless this bit is set 0 = Disable interrupt on NAK'd transactions 1 = Enable interrupt on NAK'd transaction ACK'd Transaction The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet This bit is cleared by any writes to the register 0 = The transaction does not complete with an ACK 1 = The transaction completes with an ACK Mode [3:0] The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode controls how the USB SIE responds to traffic and how the USB SIE will change the mode of that endpoint as a result of host packets to the endpoint.
Bit 6 Bit 5
Bit 4
Bits 3:0
Note When the SIE writes to the EP1MODE or the EP2MODE register it blocks firmware writes to the EP2MODE or the EP1MODE registers, respectively (if both writes occur in the same clock cycle). This is because the design employs only one common `update' signal for both EP1MODE and EP2MODE registers. Thus, when SIE writes to the EP1MODE register, the update signal is set and this prevents firmware writes to EP2MODE register. SIE writes to the endpoint mode registers have higher priority than firmware writes. This mode register write block situation can put the endpoints in incorrect modes. Firmware must read the EP1/2MODE registers immediately following a firmware write and rewrite if the value read is incorrect
Endpoint Data Buffers The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long. The reset values of the Endpoint Data Registers are unknown. Unlike past enCoRe parts the USB data buffers are only accessible in the I/O space of the processor. Table 80.Endpoint 0 Data (EP0DATA) [0x50-0x57] [R/W]
Bit # Field Read/Write Default R/W Unknown R/W Unknown R/W Unknown 7 6 5 4 R/W Unknown 3 R/W Unknown 2 R/W Unknown 1 R/W Unknown 0 R/W Unknown
Endpoint 0 Data Buffer [7:0]
The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57
Table 81.Endpoint 1 Data (EP1DATA) [0x58-0x5F] [R/W]
Bit # Field Read/Write Default R/W Unknown R/W Unknown R/W Unknown 7 6 5 4 R/W Unknown 3 R/W Unknown 2 R/W Unknown 1 R/W Unknown 0 R/W Unknown
Endpoint 1 Data Buffer [7:0]
The Endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5F
Document #: 001-07552 Rev. *B
Page 52 of 85
[+] Feedback
CYRF69213
Table 82.Endpoint 2 Data (EP2DATA) [0x60-0x67] [R/W]
Bit # Field Read/Write Default R/W Unknown R/W Unknown R/W Unknown 7 6 5 4 R/W Unknown 3 R/W Unknown 2 R/W Unknown 1 R/W Unknown 0 R/W Unknown
Endpoint 2 Data Buffer [7:0]
The Endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67
USB Mode Tables
Mode DISABLE NAK IN/OUT STATUS OUT ONLY STALL IN/OUT STATUS IN ONLY ACK OUT - STATUS IN ACK IN - STATUS OUT NAK OUT ACK OUT (STALL = 0) ACK OUT (STALL = 1) NAK IN ACK IN (STALL = 0) ACK IN (STALL = 1) Reserved Reserved Reserved Reserved Reserved Encoding 0000 0001 0010 0011 0110 1011 1111 SETUP Ignore Accept Accept Accept Accept Accept Accept IN Ignore NAK STALL STALL TX0 byte TX0 byte TX Count OUT Ignore NAK Check STALL STALL ACK Check Comments Ignore all USB traffic to this endpoint. Used by Data and Control endpoints NAK IN and OUT token. Control endpoint only STALL IN and ACK zero byte OUT. Control endpoint only STALL IN and OUT token. Control endpoint only STALL OUT and send zero byte data for IN token. Control endpoint only ACK the OUT token or send zero byte data for IN token. Control endpoint only Respond to IN data or Status OUT. Control endpoint only
1000 1001 1001 1100 1101 1101 0101 0111 1010 0100 1110
Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore
Ignore Ignore Ignore NAK TX Count STALL Ignore Ignore Ignore Ignore Ignore
NAK ACK STALL Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore
Send NAK handshake to OUT token. Data endpoint only This mode is changed by the SIE to mode 1000 on issuance of ACK handshake to an OUT. Data endpoint only STALL the OUT transfer Send NAK handshake for IN token. Data endpoint only This mode is changed by the SIE to mode 1100 after receiving ACK handshake to an IN data. Data endpoint only STALL the IN transfer. Data endpoint only These modes are not supported by SIE. Firmware should not use this mode in Control and Data endpoints
Mode Column The 'Mode' column contains the mnemonic names given to the modes of the endpoint. The mode of the endpoint is determined by the four-bit binaries in the 'Encoding' column as discussed in the following section. The Status IN and Status OUT represent the status IN or OUT stage of the control transfer. Encoding Column The contents of the 'Encoding' column represent the Mode Bits [3:0] of the Endpoint Mode Registers (Table 78 and Table 79). The endpoint modes determine how the SIE responds to different tokens that the host sends to the endpoints. For example, if the Mode Bits [3:0] of the Endpoint 0 Mode Register are set to '0001', which is NAK IN/OUT mode, the SIE will send an ACK handshake in response to SETUP tokens and NAK any IN or OUT tokens. Document #: 001-07552 Rev. *B
SETUP, IN, and OUT Columns Depending on the mode specified in the 'Encoding' column, the 'SETUP', 'IN', and 'OUT' columns contain the SIE's responses when the endpoint receives SETUP, IN, and OUT tokens, respectively. A 'Check' in the Out column means that upon receiving an OUT token the SIE checks to see whether the OUT is of zero length and has a Data Toggle (Data1/0) of 1. If these conditions are true, the SIE responds with an ACK. If any of the above conditions is not met, the SIE will respond with either a STALL or Ignore. A 'TX Count' entry in the IN column means that the SIE will transmit the number of bytes specified in the Byte Count Bit [3:0] of the Endpoint Count Register (Table 77) in response to any IN token.
Page 53 of 85
[+] Feedback
CYRF69213
Details of Mode for Differing Traffic Conditions
Control Endpoint
SIE Mode 0000 0011 0011 0011 0011 0011 0011 0011 0001 0001 0001 0001 0001 0001 0001 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0010 0010 0010 0010 0010 0010 0010 0010 0010 1011 1011 1011 1011 Token x SETUP SETUP SETUP IN OUT OUT OUT SETUP SETUP SETUP IN OUT OUT OUT SETUP SETUP SETUP IN IN OUT OUT OUT OUT OUT SETUP SETUP SETUP IN OUT OUT OUT OUT OUT SETUP SETUP SETUP IN Bus Event Count x >10 <=10 <=10 x >10 <=10 <=10 >10 <=10 <=10 x >10 <=10 <=10 >10 <=10 <=10 x x >10 <=10 <=10, <>2 2 2 >10 <=10 <=10 x >10 <=10 <=10, <>2 2 2 >10 <=10 <=10 x Dval x x invalid valid x x invalid valid x invalid valid x x invalid valid x invalid valid x x x invalid valid valid valid x invalid valid x x invalid valid valid valid x invalid valid x D0/1 x x x x x x x x x x x x x x x x x x x x x x x 0 1 x x x x x x x 0 1 x x x x ACK TX 0 1 1 0001 update 1 update STALL STALL ACK 11 0011 0011 1 1 2 junk junk data Yes Yes Yes Yes ACK STALL 1 1 0001 0011 update 1 update STALL STALL ACK 11 0011 0011 0010 1 1 2 junk junk data Yes Yes Yes Yes Yes ACK TX TX 1 1 0001 Yes 1 1 0001 update 1 update NAK junk junk data Yes ACK NAK 1 1 0001 update 1 update STALL junk junk data Yes ACK STALL 1 1 0001 update 1 update junk junk data Yes SIE EP0 Mode Register I EP0 Count Register EP0 Interrupt Comments Response S O A MODE DTOG DVAL COUNT FIFO Ignore All Ignore Ignore ACK SETUP Stall IN Ignore Ignore Stall OUT Ignore Ignore ACK SETUP NAK IN Ignore Ignore NAK OUT Ignore Ignore ACK SETUP Host Not ACK'd Host ACK'd Ignore Ignore Bad Status Bad Status Good Status Ignore Ignore ACK SETUP Stall IN Ignore Ignore Bad Status Bad Status Good Status Ignore Ignore ACK SETUP Host Not ACK'd
DISABLED
STALL_IN_OUT
NAK_IN_OUT
ACK_IN_STATUS_OUT
STATUS_OUT
ACK_OUT_STATUS_IN
Document #: 001-07552 Rev. *B
Page 54 of 85
[+] Feedback
CYRF69213
Details of Mode for Differing Traffic Conditions (continued)
1011 1011 1011 1011 0110 0110 0110 0110 0110 0110 0110 0110 SIE Mode 1001 1001 1001 1001 1001 1001 1001 1001 1000 1000 1000 1000 SIE Mode 1101 1101 1101 1101 1101 NAK IN 1100 1100 OUT IN x x x x x x NAK Ignore If Enabled NAK IN Token OUT IN IN OUT IN Token IN OUT OUT OUT IN OUT OUT OUT IN OUT OUT OUT IN OUT OUT OUT SETUP SETUP SETUP IN IN OUT OUT OUT x >10 <=10 <=10 >10 <=10 <=10 x x >10 <=10 <=10 x x invalid valid x invalid valid x x x invalid valid x x x x x x x x x x x x STALL SIE D0/1 x x valid x x valid x x valid NAK SIE D0/1 x x x x x STALL TX 1 1100 Yes EP0 Mode Register I EP0 Count Register EP0 STALL ACK 1 1000 update 1 update junk junk data Yes 0011 EP0 Mode Register I EP0 Count Register EP0 Yes Interrupt ACK TX 0 TX 0 1 1 0011 Yes 1 1 0001 update 1 update ACK 11 0001 update 1 update TX 0 1 1 0011 junk junk data junk junk data Yes Yes Yes Host ACK'd Ignore Ignore Good OUT Ignore Ignore ACK SETUP Host Not ACK'd Host ACK'd Ignore Ignore Stall OUT Comments
STATUS_IN
Data Out Endpoints
Bus Event Count x >MAX <=MAX <=MAX x >MAX <=MAX <=MAX x >MAX <=MAX <=MAX Dval x x valid x x valid x x valid Response S O A MODE DTOG DVAL COUNT FIFO Ignore Ignore Ignore ACK OUT Ignore Ignore Ignore Stall OUT Ignore Ignore Ignore If Enabled NAK OUT Interrupt Comments
ACK OUT (STALL Bit = 0)
invalid invalid
ACK OUT (STALL Bit = 1)
invalid invalid
NAK OUT
invalid invalid
Data In Endpoints
Bus Event Count x x x x x Dval x x x x x Response S O A MODE DTOG DVAL COUNT FIFO Ignore Host Not ACK'd Host ACK'd Ignore Stall IN
ACK IN (STALL Bit = 0)
ACK IN (STALL Bit = 1)
Document #: 001-07552 Rev. *B
Page 55 of 85
[+] Feedback
CYRF69213
Register Summary
Addr
00 01 02 07-09 0C 0D 0E 0F 10 11-13 14 15 20 21 26 27 28 29 30
Name
P0DATA P1DATA P2DATA P02CR- P04CR P07CR P10CR P11CR P12CR P13CR P14CR- P16CR P17CR P2CR FRTMRL FRTMRH PITMRL PITMRH PIRL PIRH CPUCLKCR
7
P0.7 P1.7
6
5
4
P0.4/INT2
3
P0.3/INT1
2
P0.2/INT0
1
Reserved P1.1/D-
0
Reserved P1.0/D+
R/W
b--bbb-bbbbbbbb bbbbbbbb --bbbbbb -bbbbbbb -bb----b -bb--b-b bbbbbbbb -bbbbbbb bbbbbbbb -bbbbbbb -bbbbbbb bbbbbbbb bbbbbbbb bbbbbbbb ----bbbb bbbbbbbb ----bbbb
Default
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010000
Reserved Reserved
P1.6/SMI P1.5/SMO P1.4/SCLK P1.3/SSEL P1.2/VREG SO SI Res Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low Int Act Low TTL Thresh Reserved TTL Thresh Reserved Reserved Reserved TTL Thresh Reserved 3.3V Drive 3.3V Drive High Sink High Sink Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain
P2.1-P2.0 Pull-up Enable Pull-up Enable Reserved Reserved Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable
Reserved Reserved Reserved Reserved Reserved CLK Output Reserved SPI Use Reserved Reserved Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable
TTL Thresh High Sink TTL Thresh Reserved
Free-Running Timer [7:0] Free-Running Timer [15:8] Prog Interval Timer [7:0] Reserved Prog Interval [7:0] Reserved Reserved USB CLK/2 Disable Reserved foffset[2:0] Reserved 32-KHz Low Power Reserved 32-KHz Bias Trim [1:0] Reserved USB CLK Select TCAPCLK Select Prog Interval [11:8] Reserved CPU CLK Select ITMRCLK Select CLKOUT Select Gain[4:0] Reserved 32-KHz Freq Trim [3:0] Mode Prog Interval Timer [11:8]
-bb----b
31 32 34 35 36
ITMRCLKCR CLKIOCR IOSCTR XOSCTR LPOSCTR
TCAPCLK Divider
ITMRCLK Divider Reserved
bbbbbbbb ---bbbbb bbbbbbbb ---bbb-b b-bbbbbb
10001111 00000000 000ddddd 000ddd0d dddddddd
39
OSCLCKCR
Reserved
Fine Tune Only SPIData[7:0]
USB Osclock Disable
------bb
00000000
3C 3D 40 41 42 43 44 45 46 50-57 58-5F 60-67
SPIDATA SPICR USBCR EP0CNT EP1CNT EP2CNT EP0MODE EP1MODE EP2MODE EP0DATA EP1DATA EP2DATA Swap USB Enable Data Toggle Data Toggle Data Toggle Setup rcv'd Stall Stall Data Valid Data Valid Data Valid IN rcv'd Reserved Reserved Reserved Reserved Reserved LSB First Comm Mode
bbbbbbbb CPHA SCLK Select bbbbbbbb bbbbbbbb Byte Count[3:0] Byte Count[3:0] Byte Count[3:0] Mode[3:0] Mode[3:0] Mode[3:0] bbbbbbbb bbbbbbbb bbbbbbbb ccccbbbb b-bcbbbb b-bcbbbb bbbbbbbb bbbbbbbb bbbbbbbb
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ???????? ???????? ????????
CPOL
Device Address[6:0]
OUT rcv'd ACK'd trans NAK Int Enable NAK Int Enable Ack'd trans Ack'd trans Endpoint 0 Data Buffer [7:0] Endpoint 1 Data Buffer [7:0] Endpoint 2 Data Buffer [7:0]
Document #: 001-07552 Rev. *B
Page 56 of 85
[+] Feedback
CYRF69213
Register Summary (continued)
Addr
73 74
Name
VREGCR USBXCR
7
6
5
4
Reserved
3
2
1
Keep Alive
0
VREG Enable USB Force State
R/W
------bb b------b
Default
00000000 00000000
USB Pull-up Enable GPIO Port 1 Reserved Sleep Timer Prog Interval Timer INT1 1-ms Timer
Reserved
DA DB
INT_CLR0 INT_CLR1
GPIO Port 0
SPI Receive
SPI Transmit USB EP2
INT0 USB EP1
POR/LVD USB EP0
bbbbbbbb -bbbbbbb
00000000 00000000
USB Active USB Reset
DC
INT_CLR2
Reserved Reserved Reserved GPIO Port 2 Reserved
INT2
16-bit Counter Wrap 16-bit Counter Wrap Int Enable
Reserved
-bbbbbb-
00000000
DE DF
INT_MSK3 INT_MSK2
ENSWINT
Reserved INT2 Int Enable Reserved
b---------bbbb-
00000000 00000000
Reserved Reserved Reserved GPIO Port 2 Reserved Int Enable
E1
INT_MSK1
Reserved
Prog 1-ms USB Active USB Reset Interval Timer Int Enable Int Enable Timer Int Enable Int Enable
USB EP2 Int Enable
USB EP1 USB EP0 Int Enable Int Enable
bbbbbbbb
00000000
E0
INT_MSK0
GPIO Port Sleep INT1 GPIO Port 0 SPI SPI Transmit INT0 POR/LVD 1 Timer Int Enable Int Enable Receive Int Enable Int Enable Int Enable Int Enable Int Enable Int Enable Pending Interrupt [7:0] Reset Watchdog Timer [7:0] Temporary Register T1 [7:0] X[7:0] Program Counter [7:0] Program Counter [15:8] Stack Pointer [7:0] Reserved GIES Reserved WDRS No Buzz Reserved Reserved Sleep Duty Cycle [1:0] Reserved XOI PORS Super Sleep Reserved Reserved LVD PPOR Carry Reserved Zero Reserved VM[2:0] CPU Speed [2:0] Global IE Stop
bbbbbbbb
00000000
E2 E3 -----FF 1E0 1E3 1EB 1E4
INT_VC RESWDT CPU_A CPU_X CPU_PCL CPU_PCH CPU_SP CPU_F CPU_SCR OSC_CR0 LVDCR ECO_TR VLTCMP
bbbbbbbb wwwwwwww --------------------------------------brwww r-ccb--b --bbbbbb --bb-bbbb bb-----------rr
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010 00010000 00000000 00000000 00000000 00000000
Sleep Timer [1:0]
PORLEV[1:0]
LEGEND In the R/W column, b = Both Read and Write r = Read Only w = Write Only c = Read/Clear ? = Unknown d = calibration value. Should not change during normal use
Document #: 001-07552 Rev. *B
Page 57 of 85
[+] Feedback
CYRF69213
Radio Function Register Descriptions
All registers are read and writeable, except where noted. Registers may be written to or read from either individually or in sequential groups. A single-byte read or write reads or writes from the addressed register. Incrementing burst read and write is a sequence that begins with an address, and then reads or writes to/from each register in address order for as long as clocking continues. It is possible to repeatedly read (poll) a single register using a non-incrementing burst read. These registers are managed and configured over SPI by the user firmware running in the microcontroller function. Table 83.Register Map Summary
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 RX_CFG_ADR 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x27 0x28 0x29 0x32 0x35 0x39 0x20 0x21 0x22 0x23 0x24 0x25 RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR RX_OVERRIDE_ADR TX_OVERRIDE_ADR CLK_OVERRIDE_ADR CLK_EN_ADR RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_ADR ANALOG_CTRL_ADR TX_BUFFER_ADR RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR RSVD RSVD RSVD Not Used RSVD ACK RX ACK TX RSVD RSVD RSVD Not Used RSVD RXTX DLY FRC PRE RSVD RSVD RSVD Not Used FRC SEN MAN RXACK RSVD RSVD RSVD ABORT EN PMU EN LVIRQ EN PMU MODE FORCE XSIRQ EN MISO OD PACTL OP FRC END LEN EN Not Used Not Used LNA HINT CRC SEED LSB CRC SEED MSB CRC LSB CRC MSB CRC LSB CRC MSB STRIM LSB Not Used FRC AWAKE FRC RXDR MAN TXACK RSVD RSVD RSVD DIS CRC0 OVRD ACK RSVD RSVD RSVD STRIM MSB Not Used DIS RXCRC DIS TXCRC RSVD RSVD RSVD Not Used ACE RSVD RXF RXF RSVD RST Not Used 00000000 TX INV RSVD RSVD RSVD 00000000 00000000 00000000 00000011 00000000 RSVD RSVD ALL SLOW 00000000 --------------Note 5 Note 6 Note 7 NA wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr bbbbbbbb Not Used TH64 RSSI EOP AGC EN RXOW IRQ RX ACK LNA SOFDET IRQ PKT ERR ATT RXB16 IRQ EOP ERR HILO RXB8 IRQ CRC0 Mnemonic CHANNEL_ADR TX_LENGTH_ADR TX_CTRL_ADR TX_CFG_ADR TX_IRQ_STATUS_ADR RX_CTRL_ADR TX GO Not Used OS IRQ RX GO TX CLR Not Used LV IRQ RSVD TXB15 IRQEN DATA CODE LENGTH TXB15 IRQ RXB16 IRQEN b7 Not Used TXB8 IRQEN b6 b5 b4 b3 Channel TX Length TXB0 IRQEN TXBERR IRQEN TXC IRQEN PA SETTING TXBERR IRQ RXBERR IRQEN Not Used RXBERR IRQ RX Code TXC IRQ RXC IRQEN RXOW EN RXC IRQ TXE IRQ RXE IRQEN VLD EN RXE IRQ 00000000 00001--00000000 00000000 LVI TH Not Used PACTL OD PACTL GPIO XOUT IP END STATE SOP TH TH32 MISO IP PMU OUTV FREQ SPI 3PIN PACTL IP ACK TO IRQ GPIO IRQ IP 10100000 000--100 00000000 0000---1-000000 10100101 ----0100 ---01010 0-100000 10100100 00000000 00000000 --------------11111111 11111111 00000000 ----0000 00000--0 0000000brrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbb-bbbb bbb--bbb bbbbbbbb bbbbrrrr b-bbbbbb bbbbbbbb ----bbbb ---bbbbb r-rrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb ----bbbb wwwww--w bbbbbbb10111000 00000111 10010-10 rrrrrrrr bbbbbbbb bbbbb-bb TXE IRQEN b2 b1 b0 Default[4] -1001000 00000000 00000011 --000101 DATA MODE TXB8 IRQ RXB8 IRQEN TXB0 IRQ RXB1 IRQEN FAST TURN EN RXB1 IRQ Bad CRC Access[4] -bbbbbbb bbbbbbbb bbbbbbbb --bbbbbb
RX Data Mode
RX Count RX Length Not Used Not Used XOUT OD IRQ OP
XOUT FN IRQ OD XOUT OP ACK EN SOP EN Not Used Not Used SOP HEN IRQ POL MISO OP Not Used SOP LEN Not Used Not Used Not Used
AUTO_CAL_TIME_MAX AUTO_CAL_OFFSET_MINUS_4 RSVD RSVD
Register Files TX Buffer File RX Buffer File SOP Code File Data Code File Preamble File MFG ID File
Notes 4. b = read/write, r = read only, w = write only, - = not used, default value is undefined. 5. SOP_CODE_ADR default = 0x17FF9E213690C782. 6. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F. 7. PREAMBLE_ADR default = 0x333302.
Document #: 001-07552 Rev. *B
Page 58 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bits 6:0 7 Not Used 6 1 R/W
CHANNEL_ADR 5 0 R/W 4 0 R/W 3 1 R/W Channel 2 0 R/W
Address 1 0 R/W 0 0
0x00
R/W
This field selects the channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 are not valid. The default channel is a fast channel above the frequency typically used in non-overlapping WiFi systems. Any write to this register will impact the time it takes the synthesizer to settle. fast (100-s) - 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 96 medium (180-s) - 2 4 8 10 14 16 20 22 26 28 32 34 38 40 44 46 50 52 56 58 62 64 68 70 74 76 78 80 82 84 86 88 90 92 94 slow (270-s) - 1 5 7 11 13 17 19 23 25 29 31 35 35 37 41 43 47 49 53 55 59 61 65 67 71 73 75 77 79 81 83 85 87 89 91 93 95 97 Usable channels subject to regulation.
Do not access or modify this register during Transmit or Receive.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 R/W 6 0 R/W
TX_LENGTH_ADR 5 0 R/W 4 0 R/W TX Length 3 0 R/W 2 0 R/W
Address 1 0 R/W 0 0
0x01
R/W
This register sets the length of the packet to be transmitted. A length of zero is valid, and will transmit a packet with SOP, length and CRC16 fields (if enabled), but no data field. Packet lengths of more than 16 bytes will require that some data bytes be written after transmission of the packet has begun. Typically, length is updated prior to setting TX GO. The maximum packet length for all packets is 40 bytes except for framed 64-chip DDR where the maximum packet length is 16 bytes.
Maximum packet length is limited by the delta between the transmitter and receiver crystals of 60-ppm or better.
Mnemonic Bit Default Read/Write Function Bit 7 7 0 R/W TX GO 6 0 R/W TX CLR
TX_CTRL_ADR 5 0 R/W TXB15 IRQEN 4 0 R/W TXB8 IRQEN 3 0 R/W TXB0 IRQEN 2 0 R/W TXBERR IRQEN
Address 1 1 R/W TXC IRQEN 0 1
0x02
R/W TXE IRQEN
Start Transmission. Setting this bit triggers the transmission of a packet. Writing a 0 to this flag has no effect. This bit is cleared automatically at the end of packet transmission. The transmit buffer may be loaded either before or after setting this bit. If data is loaded after setting this bit, the length of time available to load the buffer depends on the starting state (sleep, idle or synth), the length of the SOP code, the length of preamble, and the packet data rate. For example, if starting from idle mode on a fast channel in 8DR mode with 32-chip SOP codes the time available is 100 s (synth start) + 32 s (preamble) + 64 s (SOP length) + 32 s (length byte) = 228 s. If there are no bytes in the TX buffer at the end of transmission of the length field, a TXBERR IRQ will occur. Clear TX Buffer. Writing a 1 to this register clears the transmit buffer. Writing a 0 to this bit has no effect. The previous packet may be retransmitted by setting TX GO and not setting this bit. A new transmit packet may be loaded and transmitted without setting this bit if TX GO is set after the new packet is loaded to the buffer. If the TX_BUFFER_ADR is to be loaded after the TX GO bit has been set, then this bit should be set before loading a new transmit packet to the buffer and before TX GO is set. Buffer Not Full Interrupt Enable. See TX_IRQ_STATUS_ADR for description. Buffer Half Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description. Buffer Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description. Buffer Error Interrupt Enable. See TX_IRQ_STATUS_ADR for description. Transmission Complete Interrupt Enable. See TX_IRQ_STATUS_ADR for description. TXC IRQEN and TXE IRQEN must be set together. Transmit Error Interrupt Enable. See TX_IRQ_STATUS_ADR for description. TXC IRQEN and TXE IRQEN must be set together.
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Document #: 001-07552 Rev. *B
Page 59 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bit 5 Bits 4:3 Bits 2:0 7 Not Used 6 Not Used
TX_CFG_ADR 5 0 R/W Data Code Length 4 0 R/W Data Mode 3 0 R/W 2 1 R/W
Address 1 0 R/W PA Setting 0 1
0x03
R/W
Data Code Length. This bit selects the length of the DATA_CODE_ADR code for the data portion of the packet. This bit is ignored when the data mode is set to GFSK. 1 = 64 chip codes, 0 = 32 chip codes. Data Mode. This field sets the data transmission mode. 00 = 1-Mbps GFSK, 01 = 8DR Mode, 10 = DDR Mode, 11 = SDR Mode. It is recommended that firmware sets the ALL SLOW bit in register ANALOG_CTRL_ADR when using GFSK data rate mode. PA Setting. This field sets the transmit signal strength. 0 = -30 dBm, 1 = -25 dBm, 2 = -20 dBm, 3 = -15 dBm, 4 = -10 dBm, 5 = -5 dBm, 6 = 0 dBm, 7 = +4 dBm.
Mnemonic Bit Default Read/Write Function 7 1 R OS IRQ
TX_IRQ_STATUS_ADR 6 0 R LV IRQ 5 1 R TXB15 IRQ 4 1 R TXB8 IRQ 3 1 R TXB0 IRQ 2 0 R TXBERR IRQ
Address 1 0 R TXC IRQ 0 0 R
0x04
TXE IRQ
The state of all IRQ status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags may change value at different times in response to a single event). In particular, standard error handling is only effective if the premature termination of a transmission due to an exception does not leave the device in an inconsistent state. Bit 7 Oscillator Stable IRQ Status. This bit is set when the internal crystal oscillator has settled (synthesizer sequence starts). Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Low Voltage Interrupt Status. This bit is set when the voltage on VBAT is below the LVI threshold (see PWR_CTL_ADR). This interrupt is automatically disabled whenever the PMU is disabled. When enabled, this bit reflects the voltage on VBAT. Buffer Not Full Interrupt Status. This bit is set whenever there are 15 or fewer bytes remaining in the transmit buffer. Buffer Half Empty Interrupt Status. This bit is set whenever there are 8 or fewer bytes remaining in the transmit buffer. Buffer Empty Interrupt Status. This bit is set at any time that the transmit buffer is empty. Buffer Error Interrupt Status. This IRQ is triggered by either of two events: (1) When the transmit buffer (TX_BUFFER_ADR) is empty and the number of bytes remaining to be transmitted is greater than zero; (2) When a byte is written to the transmit buffer and the buffer is already full. This IRQ is cleared by setting bit TX CLR in TX_CTRL_ADR. Transmission Complete Interrupt Status. This IRQ is triggered when transmission is complete. If transaction mode is not enabled then this interrupt is triggered immediately after transmission of the last bit of the CRC16. If transaction mode is enabled, this interrupt is triggered at the end of a transaction. Reading this register clears this bit. TXC IRQ and TXE IRQ flags may change value at different times in response to a single event. If transaction mode is enabled and the first read of this register returns TXC IRQ = 1 and TXE IRQ = 0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of TXE. There can be a case when this bit is not triggered when ACK EN = 1 and there is an error in transmission. If the first read of this register returns TXC IRQ = 1 and TXE IRQ = 1 then the firmware must not execute a second read to this register for a given transaction. If an ACK is received RXC IRQ and RXE IRQ may be asserted instead of TXC IRQ and TXE IRQ. Transmit Error Interrupt Status. This IRQ is triggered when there is an error in transmission. This interrupt is only applicable to transaction mode. It is triggered whenever no valid ACK packet is received within the ACK timeout period. Reading this register clears this bit.
Bit 1
Bit 0
Document #: 001-07552 Rev. *B
Page 60 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function 7 0 R/W RX GO 6 0 R/W RSVD
RX_CTRL_ADR 5 0 R/W RXB16 IRQEN 4 0 R/W RXB8 IRQEN 3 0 R/W RXB1 IRQEN 2 1 R/W RXBERR IRQEN
Address 1 1 R/W RXC IRQEN 0 1
0x05
R/W RXE IRQEN
Status bits are non-atomic (different flags may change value at different times in response to a single event). Bit 7 Start Receive. Setting this bit causes the device to transition to receive mode. If necessary, the crystal oscillator and synthesizer will start automatically after this bit is set. Firmware must never clear this bit. This bit must not be set until after it self clears. The recommended method to exit receive mode when an error has occurred is to force END STATE and then dummy read all RX_COUNT_ADR bytes from RX_BUFFER_ADR or poll RSSI_ADR.SOP (bit 7) until set. See XACT_CFG_ADR and RX_ABORT_ADR for description. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Bit Default Read/Write Function 7 1 R/W AGC EN 6 0 R/W LNA Start of Packet Detect Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Buffer Full Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Buffer Half Empty Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Buffer Not Empty Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Buffer Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Packet Reception Complete Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Receive Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description. RX_CFG_ADR 5 0 R/W ATT 4 1 R/W HILO 3 0 R/W FAST TURN EN 2 Not Used Address 1 1 R/W RXOW EN 0 0 R/W VLD EN 0x06
Status bits are non-atomic (different flags may change value at different times in response to a single event). Bit 7 Automatic Gain Control (AGC) Enable. When this bit is set, AGC is enabled, and the LNA is controlled by the AGC circuit. When this bit is cleared the LNA is controlled manually using the LNA bit. Typical applications will clear this bit during initialization. It is recommended that this bit be disabled and bit 6 (LNA) be enabled unless the device will be used in a system where it may receive data from a device using an external PA to transmit signals at >+4 dBm. Low Noise Amplifier (LNA) Manual Control. When AGC EN (Bit 7) is cleared, this bit controls the state of the receiver LNA; when AGC EN is set, this bit has no effect. Setting this bit enables the LNA; clearing this bit disables the LNA. Device current in receive mode is slightly lower when the LNA is disabled. Typical applications will set this bit during initialization. Receive Attenuator Enable. Setting this bit enables the receiver attenuator. The receiver attenuator may be used to desensitize the receiver so that only very strong signals may be received. This bit should only be set when the AGC EN is disabled and the LNA is manually disabled. HILO. When FAST TURN EN is set, this bit is used to select whether the device will use the high frequency for the channel selected, or the low frequency. 1 = hi; 0 = lo. When FAST TURN EN is not enabled this also controls the highlow bit to the receiver and should be left at the default value of 1 for high side receive injection. Typical applications will clear this bit during initialization. Fast Turn Mode Enable. When this bit is set, the HILO bit determines whether the device receives data transmitted 1MHz above the RX Synthesizer frequency or 1 MHz below the receiver synthesizer frequency. Use of this mode allows for very fast turnaround, because the same synthesizer frequency may be used for both transmit and receive, thus eliminating the synthesizer resettling period between transmit and receive. Note that when this bit is set, and the HILO bit is cleared, received data bits are automatically inverted to compensate for the inversion of data received on the `image' frequency. Typical applications will set this bit during initialization. Overwrite Enable. When this bit is set, if an SOP is detected while the receive buffer is not empty, then the existing contents of receive buffer are lost, and the new packet is loaded into the receive buffer. When this bit is set, the RXOW IRQ is enabled. If this bit is cleared, then the receive buffer may not be overwritten by a new packet, and whenever the receive buffer is not empty SOP conditions are ignored, and it is not possible to receive data until the previously received packet has been completely read from the receive buffer. Valid Flag Enable. When this bit is set, the receive buffer can store only 8 bytes of data. The other half of the buffer is used to store valid flags. See RX_BUFFER_ADR for more detail.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
Document #: 001-07552 Rev. *B
Page 61 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function 7 0 R/W RXOW IRQ
RX_IRQ_STATUS_ADR 6 0 R RSVD 5 0 R RXB16 IRQ 4 0 R RXB8 IRQ 3 0 R RXB1 IRQ 2 0 R RXBERR IRQ
Address 1 0 R RXC IRQ 0 0 R
0x07
RXE IRQ
The state of all IRQ Status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags may change value at different times in response to a single event). In particular, standard error handling is only effective if the premature termination of a transmission due to an exception does not leave the device in an inconsistent state. Bit 7 Receive Overwrite Interrupt Status. This IRQ is triggered when the receive buffer is overwritten by a packet being received before the previous packet has been read from the buffer. This bit is cleared by writing any value to this register. This condition is only possible when the RXOW EN bit in RX_CFG_ADR is set. This bit must be written `1' by firmware before the new packet may be read from the receive buffer. Bit 6 Bit 5 Bit 4 Reserved. Must not be set. Receive Buffer Full Interrupt Status. This bit is set whenever the receive buffer is full, and cleared otherwise. Receive Buffer Half Full Interrupt Status. This bit is set whenever there are eight or more bytes remaining in the receive buffer. Firmware must read exactly eight bytes when reading RXB8 IRQ. It is possible, in rare cases, that the last byte of a packet may remain in the buffer even though the RXB1_IRQ flag has cleared. This can ONLY happen on the last byte of a packet and only if the packet data is being read out of the buffer while the packet is still being received. The flag is trustworthy under all other conditions, and for all bytes prior to the last. When using RXB1_IRQ and unloading the packet data during reception, the user should be sure to check the RX_COUNT_ADR value after the RXC/RXE is set and unload the last remaining byte if the number of bytes unloaded is less than the reported count, even though the RXB1_IRQ is not set Receive Buffer Not Empty Interrupt Status. This bit is set at any time that there are 1 or more bytes in the receive buffer, and cleared when the receive buffer is empty. RXB1 IRQ must not be set when RXB8 IRQ is set and vice versa. Receive Buffer Error Interrupt Status. This IRQ is triggered in one of two ways: (1) When the receive buffer is empty and there is an attempt to read data; (2) When the receive buffer is full and more data is received. This flag is cleared when RX GO is set and a SOP is received. Packet Receive Complete Interrupt Status. This IRQ is triggered when a packet has been received. If transaction mode is enabled, then this bit is not set until after transmission of the ACK. If transaction mode is not enabled then this bit is set as soon as a valid packet is received. This bit is cleared when this register is read. RXC IRQ and RXE IRQ flags may change value at different times in response to a single event. There are cases when this bit is not triggered when ACK EN = 1 and there is an error in reception. Therefore, firmware should examine RXC IRQ, RXE IRQ, and CRC 0 to determine receive status. If the first read of this register returns RXC IRQ = 1 and RXE IRQ = 0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of RXE IRQ. If the first read of this register returns RXC IRQ = 1 and RXE IRQ = 1 then the firmware must not execute a second read to this register for a given transaction. Receive Error Interrupt Status. This IRQ is triggered when there is an error in reception. It is triggered whenever a packet is received with a bad CRC16, an unexpected EOP is detected, a packet type (data or ACK) mismatch, or a packet is dropped because the receive buffer is still not empty when the next packet starts. The exact cause of the error may be determined by reading RX_STATUS_ADR. This bit is cleared when this register is read.
Bit 3 Bit 2
Bit 1
Bit 0
Document #: 001-07552 Rev. *B
Page 62 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function 7 0 R RX ACK 6 0 R
RX_STATUS_ADR 5 0 R EOP ERR 4 0 R CRC0 3 1 R Bad CRC 2 R RX Code
Address 1 R 0 R
0x08
PKT ERR
RX Data Mode
It is expected that firmware does not read this register until after TX GO self clears. Status bits are non-atomic (different flags may change value at different times in response to a single event). Bit 7 RX Packet Type. This bit is set when the received packet is an ACK packet, and cleared when the received packet is a standard packet. Bit 6 Bit 5 Receive Packet Type Error. This bit is set when the packet type received is not what was expected and cleared when the packet type received was as expected. For example, if a data packet is expected and an ACK is received, this bit will be set. Unexpected EOP. This bit is set when an EOP is detected before the expected data length and CRC16 fields have been received. This bit is cleared when SOP pattern for the next packet has been received. This includes the case where there are invalid bits detected in the length field and the length field is forced to 0. Zero-seed CRC16. This bit is set whenever the CRC16 of the last received packet has a zero seed. Bad CRC16. This bit is set when the CRC16 of the last received packet is incorrect. Receive Code Length. This bit indicates the DATA_CODE_ADR code length used in the last correctly received packet. 1 = 64-chip code, 0 = 32-chip code. Receive Data Mode. These bits indicate the data mode of the last correctly received packet. 00 = 1-Mbps GFSK, 01 = 8DR, 10 = DDR, 11 = Not Valid. These bits do not apply to unframed packets.
Bit 4 Bit 3 Bit 2 Bits 1:0
Mnemonic Bit Default Read/Write Function 7 0 R 6 0 R
RX_COUNT_ADR 5 0 R 4 0 R RX Count 3 0 R 2 0 R
Address 1 0 R 0 0 R
0x09
Count bits are non-atomic (updated at different times). Bits 7:0 This register contains the total number of payload bytes received during reception of the current packet. After packet reception is complete, this register will match the value in RX_LENGTH_ADR unless there was a packet error. This register is reset to 0x00 when RX_LENGTH_ADR is loaded. Count should not be read when RX_GO = 1 during a transaction.
Mnemonic Bit Default Read/Write Function 7 0 R 6 0 R
RX_LENGTH_ADR 5 0 R 4 0 R RX Length 3 0 R 2 0 R
Address 1 0 R 0 0 R
0x0A
Length bits are non-atomic (different flags may change value at different times in response to a single event). Bits 7:0 This register contains the length field which is updated with the reception of a new length field (shortly after start of packet detected). If there is an error in the received length field, 0x00 is loaded instead, except when using GFSK datarate, and an error is flagged.
Document #: 001-07552 Rev. *B
Page 63 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bit 7 Bit 6 7 1 R/W PMU EN 6 0 R/W
PWR_CTRL_ADR 5 1 R/W PMU MODE FORCE 4 Not Used 3 0 R/W LVI TH 2 0 R/W
Address 1 0 R/W 0 0
0x0B
R/W
LVIRQ EN
PMU OUTV
Power Management Unit (PMU) Enable. Setting this bit enables the PMU if PMU Mode Force (bit 5) is set, otherwise it has no effect. See PMU Mode Force bit (bit 5) description. Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the VBAT voltage falls below the threshold set by LVI TH, then a low voltage interrupt will be generated. The LVI is not available when the device is in sleep mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled. PMU Mode Force. If this bit is set, the PMU operation will be based on the value of PMU Enable bit (bit 7). If this bit is not set, then the PMU is diabled when in Sleep mode and enabled when not in Sleep mode. Low Voltage Interrupt Threshold. This field sets the voltage on VBAT at which the LVI is triggered. 11 = 1.8V, 10 = 2.0V, 01 = 2.2V, 00 = PMU OUTV voltage. PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V, 10 = 2.5V, 01 = 2.6V, 00 = 2.7V. When the PMU is active, the voltage output by the PMU on VREG will never be less than this voltage, provided that the total load on the VREG pin is less than the specified maximum value and the voltage in VBAT is greater than the specified minimum value.
Bit 5 Bits 3:2 Bits 1:0
To force the chip to always enable the PMU (including in Sleep mode), set bit 5 and bit 7. To force the chip to always disable the PMU set bit 5 and clear bit 7. To allow the chip to disable PMU only during sleep clear bit 5. The sequence of writing the bits in this register impact the sleep current ISB .
Mnemonic Bit Default Read/Write Function Bits 7:6 7 0 R/W XOUT FN 6 0 R/W
XTAL_CTRL_ADR 5 0 R/W XSIRQ EN 4 Not Used 3 Not Used 2 1 R/W
Address 1 0 R/W FREQ 0 0
0x0C
R/W
XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire mode then the MISO pin will output a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to GPIO mode, and set the GPIO state in IO_CFG_ADR. Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event when the crystal has stabilized after the device has woken from sleep mode. This event is cleared by writing zero to this bit. XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz, 1 = 6 MHz, 2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
Bit 5 Bits 2:0
Document #: 001-07552 Rev. *B
Page 64 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function 7 0 R/W IRQ OD 6 0 R/W IRQ POL
IO_CFG_ADR 5 0 R/W MISO OD 4 0 R/W XOUT OD 3 0 R/W PACTL OD 2 0 R/W PACTL GPIO
Address 1 0 R/W SPI 3PIN 0 0
0x0D
R/W IRQ GPIO
To use a GPIO pin as an input, the output mode must be set to open drain, and a `1' written to the corresponding output register bit. Bit 7 IRQ Pin Drive Strength. Setting this bit configures the IRQ pin as an open drain output. Clearing this bit configures the IRQ pin as a standard CMOS output, with the output `1' drive voltage being equal to the VIO pin voltage. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IRQ Polarity. Setting this bit configures the IRQ signal polarity to be active HIGH. Clearing this bit configures the IRQ signal polarity to be active LOW. MISO Pin Drive Strength. Setting this bit configures the MISO pin as an open drain output. Clearing this bit configures the MISO pin as a standard CMOS output, with the output `1' drive voltage being equal to the VIO pin voltage. XOUT Pin Drive Strength. Setting this bit configures the XOUT pin as an open drain output. Clearing this bit configures the XOUT pin as a standard CMOS output, with the output '1' drive voltage being equal to the VIO pin voltage. PACTL Pin Drive Strength. Setting this bit configures the PACTL pin as an open drain output. Clearing this bit configures the PACTL pin as a standard CMOS output, with the output '1' drive voltage being equal to the VIO pin voltage. PACTL Pin Function. When this bit is set the PACTL pin is available for use as a GPIO. SPI Mode. When this bit is cleared, the SPI interface acts as a standard 4-wire SPI Slave interface. When this bit is set, the SPI interface operates in `3-Wire Mode' combining MISO and MOSI on the same pin (SDAT), and the MISO pin is available as a GPIO pin. IRQ Pin Function. When this bit is cleared, the IRQ pin is asserted when an IRQ is active; the polarity of this IRQ signal is configurable in IRQ POL. When this bit is set, the IRQ pin is available for use as a GPIO pin, and the IRQ function is multiplexed onto the MOSI pin. In this case the IRQ signal state is presented on the MOSI pin whenever the SS signal is inactive (HIGH).
Bit 0
Mnemonic Bit Default Read/Write Function 7 0 R/W XOUT OP 6 0 R/W
GPIO_CTRL_ADR 5 0 R/W PACTL OP 4 0 R/W IRQ OP 3 R XOUT IP 2 R MISO IP
Address 1 R PACTL IP 0 R
0x0E
MISO OP
IRQ IP
To use a GPIO pin as an input, the output mode must be set to open drain, and a '1' written to the corresponding output register bit. Bit 7 XOUT Output. When the XOUT pin is configured to be a GPIO, the state of this bit sets the output state of the XOUT pin. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO Output. When the MISO pin is configured to be a GPIO, the state of this bit sets the output state of the MISO pin. PACTL Output. When the PACTL pin is configured to be a GPIO, the state of this bit sets the output state of the PACTL pin. IRQ Output. When the IRQ pin is configured to be a GPIO, the state of this bit sets the output state of the IRQ pin. XOUT Input. When the XOUT pin is configured to be a GPIO, the state of this bit reflects the voltage on the XOUT pin. MISO Input. When the MISO pin is configured to be a GPIO, the state of this bit reflects the voltage on the MISO pin. PACTL Input. When the PACTL pin is configured to be a GPIO, the state of this bit reflects the voltage on the PACTL pin. IRQ Input. When the IRQ pin is configured to be a GPIO, the state of this bit reflects the voltage on the IRQ pin.
Document #: 001-07552 Rev. *B
Page 65 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bit 7 7 1 R/W ACK EN 6 -
XACT_CFG_ADR 5 0 R/W FRC END 4 0 R/W 3 0 R/W END STATE 2 0 R/W
Address 1 0 R/W ACK TO 0 0
0x0F
R/W
Not Used
Acknowledge Enable. When this bit is set, an ACK packet is automatically transmitted whenever a valid packet is received; in this case the device is considered to be in transaction mode. After transmission of the ACK packet, the device automatically transitions to the END STATE. When this bit is cleared, the device transitions directly to the END STATE immediately after the end of packet transmission. Force End State. Setting this bit forces a transition to the state set in END STATE. By setting the desired END STATE at the same time as setting this bit the device may be forced to immediately transition from its current state to any other state. This bit is automatically cleared upon completion. Transaction End State. This field defines the mode to which the device transitions after receiving or transmitting a packet. 000 = Sleep Mode; 001 = Idle Mode; 010 = Synth Mode (TX); 011 = Synth Mode (RX); 100 = RX Mode. In normal use, this field will typically be set to 000 or 001 when the device is transmitting packets and 100 when the device is receiving packets. Note that when the device transitions to receive mode as an END STATE, the receiver must still be armed by setting RX GO before the device can begin receiving data. If the system only support packets <=16 bytes then firmware should examine RXC IRQ and RXE IRQ to determine the status of the packet. If the system supports packets > 16 bytes ensure that END STATE is not sleep, force RXF = 1, perform receive operation, force RXF = 0, and if necessary set END STATE back to sleep. ACK Timeout. When the device is configured for transaction mode, this field sets the timeout period after transmission of a packet during which an ACK must be correctly received in order to prevent a transmit error condition from being detected. This timeout period is expressed in terms of a number of SOP_CODE_ADR code lengths; if SOP LEN is set, then the timeout period is this value multiplied by 64 s and if SOP LEN is cleared then the timeout is this value multiplied by 32 s. 00 = 4x, 01 = 8x, 10 = 12x, 11 = 15x the SOP_CODE_ADR code length. ACK_TO must be set to greater than 30 + Data Code Length (only for 8DR) + Preamble Length + SOP Code Length (x2).
Bit 5
Bits 4:2
Bits 1:0
Mnemonic Bit Default Read/Write Function Bit 7 7 1 R/W SOP EN
FRAMING_CFG_ADR 6 0 R/W SOP LEN 5 1 R/W LEN EN 4 0 R/W 3 0 R/W 2 1 R/W SOP TH
Address 1 0 R/W 0 1
0x10
R/W
SOP Enable. When this bit is set, each transmitted packet begins with a SOP field, and only packets beginning with a valid SOP field will be received. If this bit is cleared, no SOP field will be generated when a packet is transmitted, and packet reception will begin whenever two successive correlations against the DATA_CODE_ADR code are detected. SOP PN Code Length. When this bit is set the SOP_CODE_ADR code length is 64 chips. When this bit is cleared the SOP_CODE_ADR code length is 32 chips. Packet Length Enable. When this bit is set the 8-bit value contained in TX_LENGTH_ADR is transmitted immediately after the SOP field. In receive mode, the 8 bits immediately following the SOP field are interpreted as the length of the packet. When this bit is cleared no packet length field is transmitted. 8DR always sends the packet length field (forces LEN EN = 1). GFSK requires user set LEN EN = 1. SOP Correlator Threshold. This is the receive data correlator threshold used when attempting to detect a SOP symbol. There is a threshold for the SOP_CODE_ADR code. This (single) threshold is applied independently to each of SOP1 and SOP2 fields. There are then two thresholds for each of the 64-chip DATA_CODE_ADR codes and 32-chip DATA_CODE_ADR codes. When SOP LEN is set, all 5 bits of this field are used. When SOP LEN is cleared, the most significant bit is disregarded. Typical applications configure SOP TH = 04h for SOP32 and SOP TH = 0Eh for SOP64.
Bit 6 Bit 5
Bits 4:0
Document #: 001-07552 Rev. *B
Page 66 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bits 3:0: 7 Not Used
DATA32_THOLD_ADR 6 Not Used 5 Not Used 4 Not Used 3 0 R/W 2 1 R/W TH32
Address 1 0 R/W 0 0
0x11
R/W
32-chip Data PN Code Correlator Threshold. This register sets the correlator threshold used in DSSS modes when DATA CODE LENGTH (see TX_CFG_ADR) is set to 32. Typical applications configure TH32 = 05h.
Mnemonic Bit Default Read/Write Function Bits 4:0 7 Not Used
DATA64_THOLD_ADR 6 Not Used 5 Not Used 4 0 R/W 3 1 R/W 2 0 R/W TH64
Address 1 1 R/W 0 0
0x12
R/W
64 Chip Data PN Code Correlator Threshold. This register sets the correlator threshold used in DSSS modes when the DATA CODE LENGTH (see TX_CFG_ADR) is set to 64. Typical applications configure TH64 = 0Eh.
Mnemonic Bit Default Read/Write Function 7 0 R SOP 6 Not Used
RSSI_ADR 5 1 R LNA 4 0 R 3 0 R 2 0 R RSSI
Address 1 0 R 0 0 R
0x13
A Received Signal Strength Indicator (RSSI) reading is taken automatically when an SOP symbol is detected. In addition, an RSSI reading is taken whenever RSSI_ADR is read. The contents of this register are not valid after the device is configured for receive mode until either a SOP symbol is detected, or the register is read. The conversion can occur as often as once every 12 s. To measure the background RF signal strength on a channel before a packet has been received, the MCU should perform a `dummy' read of this register, the results of which should be discarded. This `dummy' read will cause an RSSI measurement to be taken, and therefore subsequent readings of the register will yield valid data. Bit 7 SOP RSSI Reading. When set, this bit indicates that the reading in the RSSI field was taken when a SOP symbol was detected. When cleared, this bit indicates that the reading stored in the RSSI field was triggered by a previous SPI read of this register. Bit 5 LNA State. This bit indicates the LNA state when the RSSI reading was taken. When cleared, this bit indicates that the LNA was disabled when the RSSI reading was taken; if set, this bit indicates that the LNA was enabled when the RSSI reading was taken. RSSI Reading. This field indicates the instantaneous strength of the RF signal being received at the time that the RSSI reading was taken. A larger value indicates a stronger signal. The signal strength measured is for the RF signal on the configured channel, and is measured after the LNA stage.
Bits 4:0
Document #: 001-07552 Rev. *B
Page 67 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function 7 1 R/W HEN 6 0 R/W
EOP_CTRL_ADR 5 1 R/W HINT 4 0 R/W 3 0 R/W 2 1 R/W EOP
Address 1 0 R/W 0 0
0x14
R/W
If the LEN EN bit is set, then the contents of this register have no effect. If the LEN EN bit is cleared, then this register is used to configure how an EOP (end of packet) condition is detected. Bit 7 EOP Hint Enable. When set, this bit will cause an EOP to be detected if no correlations have been detected for the number of symbol periods set by the HINT field and the last two received bytes match the calculated CRC16 for all previously received bytes. Use of this mode reduces the chance of non-correlations in the middle of a packet from being detected as an EOP condition. Bits 6:4 Bits 4:0 EOP Hint Symbol Count. The minimum number of symbols of consecutive non-correlations at which the last two bytes are checked against the calculated CRC16 to detect an EOP condition. EOP Symbol Count. An EOP condition is deemed to exist when the number of consecutive non-correlations is detected.
Mnemonic Bit Default Read/Write Function 7 0 R/W
CRC_SEED_LSB_ADR 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W
Address 1 0 R/W 0 0
0x15
R/W
CRC SEED LSB
The CRC16 seed allows different devices to generate or recognize different CRC16s for the same payload data. If a transmitter and receiver use a randomly selected CRC16 seed, the probability of correctly receiving data intended for a different receiver is 1/65535, even if the other transmitter/receiver are using the same SOP_CODE_ADR codes and channel. Bits 7:0 CRC16 Seed Least Significant Byte. The LSB of the starting value of the CRC16 calculation.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 R/W
CRC_SEED_MSB_ADR 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W
Address 1 0 R/W 0 0
0x16
R/W
CRC SEED MSB CRC16 Seed Most Significant Byte. The MSB of the starting value of the CRC16 calculation.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 R 6 R
TX_CRC_LSB_ADR 5 R 4 R TX CRC LSB 3 R 2 R
Address 1 R 0 R
0x17
Calculated CRC16 LSB. The LSB of the CRC16 that was calculated for the last transmitted packet. This value is only valid after packet transmission is complete.
Document #: 001-07552 Rev. *B
Page 68 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bits 7:0 7 R 6 R
TX_CRC_MSB_ADR 5 R 4 R 3 R 2 R 1
Address 0 R R
0x18
TX CRC MSB Calculated CRC16 MSB. The MSB of the CRC16 that was calculated for the last transmitted packet. This value is only valid after packet transmission is complete.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 1 R 6 1 R
RX_CRC_LSB_ADR 5 1 R 4 1 R RX CRC LSB 3 1 R 2 1 R
Address 1 1 R 0 1 R
0x19
Received CRC16 LSB. The LSB of the CRC16 field from the last received packet. This value is valid whether or not the CRC16 field matched the calculated CRC16 of the received packet.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 1 R 6 1
RX_CRC_MSB_ADR 5 1 R 4 1 R 3 1 R 2 1 R
Address 1 1 R 0 1 R
0x1A
R
RX CRC MSB Received CRC16 MSB. The MSB of the CRC16 field from the last received packet. This value is valid whether or not the CRC16 field matched the calculated CRC16 of the received packet.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 R/W
TX_OFFSET_LSB_ADR 6 0 R 5 0 R 4 0 R STRIM LSB 3 0 R 2 0 R
Address 1 0 R 0 0 R
0x1B
The least significant 8 bits of the synthesizer offset value. This is a 12-bit 2's complement signed number, which may be used to offset the transmit frequency of the device by up to 1.5 MHz. A positive value increases the transmit frequency, and a negative value reduces the transmit frequency. A value of +1 increases the transmit frequency by 732.6 Hz; a value of -1 decreases the transmit frequency by 732.6 Hz. A value of 0x0555 increases the transmit frequency by 1 MHz; a value of 0xAAB decreases the transmit frequency by 1 MHz. Typically, this register is loaded with 0x55 during initialization. This feature is typically used to avoid the need to change the synthesizer frequency when switching between TX and RX. As the IF = 1 MHz the RX frequency is offset 1 MHz from the synthesizer frequency; therefore, transmitting with a 1-MHz offset allows the same synthesizer frequency to be used for both transmit and receive.
Synthesizer offset has no effect on receive frequency.
Mnemonic Bit Default Read/Write Function Bits 3:0 7 Not Used
TX_OFFSET_MSB_ADR 6 Not Used 5 Not Used 4 Not Used 3 0 R/W 2 0 R/W
Address 1 0 R/W 0 0
0x1C
R/W
STRIM MSB
The most significant 4 bits of the synthesizer trim value. Typically, this register is loaded with 0x05 during initialization.
Document #: 001-07552 Rev. *B
Page 69 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bits 7 Bits 5 Bits 4:3 Bits 0 Mnemonic Bit Default Read/Write Function Bits 7 Bits 6 Bits 5 Bits 4 Bits 3 Bits 2 Bits 1 7 0 R/W ACK RX 7 0 W RSVD
MODE_OVERRIDE_ADR 6 0 W RSVD 5 0 W FRC SEN 4 0 W FRC AWAKE 3 0 W 2 Not Used
Address 1 Not Used 0 0 W
0x1D
RST
Reserved. Do not write a 1 to these bits. Manually Initiate Synthesizer. Setting this bit forces the synthesizer to start. Clearing this bit has no effect. For this bit to operate correctly, the oscillator must be running before this bit is set. Force Awake. Force the device out of sleep mode. Setting both bits of this field forces the oscillator to keep running at all times regardless of the END STATE setting. Clearing both of these bits disables this function. Reset. Setting this bit forces a full reset of the device. Clearing this bit has no effect. RX_OVERRIDE_ADR 6 0 R/W RXTX DLY 5 0 R/W MAN RXACK 4 0 R/W FRC RXDR 3 0 R/W DIS CRC0 2 0 R/W DIS RXCRC Address 1 0 R/W ACE 0 Not Used 0x1E
This register provides the ability to override some automatic features of the device. When this bit is set, the device uses the transmit synthesizer frequency rather than the receive synthesizer frequency for the given channel when automatically entering receive mode. When this bit is set and ACK EN is enabled, the transmission of the ACK packet is delayed by 20 s. Force Expected Packet Type. When this bit is set, and the device is in receive mode, the device is configured to receive an ACK packet at the data rate defined in TX_CFG_ADR. Force Receive Data Rate. When this bit is set, the receiver will ignore the data rate encoded in the SOP symbol, and will receive data at the data rate defined in TX_CFG_ADR. Reject packets with a zero-seed CRC16. Setting this bit causes the receiver to reject packets with a zero-seed, and accept only packets with a CRC16 that matches the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. The RX CRC16 checker is disabled. If packets with CRC16 enabled are received, the CRC16 will be treated as payload data and stored in the receive buffer. Accept Bad CRC16. Setting this bit causes the receiver to accept packets with a CRC16 that do not match the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. An ACK is to be sent regardless of the condition of the received CRC16.
Mnemonic Bit Default Read/Write Function Bits 7 Bits 6 Bits 5 Bits 4 Bits 3 Bits 2 Bits 1 Bits 0 7 0 R/W ACK TX
TX_OVERRIDE_ADR 6 0 R/W FRC PRE 5 0 R/W RSVD 4 0 R/W MAN TXACK 3 0 R/W OVRD ACK 2 0 R/W DIS TXCRC
Address 1 0 R/W RSVD 0 0
0x1F
R/W TX INV
This register provides the ability to override some automatic features of the device. When this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the given channel when automatically entering transmit mode. Force Preamble. When this bit is set, the device will transmit a continuous repetition of the preamble pattern (see PREAMBLE_ADR) after TX GO is set. This mode is useful for some regulatory approval procedures. Reserved. Do not write a 1 to this bit. Transmit ACK Packet. When this bit is set, the device sends an ACK packet when TX GO is set. ACK Override. Use TX_CFG_ADR to determine the data rate and the CRC16 used when transmitting an ACK packet. Disable Transmit CRC16. When set, no CRC16 field is present at the end of transmitted packets. Reserved. Do not write a 1 to this bit. TX Data Invert. When this bit is set the transmit bitstream is inverted.
Document #: 001-07552 Rev. *B
Page 70 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bits 7:2 Bits 1 Bits 0 7 0 W RSVD 6 0 W
CLK_OFFSET_ADR 5 0 W RSVD 4 0 W RSVD 3 0 W RSVD 2 0 W RSVD
Address 1 0 W RXF 0 0 W
0x27
RSVD
RSVD
This register provides the ability to override some automatic features of the device. Reserved. Do not write a 1 to these bits. Force Receive Clock Reserved. Do not write a 1 to this bit.
Mnemonic Bit Default Read/Write Function Bits 7:2 Bits 1 Bits 0 7 0 W RSVD 6 0 W RSVD
CLK_EN_ADR 5 0 W RSVD 4 0 W RSVD 3 0 W RSVD 2 0 W RSVD
Address 1 0 W RXF 0 0 W
0x28
RSVD
This register provides the ability to override some automatic features of the device. Reserved. Do not write a 1 to these bits. Force Receive Clock Enable. Typical application will set this bit during initialization. Reserved. Do not write a 1 to this bit.
Mnemonic Bit Default Read/Write Function Bits 7:6 Bits 5 Bits 4:0 7 0 W RSVD 6 0 W RSVD
RX_ABORT_ADR 5 0 W ABORT EN 4 0 W RSVD 3 0 W RSVD 2 0 W RSVD
Address 1 0 W RSVD 0 0 W
0x29
RSVD
This register provides the ability to override some automatic features of the device. Reserved. Do not write a 1 to these bits. Receive Abort Enable. Reserved. Do not write a 1 to these bits.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 W
AUTO_CAL_TIME_ADR 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W
Address 1 1 W 0 1 W
0x32
AUTO_CAL_TIME_MAX Auto Cal Time Max. Firmware must write 3Ch to this register during initialization.
This register provides the ability to over-ride some automatic features of the device.
Document #: 001-07552 Rev. *B
Page 71 of 85
[+] Feedback
CYRF69213
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 W
AUTO_CAL_OFFSET_ADR 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W
Address 1 0 W 0 0 W
0x35
AUTO_CAL_OFFSET_MINUS_4 Auto Cal Time Max. Firmware must write 14h to this register during initialization.
This register provides the ability to override some automatic features of the device.
Mnemonic Bit Default Read/Write Function Bits 7:1 Bits 0 7 0 W RSVD
ANALOG_CTRL_ADR 6 0 W RSVD 5 0 W RSVD 4 0 W RSVD 3 0 W RSVD 2 0 W RSVD
Address 1 0 W RSVD 0 0 W
0x39
ALL SLOW
This register provides the ability to over-ride some automatic features of the device. Reserved. Do not write a 1 to these bits. All Slow. When set, the synth settling time for all channels is the same as for slow channels. It is recommended that firmware set this bit when using GFSK data rate mode.
Document #: 001-07552 Rev. *B
Page 72 of 85
[+] Feedback
CYRF69213
Register Files Files are written to or read from using non-incrementing burst read or write transactions. In most cases reading a file may be destructive; the file must be completely read, otherwise the contents may be altered.
Mnemonic Length Default TX_BUFFER_ADR 16 Bytes 0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Address R/W 0x20 W
The transmit buffer is a FIFO. Writing to this file adds a byte to the packet being sent. Writing more bytes to this file than the packet length in TX_LENGTH_ADR will have no effect, and these bytes will be lost after successful packet transmission. It is NOT possible to load two 8-byte packets into this register, and then transmit them sequentially by enabling the TX GO bit twice; this would have the effect of sending the first eight bytes twice.
Mnemonic Length Default
RX_BUFFER_ADR 16 Bytes 0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Address R/W
0x21 R
The receive buffer is a FIFO. Received bytes may be read from this file register at any time that it is not empty, but when reading from this file register before a packet has been completely received care must be taken to ensure that error packets (for example with bad CRC16) are handled correctly. When the receive buffer is configured to be overwritten by new packets (the alternative is for new packets to be discarded if the receive buffer is not empty), similar care must be taken to verify after the packet has been read from the buffer that no part of it was overwritten by a newly received packet while this file register is being read. When the VLD EN bit in RX_CFG_ADR is set, the bytes in this file register alternate--the first byte read is data, the second byte is a valid flag for each bit in the first byte, the third byte is data, the fourth byte valid flag, and so on. In SDR and DDR modes the valid flag for a bit is set if the correlation coefficient for the bit exceeded the correlator threshold, and is cleared if it did not. In 8DR mode, the MSB of a valid flag byte indicates whether or not the correlation coefficient of the corresponding received symbol exceeded the threshold. The seven LSBs contain the number of erroneous chips received for the data.
Mnemonic Length Default
SOP_CODE_ADR 8 Bytes 0x17FF9E213690C782
Address R/W
0x22 R/W
When using 32-chip SOP_CODE_ADR codes, only the first four bytes of this register are used; in order to complete the file write process, these four bytes must be followed by four bytes of `dummy' data. However, a class of codes known as `multiplicative codes' may be used; there are 64-chip codes with good auto-correlation and cross-correlation properties where the least significant 32 chips themselves have good auto-correlation and cross-correlation properties when used as 32-chip codes. In this case the same eight-byte value may be loaded into this file and used for both 32-chip and 64-chip SOP symbols. When reading this file, all eight bytes must be read; if fewer than eight bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This applies to writes, as well. Recommended SOP Codes: 0x91CCF8E291CC373C 0x0FA239AD0FA1C59B 0x2AB18FD22AB064EF 0x507C26DD507CCD66 0x44F616AD44F6E15C 0x46AE31B646AECC5A 0x3CDC829E3CDC78A1 0x7418656F74198EB9 0x49C1DF6249C0B1DF 0x72141A7F7214E597 Do not access or modify this register during Transmit or Receive.
Document #: 001-07552 Rev. *B
Page 73 of 85
[+] Feedback
CYRF69213
Mnemonic Length Default
DATA_CODE_ADR 16 Bytes
0x02F9939702FA5CE3012BF1DB0132BE6F
Address R/W
0x23 R/W
This file is ignored when using the device in 1-Mbps GFSK mode. In 64-SDR mode, only the first eight bytes are used; in order to complete the file write process, these eight bytes must be followed by eight bytes of `dummy' data. In 32-SDR mode, only four bytes are used, and in 32-DDR mode only eight bytes are used. In 64-DDR and 8DR modes, all sixteen bytes are used. Certain sixteen-byte sequences have been calculated that provide excellent auto-correlation and cross-correlation properties, and it is recommended that such sequences be used; the default value of this register is one such sequence. In typical applications, all devices use the same DATA_CODE_ADR codes, and devices and systems are addressed by using different SOP_CODE_ADR codes; in such cases it may never be necessary to change the contents of this register from the default value. When reading this file, all sixteen bytes must be read; if fewer than sixteen bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This applies to writes, as well. Typical applications should use the default code. Do not access or modify this register during Transmit or Receive.
Mnemonic Length Default
PREAMBLE_ADR 3 Bytes 0x333302
Address R/W
0x24 R/W
Byte 1 - The number of repetitions of the preamble sequence that are to be transmitted. The preamble may be disabled by writing 0x00 to this byte. Byte 2 - Least significant eight chips of the preamble sequence Byte 3- Most significant eight chips of the preamble sequence If using 64-SDR to communicate with CYWUSB69xx devices, set number of repetitions to four for optimum performance When reading this file, all three bytes must be read; if fewer than three bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This applies to writes, as well. Do not access or modify this register during Transmit or Receive.
Mnemonic Length Default
MFG_ID_ADR 6 Bytes NA
Address R
0x25 R
Byte 1 - 4 bits version + 2 bits vendor ID + high 2 bits of Year Byte 2 through Byte 6: Manufacturing ID for the device. To minimize ~190 A of current consumption (default), execute a `dummy' single-byte SPI write to this address with a zero data stage after the contents have been read. Non-zero to enable reading of fuses. Zero to disable reading fuses.
Absolute Maximum Ratings
Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied ........ 0C to +70C Supply Voltage on any power supply pin relative to VSS-0.3V to +3.9V DC Voltage to Logic Inputs[8] ................... -0.3V to VIO +0.3V DC Voltage applied to Outputs in High-Z State .. -0.3V to VIO +0.3V
Static Discharge Voltage (Digital)[9] ........................... >2000V Static Discharge Voltage (RF)[9] ................................. 1100V Latch-up Current......................................+200 mA, -200 mA Ground Voltage.................................................................. 0V FOSC (Crystal Frequency)........................... 12 MHz 30 ppm
Notes 8. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed. 9. Human Body Model (HBM).
Document #: 001-07552 Rev. *B
Page 74 of 85
[+] Feedback
CYRF69213
DC Characteristics (T = 25C)
Parameter VBAT VIO VCC VDD_MICRO1 VDD_MICRO2 VLVD Description Battery Voltage VIO Voltage VCC Voltage Operating Voltage Operating Voltage Low-voltage Detect Trip Voltage (8 programmable trip points) 0-70C No USB activity, CPU speed < 12 MHz USB activity, CPU speed < 12 MHz. Flash programming 0-70C Conditions Min. 1.8 1.8 2.4 4.0 4.35 2.68 Typ. Max. 3.6 3.6 3.6 5.25 5.25 4.87 Unit V V V V V V Radio Function Operating Voltages
MCU Function Operating Voltages
Device Current (For total current consumption in different modes, for example Radio, active, MCU, sleep, etc., add Radio Function Current and MCU Function Current) IDD (GFSK)[10] Average IDD, 1 Mbps, slow channel PA = 5, 2-way, 4 bytes/10 ms PA = 5, 2-way, 4 bytes/10 ms Radio function and MCU function in Sleep mode, VREG in Keep Alive. XOUT disabled PA = 5 (-5 dBm) PA = 6 (0 dBm) PA = 7 (+4 dBm) LNA off, ATT on LNA on, ATT off No GPIO loading, 6 MHz Internal and External Oscillators, Bandgap, Flash, CPU Clock, Timer Clock, USB Clock all disabled 15K 5% Ohm to VSS RUP is enabled 0.2 0.8 0.8 0V < VIN < 3.3V At IOH = -100.0 A At IOH = -2.0 mA -10 VIO - 0.1 VIO - 0.4 VIO VIO 2.5 2 20 10 2.8 10.87 11.2 40.1 mA mA A IDD (32-8DR)[10] Average IDD, 250 kbps, fast channel ISB Sleep Mode IDD
Radio Function Current (VDD_Micro = 5.0V, VREG enabled, MCU sleep) IDLE ICC Isynth TX ICC TX ICC TX ICC RX ICC RX ICC IDD_MICRO1 ISB1 Radio Off, XTAL Active ICC during Synth Start ICC during Transmit ICC during Transmit ICC during Transmit ICC during Receive ICC during Receive VDD_MICRO Operating Supply Current Standby Current 2.1 9.8 22.4 27.7 36.6 20.2 23.4 10 4 10 mA mA mA mA mA mA mA mA A
MCU Function Current (VDD_Micro = 5.0V, VREG disabled)
USB Interface VON VOFF VDI VCM VSE CIN IIO VOH1 VOH2 Static Output High Static Output Low Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage Output High Voltage Condition 1 Output High Voltage Condition 2 3.6 0.3 V V V V V pF A V V
Radio Function GPIO Interface
Notes 10. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK handshake. Device is in sleep except during this transaction.
Document #: 001-07552 Rev. *B
Page 75 of 85
[+] Feedback
CYRF69213
DC Characteristics (T = 25C) (continued)
Parameter VOL VIH VIL IIL CIN RUP VICR VICF VHC VILTTL VIHTTL VOL1 VOL2 VOL3 VOH 3.3V Regulator IVREG IKA VREG1 VREG2 VKA Max Regulator Output Current Keep Alive Current VREG Output Voltage VREG Output Voltage Keep Alive Voltage VCC > 4.35V When regulator is disabled with `keep alive' enable VCC > 4.35V, 0 < temp < 40C, 25 mA < IVREG < 125 mA VCC > 4.35V, 0 < temp < 40C, 1 mA < IVREG < 25 mA Keep Alive bit set in VREGCR 3.0 3.15 2.35 125 20 3.6 3.45 3.9 mA A V V V Description Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Pin Input Capacitance Pull-up Resistance Input Threshold Voltage Low, CMOS mode Input Threshold Voltage Low, CMOS mode Input Hysteresis Voltage, CMOS Mode Input Low Voltage, TTL Mode Input High Voltage, TTL Mode Output Low Voltage, High Drive[11] Output Low Voltage, High Output High Voltage[11] Drive[11] Output Low Voltage, Low Drive[11] Low to High edge High to Low edge High to Low edge I/O-pin Supply = 2.9-3.6V I/O-pin Supply = 4.0-5.5V IOL1 = 50 mA IOL1 = 25 mA IOL2 = 8 mA IOH = 2 mA VCC - 0.5 2.0 0.8 0.4 0.4 0 < VIN < VIO except XTAL, RFN, RFP, RFBIAS 4 40% 30% 3% Conditions At IOL = 2.0 mA 0.76VIO 0 -1 0.26 3.5 Min. Typ. 0 Max. 0.4 VIO 0.24VIO +1 10 12 65% 55% 10% 0.8 Unit V V V A pF K VCC VCC VCC V V V V V V
MCU Function GPIO Interface
RF Characteristics
Table 84.Radio Parameters Parameter Description Conditions Min. 2.400 -97 -93 -80 -87 -84 22.8 -31.7 LNA On LNA On -15 -6 21 1.9 Typ. Max. 2.497 Unit GHz dBm dBm dBm dBm dB dB dBm Count dB/Count RF Frequency Range Subject to regulations. Receiver (T = 25C, VCC = 3.0V, fOSC = 12.000 MHz, BER < 10-3) Sensitivity 125 kbps 64-8DR BER 1E-3 Sensitivity 250 kbps 32-8DR Sensitivity Sensitivity GFSK LNA gain ATT gain Maximum Received Signal RSSI value for PWRin -60 dBm RSSI slope
Note 11. Except for pins P1.0, P1.1 in GPIO mode.
BER 1E-3 CER 1E-3 BER 1E-3, ALL SLOW = 1
Document #: 001-07552 Rev. *B
Page 76 of 85
[+] Feedback
CYRF69213
Table 84.Radio Parameters (continued) Parameter Description Interference Performance (CER 1E-3) Co-channel Interference rejection Carrier-to-Interference (C/I) Adjacent (1 MHz) channel selectivity C/I 1 MHz Adjacent (2 MHz) channel selectivity C/I 2 MHz Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz Out-of-Band Blocking 30 MHz-12.75 MHz[12] Intermodulation Receive Spurious Emission 800 MHz 1.6 GHz 3.2 GHz Transmitter (T = 25C, VCC = 3.0V, fOSC = 12.000 MHz) Maximum RF Transmit Power Maximum RF Transmit Power Maximum RF Transmit Power Maximum RF Transmit Power RF Power Control Range RF Power Range Control Step Size Frequency Deviation Min Frequency Deviation Max Error Vector Magnitude (FSK error) Occupied Bandwidth Transmit Spurious Emission (PA = 7) In-band Spurious Second Channel Power (2 MHz) In-band Spurious Third Channel Power (>3 MHz) Non-Harmonically Related Spurs (8.000 GHz) Non-Harmonically Related Spurs (1.6 GHz) Non-Harmonically Related Spurs (3.2 GHz) Harmonic Spurs (Second Harmonic) Harmonic Spurs (Third Harmonic) Fourth and Greater Harmonics Power Management (Crystal PN# eCERA GF-1200008) Crystal start to 10 ppm Crystal start to IRQ Synth Settle Synth Settle Synth Settle Link turn-around time Link turn-around time Link turn-around time Link turn-around time XSIRQ EN = 1 Slow channels Medium channels Fast channels GFSK 250 kbps 125 kbps <125 kbps 0.7 0.6 270 180 100 30 62 94 31 1.3 ms ms s s s s s s s -38 -44 -38 -34 -47 -43 -48 -59 dBm dBm dBm dBm dBm dBm dBm dBm seven steps, monotonic PN Code Pattern 10101010 PN Code Pattern 11110000 >0 dBm -6 dBc, 100-kHz ResBW 500 PA = 7 PA = 6 PA = 5 PA = 0 +2 -2 -7 4 0 -5 -35 39 5.6 270 323 10 876 +6 +2 -3 dBm dBm dBm dBm dB dB kHz kHz %rms kHz 100-kHz ResBW 100-kHz ResBW 100-kHz ResBW -79 -71 -65 dBm dBm dBm C = -60 dBm, C = -60 dBm C = -60 dBm C = -67 dBm C = -67 dBm C = -64 dBm, f = 5,10 MHz 9 3 -30 -38 -30 -36 dB dB dB dB dBm dBm Conditions Min. Typ. Max. Unit
Document #: 001-07552 Rev. *B
Page 77 of 85
[+] Feedback
CYRF69213
Table 84.Radio Parameters (continued) Parameter Description Conditions Min. Typ. Max. Unit
Note 12. Exceptions F/3 & 5C/3. 13. When using an external switching regulator to power the radio, the switching frequency should be set very far from the IF frequency of 1 MHz.
Max. packet length Max. packet length
< 60 ppm Crystal to Crystal all modes except 64-DDR < 60 ppm Crystal to Crystal 64-DDR
40 16
bytes bytes
AC Test Loads and Waveforms for Digital Pins
Figure 20. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
OUTPUT 30 pF INCLUDING JIG AND SCOPE OUTPUT 5 pF
DC Test Load
VCC OUTPUT R2 R1
Max
INCLUDING JIG AND Typical SCOPE ALL INPUT PULSES VCC GND Rise time: 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH VTH OUTPUT
Parameter R1 R2 RTH VTH VCC
1071 937 500 1.4 3.00
Unit V V
90% 10%
90% 10% Fall time: 1 V/ns
AC Characteristics
Parameter 3.3V Regulator VORIP USB Driver TR1 TR2 TF1 TF2 TR VCRS TDRATE TDJR1 TDJR2 TDEOP TEOPR1 TEOPR2 TEOPT Transition Rise Time Transition Rise Time Transition Fall Time Transition Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Low-speed Data Rate Receiver Data Jitter Tolerance Receiver Data Jitter Tolerance Differential to EOP Transition Skew EOP Width at Receiver EOP Width at Receiver Source EOP Width Rejects as EOP Accept as EOP 675 1.25 1.5 Ave. Bit Rate (1.5 Mbps 1.5%) To next transition To pair transition CLOAD = 200 pF CLOAD = 600 pF CLOAD = 200 pF CLOAD = 600 pF 80 1.3 1.4775 -75 -45 -40 75 300 125 2.0 1.5225 75 45 100 330 75 300 ns ns ns ns % V Mbps ns ns ns ns ns s Output Ripple Voltage 45 55 % Description Conditions Min. Typical Max. Unit
USB Data Timing
Document #: 001-07552 Rev. *B
Page 78 of 85
[+] Feedback
CYRF69213
AC Characteristics (continued)
Parameter TUDJ1 TUDJ2 TLST TFPS2 SPI Timing TSMCK TSSCK TSCKH TSCKL TMDO TMDO1 TMSU TMHD TSSU TSHD TSDO TSDO1 TSSS TSSH SPI Master Clock Rate SPI Slave Clock Rate SPI Clock High Time SPI Clock Low Time Master Data Output Time[14] Master Data Output Time, First bit with CPHA = 0 Master Input Data Set-up time Master Input Data Hold time Slave Input Data Set-up Time Slave Input Data Hold Time Slave Data Output Time Slave Data Output Time, First bit with CPHA = 0 Slave Select Set-up Time Slave Select Hold Time SCK to data valid Time after SS LOW to data valid Before first SCK edge After last SCK edge Figure 21. Clock Timing TCYC TCH 150 150 High for CPOL = 0, Low for CPOL = 1 Low for CPOL = 0, High for CPOL = 1 SCK to data valid Time before leading SCK edge 125 125 -25 100 50 50 50 50 100 100 50 FCPUCLK/6 2 2.2 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns Description Differential Driver Jitter Differential Driver Jitter Width of SE0 during Diff. Transition SDATA/SCK Transition Fall Time 50 Conditions To next transition To pair transition Min. -95 -95 Typical Max. 95 95 210 300 Unit ns ns ns ns
Non-USB Mode Driver Characteristics
CLOCK
TCL
Figure 22. USB Data Signal Timing
Voh Vcrs Vol
D+
TR
90% 10% 90%
TF
10%
D-
Notes 14. In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
Document #: 001-07552 Rev. *B
Page 79 of 85
[+] Feedback
CYRF69213
Figure 23. Clock Timing TCYC TCH
CLOCK
TCL
Figure 24. USB Data Signal Timing
Voh Vcrs Vol
D+
TR
90% 10% 90%
TF
10%
D-
Figure 25. Receiver Jitter Tolerance
TPERIOD Differential Data Lines
TJR TJR1 TJR2
Consecutive Transitions N * TPERIOD + TJR1 Paired Transitions N * TPERIOD + TJR2
Document #: 001-07552 Rev. *B
Page 80 of 85
[+] Feedback
CYRF69213
Figure 26. Differential to EOP Transition Skew and EOP Width
TPERIOD Differential Data Lines
Crossover Point
Crossover Point Extended
Diff. Data to SE0 Skew N * TPERIOD + TDEOP
Source EOP Width: TEOPT Receiver EOP Width: TEOPR1, TEOPR2
Figure 27. Differential Data Jitter
TPERIOD Differential Data Lines
Crossover Points
Consecutive Transitions N * TPERIOD + TxJR1 Paired Transitions N * TPERIOD + TxJR2
Document #: 001-07552 Rev. *B
Page 81 of 85
[+] Feedback
CYRF69213
Figure 28. SPI Master Timing, CPHA = 1
SS
(SS is under firmware control in SPI Master mode)
TSCKL
SCK (CPOL=0)
TSCKH
SCK (CPOL=1)
TMDO
MOSI
MSB
LSB
MISO
MSB
LSB
TMSU TMHD
Figure 29. SPI Slave Timing, CPHA = 1
SS
TSSS TSCKL TSSH TSCKH
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
TSDO
MSB
LSB
TSSU TSHD
MSB LSB
MISO
Document #: 001-07552 Rev. *B
Page 82 of 85
[+] Feedback
CYRF69213
Figure 30. SPI Master Timing, CPHA = 0
SS
(SS is under firmware control in SPI Master mode)
TSCKL
SCK (CPOL=0)
TSCKH
SCK (CPOL=1)
TMDO1 TMDO
MSB LSB
MOSI
MISO
MSB
LSB
TMSU TMHD Figure 31. SPI Slave Timing, CPHA = 0
SS
TSSS TSCKL TSSH TSCKH
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MSB
LSB
TSSU TSHD TSDO1 TSDO
MSB LSB
MISO
Document #: 001-07552 Rev. *B
Page 83 of 85
[+] Feedback
CYRF69213
Table 85.Ordering Information Package 40-pin Lead-Free QFN 6x6 mm CYRF69213-40 LFXC Ordering Part Number
Package Diagram
Figure 32. 40-pin Lead-Free QFN 6x6 mm
SIDE VIEW BOTTOM VIEW
C 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF.
TOP VIEW
0.08[0.003] A 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] N 1 0.60[0.024] DIA. 2 1.00[0.039] MAX.
18.5 0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018]
5.70[0.224] 5.80[0.228]
5.90[0.232] 6.10[0.240]
18.5
0-12
0.30[0.012] 0.50[0.020] C SEATING PLANE 4.45[0.175] 4.55[0.179]
0.50[0.020]
0.24[0.009] 0.60[0.024]
(4X)
NOTES: 1. HATCH IS SOLDERABLE EXPOSED AREA
51-85190-*A
2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.086g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
WirelessUSB, PSoC, enCoRe and PRoC are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-07552 Rev. *B
Page 84 of 85
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
4.45[0.175] 4.55[0.179]
SOLDERABLE EXPOSED PAD
[+] Feedback
CYRF69213
Document History Page
Document Title: CYRF69213 Programmable Radio on Chip Low Power Document #: 001-07552 REV. ** *A *B ECN No. Issue Date Orig. of Change OYR OYR BOO New advance data sheet. Preliminary data sheet. Final datasheet. Updated DC Characteristics table with characterization data. Minor text changes Removed all residual references to external crystal oscillator and GPIO4 Voltage regulator line/load regulation documented GPIO capacitance and timing diagram included Sleep and Wake up sequence documented. EP1MODE/EP2MODE register issue discussed Updated radio function register descriptions Changed L/D pin description Changed RST Capacitor from 0.1uF to 0.47uF Description of Change
436355 See ECN 501280 See ECN 631538 See ECN
Document #: 001-07552 Rev. *B
Page 85 of 85
[+] Feedback

▲Up To Search▲

Price & Availability of CYRF69213

	To Download CYRF69213 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .