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EVB7122
27 to 930MHz Transceiver Evaluation Board Description Features
! Single chip solution with only a few external components ! Stand-alone fixed-frequency user mode ! Programmable multi-channel user mode ! Low current consumption in active mode and very low standby current ! PLL-stabilized RF VCO (LO) with internal varactor diode ! Lock detect output in programmable user mode ! On-chip AFC for extended input frequency acceptance range ! FSK for digital data or FM for analog signal reception ! FSK/ASK mode selection ! RSSI output for signal strength indication and ASK reception ! ASK detection normal or with peak detector ! Switchable LNA gain for improved dynamic range ! Automatic PA turn-on after PLL lock ! ASK modulation achieved by PA on/off keying ! 3wire bus serial control interface ! EVB comes with a cable to connect to a PC's LPT port ! EVB programming software is available on Melexis web site
Ordering Information
Part No. (see paragraph 6) EVB7122-315-FSK-C EVB7122-433-FSK-C EVB7122-868-FSK-C EVB7122-915-FSK-C
Note 1: EVB default population is FSK, ASK modifications according to section 4.2 and 4.3. Note 2: EVB7122 is applicable for devices TH7122 and TH71221.
Application Examples
! General bi-directional half duplex digital data RF signaling or analog signal communication ! Tire Pressure Monitoring Systems (TPMS) ! Remote Keyless Entry (RKE) ! Low-power telemetry systems ! Alarm and security systems ! Wireless access control ! Garage door openers ! Networking solutions ! Active RFID tags ! Remote controls ! Home and building automation
Evaluation Board Example
General Description
The TH7122 is a single chip FSK/FM/ASK transceiver IC. It is designed to operate in low-power multichannel programmable or single-channel stand-alone, half-duplex data transmission systems. It can be used for applications in automotive, industrial-scientific-medical (ISM), short range devices (SRD) or similar applications operating in the frequency range of 300 MHz to 930 MHz. In programmable user mode, the transceiver can operate down to 27 MHz by employing an external VCO varactor diode.
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description Document Content
1 Theory of Operation ...................................................................................................3
1.1 1.2 1.3 1.4 1.5 General............................................................................................................................. 3 Technical Data Overview.................................................................................................. 3 Note on ASK Operation .................................................................................................... 3 Block Diagram .................................................................................................................. 4 User Mode Features ......................................................................................................... 4
2
Description of User Modes........................................................................................5
2.1
2.1.1 2.1.2 2.1.3 2.1.4
Stand-alone User Mode Operation ................................................................................... 5
Frequency Selection .................................................................................................................... 5 Operation Mode ........................................................................................................................... 5 Modulation Type .......................................................................................................................... 6 LNA Gain Mode ........................................................................................................................... 6
2.2
2.2.1
Programmable User Mode Operation............................................................................... 6
Serial Control Interface Description ............................................................................................. 6
3
Register Description ..................................................................................................7
3.1
3.1.1 3.1.2 3.1.3 3.1.4 3.1.5
Register Overview ............................................................................................................ 8
Default Register Settings for FS0, FS1........................................................................................ 8 A - word ....................................................................................................................................... 9 B - word ..................................................................................................................................... 10 C - word..................................................................................................................................... 11 D - word..................................................................................................................................... 12
4
Application Circuits .................................................................................................13
4.1
4.1.1 4.1.2
FSK Application Circuit Programmable User Mode (internal AFC option)...................... 13
Board Component Values for FSK Reception ........................................................................... 14 Component Arrangement Top Side for FSK Reception ............................................................ 15
4.2
4.2.1 4.2.2
ASK Application Circuit Programmable User Mode (normal data slicer option) ............. 16
Board Component Values for ASK (normal data slicer option) ................................................. 17 Component Arrangement Top Side for ASK Reception (normal data slicer option) ................. 18
4.3
4.3.1 4.3.2
ASK Application Circuit with Peak Detector Option ........................................................ 19
Board Component Values for ASK (peak detector option)........................................................ 20 Component Arrangement Top Side for ASK Reception (peak detector option)........................ 21
5 6 7
Evaluation Board Layouts .......................................................................................22 Board Variants..........................................................................................................22 Package Description ................................................................................................23
7.1 Soldering Information ..................................................................................................... 23
8
Disclaimer .................................................................................................................24
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description 1
1.1
Theory of Operation
General
The main building block of the transceiver is a programmable PLL frequency synthesizer that is based on an integer-N topology. The PLL is used for generating the carrier frequency during transmission and for generating the LO signal during reception. The carrier frequency can be FSK-modulated by pulling the crystal and ASK-modulated by on/off keying of the power amplifier. The receiver is based on the principle of a single conversion superhet. Therefore the VCO frequency has to be changed between transmit and receive mode. In receive mode, the preferred LO injection type is low-side injection. The TH7122 transceiver IC consists of the following building blocks: " " " " " " " Low-noise amplifier (LNA) for high-sensitivity RF signal reception with switchable gain Mixer (MIX) for RF-to-IF down-conversion IF amplifier (IFA) to amplify and limit the IF signal and for RSSI generation Phase-coincidence demodulator with external ceramic discriminator (FSK Demodulator) Operational amplifier (OA1), connected to demodulator output Operational amplifier (OA2), for geral use Peak detector (PKDET) for ASK detection " " " " " " " " Control logic with 3wire bus serial control interface (SCI) Reference oscillator (RO) with external crystal Reference divider (R counter) Programmable divider (N/A counter) Phase-frequency detector (PFD) Charge pump (CP) Voltage controlled oscillator (VCO) with internal varactor Power amplifier (PA) with adjustable output power
1.2
Technical Data Overview
! Sensitivity: -107 dBm at ASK with 180 kHz IF filter BW ! Max. data rate with crystal pulling: 20 kbps NRZ ! Max. data rate with direct VCO modulation: 115 kbps NRZ ! Max. input level: -10 dBm at FSK and -20 dBm at ASK ! Input frequency acceptance: 10 to 150 kHz (depending on FSK deviation) ! FM/FSK deviation range: 2.5 to 80 kHz ! Analog modulation frequency: max. 10 kHz ! Crystal reference frequency: 3 MHz to 12 MHz ! External reference frequency: 1 MHz to 16 MHz
! Frequency range: 300 MHz to 930 MHz in programmable user mode ! Extended frequency range with external VCO varactor diode: 27 MHz to 930 MHz ! 315 MHz, 433 MHz, 868 MHz or 915 MHz fixedfrequency settings in stand-alone mode ! Power supply range: 2.2 V to 5.5 V ! Temperature range: -40 C to +85 C ! Standby current: 50 nA ! Operating current in receive: 6.5 mA (low gain) ! Operating current in transmit: 12 mA (at -2 dBm) ! Adjustable RF power range: -20 dBm to +10dBm ! Sensitivity: -105 dBm at FSK with 180 kHz IF filter BW
1.3
Note on ASK Operation
Optimum ASK performance can be achieved by using an 8-MHz crystal for operation at 315 MHz, 434 MHz and 915 MHz. For details please refer to the software settings shown in sections 4.2 and 4.3. FSK operation is the preferred choice for applications in the European 868MHz band.
For more detailed information, please refer to the latest TH7122 data sheet revision
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
1.4 Block Diagram
GAIN_LNA
OUT_LNA
VEE_LNA
IN_MIX
VEE_IF
OUT_MIX
VCC_IF
IN_IFA
RSSI
27
29
28
30
32
31
1
2
7
3 IN_DEM
6 OUT_DEM
PKDET
SW1 1.5pF
bias
OA2
4
FSK Demodulator
MIX
SW2 200k
INT2/PDO
5
IN_LNA
26
MIX LNA
LO IF
INT1
IFA
OA1
8
OUT_DTA
Control Logic
ASK
SCI
SDEN SDTA SCLK
N counter VCO
R counter RO RO
FSK_SW FSK FS0/SDEN
OUT_PA
25
PA
ASK/FSK RE/SCLK VEE_RO
24 PS_PA 21 TNK_LO 20 VCC_PLL 23 LF 22 VEE_PLL 10 RO
FS1/LD
11
19
9
12
13
15
16
17
18
14
Fig. 1:
TH7122 block diagram
1.5
User Mode Features
The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to Standalone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC in order to set the desired frequency of operation. There are 4 pre-defined frequency settings: 315MHz, 433.92MHz, 868.3MHz and 915MHz. The logic level at pin FS0/SDEN must not be changed after power up in order to remain in fixed-frequency mode. After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode (PUM). In this mode, the user can set any PLL frequency or mode of operation by the SCI. In SUM pins FS0/SDEN and FS1/LD are used to set the desired frequency, while in PUM pin FS0/SDEN is part of the 3-wire serial control interface (SCI) and pin FS1/LD is the look detector output signal of the PLL synthesizer. A mode control logic allows several operating modes. In addition to standby, transmit and receive mode, two idle modes can be selected to run either the reference oscillator only or the whole PLL synthesizer. The PLL settings for the PLL idle mode are taken over from the last operating mode which can be either receive or transmit mode. The different operating modes can be set in SUM and PUM as well. In SUM the user can program the transceiver via control pins RE/SCLK and TE/SDTA. In PUM the register bits OPMODE are used to select the modes of operation while pins RE/SCLK and TE/SDTA are part of the SCI.
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EVB Description June/07
VCC_DIG
VEE_DIG
TE/SDTA
IN_DTA
EVB7122
27 to 930MHz Transceiver Evaluation Board Description 2
2.1
Description of User Modes
Stand-alone User Mode Operation
After power up the transceiver is set to stand-alone user mode. In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC to set the desired frequency of operation. The logic level at pin FS0/SDEN must not be changed after power up in order to remain in stand-alone user mode. The default settings of the control word bits in stand-alone user mode are described in the frequency selection table. Detailed information about the default settings can be found in the tables of section 5.
2.1.1
Frequency Selection
Channel frequency 433.92 MHz 1 0 868.3 MHz 0 0 7.1505 MHz 32 223.45 kHz 1894 423.22 MHz 433.92 MHz 32 223.45 kHz 1942 433.92 MHz 433.92 MHz 10.7 MHz 16 446.91 kHz 1919 857.60 MHz 868.30 MHz 16 446.91 kHz 1943 868.30 MHz 868.30 MHz 10.7 MHz 18 397.25 kHz 766 304.30 MHz 315.00 MHz 18 397.25 kHz 793 315.00 MHz 315.00 MHz 10.7 MHz 32 223.45 kHz 4047 904.30 MHz 915.00 MHz 32 223.45 kHz 4095 915.00 MHz 915.00 MHz 10.7 MHz 315 MHz 1 1 915 MHz 0 1
FS0/SDEN FS1/LD Reference oscillator frequency R counter ratio in RX mode (RR) PFD frequency in RX mode N counter ratio in RX mode (NR) VCO frequency in RX mode RX frequency R counter ratio in TX mode (RT) PFD frequency in TX mode N counter ratio in TX mode (NT) VCO frequency in TX mode TX frequency IF in RX mode
In stand-alone user mode, the transceiver can be set to Standby, Receive, Transmit or Idle mode (only PLL synthesizer active) via control pins RE/SCLK and TE/SDTA. The modulation scheme and the LNA gain are set by pins ASK/FSK and GAIN_LNA, respectively.
2.1.2
Operation Mode
Operation mode RE/SCLK TE/SDTA Standby 0 0 Receive 1 0 Transmit 0 1 Idle 1 1
Note: Pins with internal pull-down
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
2.1.3 Modulation Type
Modulation type ASK / FSK ASK 0 FSK 1
2.1.4
LNA Gain Mode
LNA gain GAIN_LNA high 0 low 1
2.2
Programmable User Mode Operation
The transceiver can also be used in programmable user mode. After power-up the first logic change at pin FS0/SDEN enters into this mode. Now full programmability can be achieved via the Serial Control Interface (SCI).
2.2.1
Serial Control Interface Description
A 3-wire (SCLK, SDTA, SDEN) Serial Control Interface (SCI) is used to program the transceiver in programmable user mode. At each rising edge of the SCLK signal, the logic value on the SDTA pin is written into a 24-bit shift register. The data stored in the shift register are loaded into one of the 4 appropriate latches on the rising edge of SDEN. The control words are 24 bits lengths: 2 address bits and 22 data bits. The first two bits (bit 23 and 22) are latch address bits. As additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. The first incoming bit is the most significant bit (MSB). To program the transceiver in multi-channel application, four 24-bit words may be sent: A-word, B-word, C-word and D-word. If individual bits within a word have to be changed, then it is sufficient to program only the appropriate 24-bit word. The serial data input timing and the structure of the control words are illustrated in Fig. 2 and 3.
22 22
SDTA SCLK
24-BIT SHIFT REGISTER
2
A - LATCH B - LATCH C - LATCH D - LATCH
22
A-word
22
22
B-word
22
`00'
22
C-word
SDEN
ADDR DECODER
`01' `10' `11'
22
22
D-word
Fig. 2:
SCI Block Diagram
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
Due to the static CMOS design, the SCI consumes virtually no current and it can be programmed in active as well as in standby mode. If the transceiver is set from standby mode to any of the active modes (idle, receive, transmit), the SCI settings remain the same as previously set in one of the active modes, unless new settings are done on the SCI while entering into an active mode.
Invalid data SDTA Invalid data
MSB bit 23 bit 22 bit 1
LSB bit 0
SCLK t CS t CH t CWL tCWH
SDEN
tES
tEW
tEH
Fig. 3:
Serial Data Input Timing
3
Register Description
As shown in the previous section there are four control words which stipulate the operation of the whole chip. In Stand-alone User Mode SUM the intrinsic default values with respect to the applied levels at pins FS0 and FS1 lay down the configuration of the transceiver. In Programmable User Mode (PUM) the register settings can be changed via 3-wire interface SCI. The default settings which vary with the desired operating frequency depend on the voltage levels at the frequency selection pins FS0 and FS1 before entering the PUM. Table 5.1.1 shows the default register settings of different frequency selections. It should be noted that the channel frequency listed below will be achieved with a crystal frequency of 7.1505 MHz. The following table depicts an overview of the register configuration of the TH7122.
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
3.1 Register Overview
DATA
LSB 9 8 7 6 5 4 3 2 1 0 Bit No. default
WORD MSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 DATAPOL 0 MODSEL 0 CPCUR 0 LOCKMODE 1 PACTRL 1 1 1 Set to 1 1 LNAGAIN 0 0
Depends on FS0/FS1 voltage level after power up
TXPOWER [ 1 :0 ]
OPMODE [1:0]
A
23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 1 0 PKDET 1 Set to 1 1 DELPLL 1 LNAHYST 0 0 1 1 ROMAX [2:0] 1 0 1 ROMIN [2:0] 0
9
8
7
6
5
RR [9:0] 4 3
IDLE
2
1
0
Bit No. default
Depends on FS0/FS1 voltage level after power up
B
23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 0 0 LNACTRL 0 VCOCUR [ 1 :0 ] PFDPOL BAND
9
8
7
6
5
RT [9:0] 4 3
OA2
AFC
2
1
0
Bit No. default
Depends on FS0/FS1 voltage level after power up
C
23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 1 0 MODCTRL 0 1 0 0
9
NR [ 16 : 0 ] 8 7
6
5
4
3
2
1
0
Bit No. default
Depends on FS0/FS1 voltage level after power up
D
3.1.1
FS1 0 0 1 1 Note:
Default Register Settings for FS0, FS1
FS0 0 1 0 1 Channel frequency 868.30 MHz 433.92 MHz 915.00 MHz 315.00 MHz BAND 1 0 1 0 VCOCUR [1:0] 11 01 11 00 RR [9:0] 16d 32d 32d 18d NR [ 16 :0 ] 1919d 1894d 4047d 766d RT [ 9 :0 ] 16d 32d 32d 18d NT [ 16 : 0 ] 1943d 1942d 4095d 793d
d - decimal code
A detailed description of the registers function and their configuration can be found in the following sections.
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NT [ 16 : 0 ]
LDTM [ 1 :0 ]
ERTM [ 1 :0 ]
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
3.1.2 A - word
Name Bits [9:0] 4d .. 1023d Operation mode 00 01 10 11 0 1 Standby mode Receive mode Transmit mode Idle mode LNA gain low LNA gain high LNA gain set to `1' for correct function Output power steps 00 01 10 11 0 1 0 P1 P2 P3 P4 Set the PA-on condition PA is switched on if the PLL locks PA is always on in TX mode Set the PLL locked state observation mode before lock only #default Description Reference divider ratio in RX operation mode
RR
OPMODE
[11:10]
LNAGAIN not used
[12]
#default
This selection is valid if bit LNACTR (bit 21 in C-word) is set to internal LNA gain control.
[13]
TXPOWER
[15:14]
#default
PACTRL
[16]
#default #default
LOCKMODE
[17] 1
Locked state condition will be ascertained only one time afterwards the LD signal remains in high state.
before and after lock
locked state will be observed permanently
Charge Pump output current
CPCUR
[18]
0 1 0 1
260 A 1300 A Modulation mode ASK FSK Input data polarity
#default
MODSEL
[19]
#default
This selection is valid if bit MODCTRL (bit 21 in D-word) is set to internal modulation control.
0
normal
`0' for space at ASK or fmin at FSK, `1' for mark at ASK or fmax at FSK
#default
DTAPOL
[20] 1
inverse
`1' for space at ASK or fmin at FSK, `0' for mark at ASK or fmax at FSK
Active blocks in IDLE mode
IDLESEL
[21]
0 1
only RO active whole PLL active
#default
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
3.1.3 B - word
Name Bits [9:0] 4d .. 1023d Set the desired steady state current of the reference oscillator 000 001 010 011 100 101 110 111 0 A 75 A 150 A #default 225 A 300 A 375 A 450 A 525 A 0 A 75 A 150 A 225 A 300 A 375 A 450 A 525 A #default disabled enabled
OA2 can be enabled in FSK receive mode. OA2 is disabled in ASK mode receive. The control circuitry regulates the current of the oscillator core between the values ROMAX and ROMIN. As the regulation input signal the amplitude on pin RO is used. If the ROMIN value is sufficient to achieve an amplitude of about 400mV on pin RO the current of the reference oscillator core will be set to ROMIN. Otherwise the current will be permanently regulated between ROMAX and ROMIN. If ROMIN and ROMAX are equal no regulation of the oscillator current occurs. Please also note the block description of the reference oscillator in para. 3.1.1
Description Reference divider ratio in TX operation mode
RT
ROMIN
[12:10]
Set the start-up current of the reference oscillator 000 001 010 011 100 101 110 111
ROMAX
[15:13]
Set the start-up current of the reference oscillator core. Please also note the description of the ROMIN register and the block description of the reference oscillator which can be seen above.
OA2 operation
OA2
[16]
0 1
#default
Internal AFC feature
AFC
[17]
0 1
disabled enabled Hysteresis on pin GAIN_LNA
#default
LNAHYST
[18]
0 1 0
disabled enabled - typical 340 mV (V01 = 1.56V, V10 = 1.22V) Delayed start of the PLL undelayed start
PLL starts at the reference oscillator start-up
#default
DELPLL
[19]
1
starts after 8 valid RO-cycles
#default
PLL starts after 8 valid RO-cycles before entering an active mode to ensure reliable oscillation of the reference oscillator.
not used
[20] 0 disabled
set to `1' for correct function RSSI Peak Detector #default
PKDET
[21] 1
The RSSI output signal directly feeds the data slicer setup by means of OA1.
enabled
In ASK receive mode the RSSI Peak Detector output is multiplexed to pin INT2/PDO.
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
3.1.4 C - word
Name Bits [16:0] 64d .. 131071d 0 1 Set the desired frequency range recommended at fRF < 500 MHz recommended at fRF > 500MHz
Some tail current sources are linked to this bit in order to save current for low frequency operations.
Description Feedback divider ratio in RX operation mode
NR
BAND
[17]
VCO active current
VCOCUR
[19:18]
00 01 10 11
low current (300 A) standard current (500 A) high1 current (700 A) high2 current (900 A) Phase Detector polarity
0
PFDPOL
[20] 1
negative #default
VCO OUTPUT FREQUENCY
pos neg VCO INPUT VOLTAGE
positive
0
LNA gain control mode external LNA gain control
LNA gain will be set via pin GAIN_LNA.
#default
LNACTRL
[21] 1
internal LNA gain control
LNA gain will be set via bit LNAGAIN (bit 12 in A-word). Nevertheless pin GAIN_LNA must be connected to either VCC or VEE.
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
3.1.5 D - word
Name Bits [16:0] 64d .. 131071d Set the unlock condition of the PLL 00 01 10 11 00 01 10 11 0 2 clocks #default 4 clocks 8 clocks 16 clocks 4 clocks 16 clocks #default 64 clocks 256 clocks Description Feedback divider ratio in TX operation mode
NT
ERTM
[18:17]
Set the maximum allowed number of reference clocks (1/fRO) during the phase detector output signals (UP & DOWN) can be in-consecutive.
Set the lock condition of the PLL
LDTM
[20:19]
Set the minimum number of consecutive edges of phase detector output cycles, without appearance of any unlock condition.
Set mode of modulation control: external modulation control
Modulation will be set via pin ASK/FSK.
#default
MODCTRL
[21] 1
internal modulation control
Modulation will be set via bit MODSEL (bit 19 in A-word). Nevertheless pin ASK/FSK must be connected to either VCC or VEE.
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EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description 4
4.1
Application Circuits
FSK Application Circuit Programmable User Mode (internal AFC option)
21
4321 RS2 RS3 RE/SCLK ASK/FSK
4321
CB0
RS1 TE/SDTA
FS0/SDEN
FS1/LD
12 3
12 3
12 3
12 3
12 3
CX2
CB7
16 RE/SCLK 15 VCC_DIG 14 ASK/FSK 13 IN_DTA 12
FSK_SW 11
RO 10
FS0/SDEN 17
OUT_DTA 8 RSSI 7 OUT_DEM 6
VEE_RO
9
RSSI GND OUT_DEM GND 4321 CX1 XTAL
VCC GND
IN_DTA GND OUT_DTA GND
GND SDTA SDEN SCLK
CB6 C0 L0 CF1 CF2 RPS RF
18 VEE_DIG 19 FS1/LD 20 VCC_PLL 21 TNK_LO 22 VEE_PLL 23 LF 29 GAIN_LNA 27 VEE_LNA 25 OUT_PA 26 IN_LNA 30 IN_MIX 31 VEE_IF 24 28 OUT_LNA
C5 C3 C4 RP CB5 CERDIS RL0
TH7122
INT1 5 INT2/PDO 4 IN_DEM 3 VCC_IF 2 32 OUT_MIX IN_IFA 1
CTX4 CB2 LTX0 CTX1 CTX2
CTX0 LRX2 LTX1
CRX0
C2 C1 L1 CB1
CERFIL RB1
CB4
VCC
50
TX_OUT RX_IN
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VCC
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
4.1.1 Board Component Values for FSK Reception
Value @ 315 MHz
0.47 pF 3.9 pF 1.5 pF 10 nF 330 pF 1.5 nF 10 F 10 nF 330 pF 10 nF 100 nF 100 pF 100 nF 1 nF 100 pF 8.2 pF 150 pF 100 pF 10 pF 10 pF 10 pF 12 pF 100 33 k 3.3 K 390 18 k 10 k 56 nH
Part
C0 C1 C2 C3 C4 C5 CB0 CB1 CB2 CB4 CB5 CB6 CB7 CF1 CF2 CX1 CX2 CRX0 CTX0 CTX1 CTX2 CTX4 RB1 RF RP RL0 RPS RS1...RS3 L0
Size
0603 0603 0603 0603 0603 0603 1210 0603 0603 0603 0603 0603 0603 0603 0603 0805 0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
Value @ 433.92 MHz
NIP 4.7 pF 1.5 pF 10 nF 330 pF 1.5 nF 10 F 10 nF 330 pF 10 nF 100 nF 100 pF 100 nF 1 nF 68 pF 10 pF 56 pF 100 pF 10 pF 6.8 pF 6.8 pF 4.7 pF 100 33 k 3.3 K 390 33 k 10 k 33 nH
Value @ 868.3 MHz
1.8 pF 1.8 pF 1.5 pF 10 nF 330 pF 1.5 nF 10 F 10 nF 330 pF 10 nF 100 nF 100 pF 100 nF 1 nF 150 pF 12 pF 18 pF 100 pF 10 pF 5.6 pF 3.9 pF 2.2 pF 100 33 k 3.3 K 390 43 k 10 k 4.7 nH
Value @ 915 MHz
1.5 pF 1 pF 1.5 pF 10 nF 330 pF 1.5 nF 10 F 10 nF 330 pF 10 nF 100 nF 100 pF 100 nF 1 nF 82 pF 12 pF 15 pF 100 pF 10 pF 4.7 pF 3.9 pF 1.8 pF 100 33 k 3.3 K 390 43 k 10 k 3.9 nH
Tol.
5% 5% 5% 5%
Description
VCO tank capacitor LNA output tank capacitor MIX input matching capacitor demodulator output low-pass capacitor, depending on data rate
10% data slicer capacitor
10% RSSI output low pass capacitor 20% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% de-coupling capacitor 10% loop filter capacitor 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% loop filter capacitor RO capacitor for FSK (f = 20 kHz) RO capacitor for FSK (f = 20 kHz) RX coupling capacitor TX coupling capacitor TX impedance matching capacitor TX impedance matching capacitor TX impedance matching capacitor protection resistor loop filter resistor CERDIS loading resistor CERFIL loading, optionally power-select resistor protection resistor VCO tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part LNA output tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part impedance matching inductor from Wurth-Elektronik (WE-KI series) or equivalent part fundamental-mode crystal from: Telcona/Hong Kong X'tals C5L7150500D10F3EHK02 ceramic filter from Murata, or equivalent part ceramic Discriminator from Murata, or equivalent part
L1 LRX2 LTX0 LTX1 XTAL CERFIL CERDIS
0603 0603 0603 0603 HC49 SMD 7x5 SMD 3.45x3.1 SMD 4.5x2
33 nH 82 nH 15 nH 33 nH
15 nH 56 nH 15 nH 33 nH
4.7 nH 15 nH 3.9 nH 10 nH
4.7 nH 15 nH 3.9 nH 10 nH
5% 5% 5% 5%
7.1505 MHz 20ppm cal., 20ppm temp. SFECF10M7HA00 B3dB = 180 kHz CDSCB10M7GA136
Note:
- NIP - not in place, may be used optionally
39012 07122 02 Rev. 005
Page 14 of 24
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
4.1.2 Component Arrangement Top Side for FSK Reception
OUT DEM
1
C4
C3 RP CB4
IN DTA
SDTA
GND
OUT DTA
GND
SDEN
SCLK
RSSI
GND
VCC
GND
GND
1
1
1
CB0
RS1 RS3 RS2
ASK/FSK
C5
GND LD VCC
3
1
1
1
1
1
XTAL
FS1
FS0
RE
TE
CB7
CB6 CF1 CF2
L0
CX1
CX2
1
CERDIS
CB5
RF RPS
C2 CTX0 CRX0 CTX4 CB2 LTX0 C1 L1 CB1 RB1
CTX1
EVB7122_003
LTX1
LRX2
RL0
CTX2
TX_output
39012 07122 02 Rev. 005
Page 15 of 24
RX_input
Melexis
EVB Description June/07
GND
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
4.2 ASK Application Circuit Programmable User Mode (normal data slicer option)
21
4321 RS2 RS3 RE/SCLK ASK/FSK
4321
CB0
RS1 TE/SDTA
FS0/SDEN
FS1/LD
12 3
12 3
12 3
12 3
12 3
CB7
RE/SCLK 15 VCC_DIG 14 ASK/FSK 13 FSK_SW 11 IN_DTA 12 RO 10 VEE_RO 16 9
FS0/SDEN 17
RSSI GND OUT_DEM GND 4321 CX1 XTAL
OUT_DTA 8 RSSI 7 OUT_DEM 6
VCC GND
IN_DTA GND OUT_DTA GND
GND SDTA SDEN SCLK
CB6 C0 L0 CF1 CF2 RF RPS CPS
18 VEE_DIG 19 FS1/LD 20 VCC_PLL 21 TNK_LO 22 VEE_PLL 23 LF 29 GAIN_LNA 27 VEE_LNA 25 OUT_PA 26 IN_LNA 30 IN_MIX 31 VEE_IF 24 28 OUT_LNA
C5 C3
TH7122
INT1 5 INT2/PDO 4 IN_DEM 3 VCC_IF 2 32 OUT_MIX IN_IFA 1
CB5
CTX4 LTX0 CTX1 CTX2
RL0 CERFIL
CB2
CTX0 LRX2 LTX1
CRX0
C2 C1 L1 CB1
VCC
50
TX_OUT RX_IN
Software Settings for ASK
Channel frequency 315.00 MHz 434.00 MHz 915.00 MHz fRO = 8.0000MHz RR 80 80 80 NR 3043 4233 9043 RT 8 8 8 NT 315 434 915 CPCUR RX 260A 260A 260A TX 1300A 1300A 1300A VCOCUR RX 300A 300A 300A TX 900A 900A 900A
39012 07122 02 Rev. 005
Page 16 of 24
VCC
RB1
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
4.2.1
Part
C0 C1 C2 C3 C5 CB0 CB1 CB2 CB5 CB6 CB7 CF1 CF2 CPS CX1 CRX0 CTX0 CTX1 CTX2 CTX4 RB1 RF RP RL0 RPS RS1...RS3 L0
Board Component Values for ASK (normal data slicer option)
Size
0603 0603 0603 0603 0603 1210 0603 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
Value @ 315 MHz
1.8 pF 3.9 pF 1.5 pF 10 nF 1.5 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 100 pF 10 pF 10 pF 10 pF 12 pF 100 33 k 3.3 K 390 18 k 10 k 47 nH
Value @ 434 MHz
2.2 pF 4.7 pF 1.0 pF 10 nF 1.5 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 100 pF 10 pF 6.8 pF 6.8 pF 4.7 pF 100 33 k 3.3 K 390 33 k 10 k 27 nH
Value @ 915 MHz
1.8 pF 1 pF 1.5 pF 10 nF 1.5 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 10 pF 10 pF 4.7 pF 3.9 pF 1.8 pF 100 33 k 3.3 K 390 43 k 10 k 3.9 nH
Tol.
5% 5% 5% 10% 10% 20% 10% 10% 10% 10% 10% 10% 5% 10% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
Description
VCO tank capacitor LNA output tank capacitor MIX input matching capacitor data slicer capacitor RSSI output low pass capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor loop filter capacitor loop filter capacitor power-select capacitor RO capacitor RX coupling capacitor TX coupling capacitor TX impedance matching capacitor TX impedance matching capacitor TX impedance matching capacitor protection resistor loop filter resistor CERDIS loading resistor CERFIL loading, optionally power-select resistor protection resistor VCO tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part LNA output tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part impedance matching inductor from Wurth-Elektronik (WE-KI series) or equivalent part fundamental-mode crystal from: Telcona/Hong Kong X'tals C5L8000000D10F3EHK01 ceramic filter from Murata, or equivalent part
L1 LRX2 LTX0 LTX1 XTAL CERFIL
0603 0603 0603 0603 HC49 SMD 7x5 SMD 3.45x3.1
33 nH 82 nH 15 nH 33 nH
15 nH 56 nH 15 nH 33 nH
4.7 nH 15 nH 3.9 nH 10 nH
5% 5% 5% 5%
8.0000 MHz 20ppm cal., 20ppm temp. SFECF10M7HA00 B3dB = 180 kHz
39012 07122 02 Rev. 005
Page 17 of 24
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
4.2.2 Component Arrangement Top Side for ASK Reception (normal data slicer option)
OUT DEM
1
C3
IN DTA
SDTA
GND
OUT DTA
GND
SDEN
SCLK
RSSI
GND
VCC
GND
GND
1
1
1
CB0
RS1 RS3 RS2
ASK/FSK
C5
GND LD VCC
3
1
1
1
1
1
XTAL
FS1
FS0
RE
TE
CB7
CB6 CF1 CF2
C0
RF RPS CPS C2 CTX0 CRX0 CTX4 CB2 LTX0 C1 L1 CB1 RB1
L0
CX1
CB5 RL0
CTX1
EVB7122_003
LTX1
LRX2
1
CTX2
TX_output
39012 07122 02 Rev. 005
Page 18 of 24
RX_input
Board size is 39.5mm x 56.5mm
Melexis
EVB Description June/07
GND
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
4.3 ASK Application Circuit with Peak Detector Option
21
4321 RS2 RS3 RE/SCLK ASK/FSK
4321
CB0
RS1 TE/SDTA
FS0/SDEN
FS1/LD
12 3
12 3
12 3
12 3
12 3
CB7
RE/SCLK 15 VCC_DIG 14 ASK/FSK 13 FSK_SW 11 IN_DTA 12 RO 10 VEE_RO 16 9
FS0/SDEN 17
RSSI GND OUT_DEM GND 4321 CX1 XTAL
OUT_DTA 8 RSSI 7 OUT_DEM 6
VCC GND
IN_DTA GND OUT_DTA GND
GND SDTA SDEN SCLK
CB6 C0 L0 CF1 CF2 RF RPS CPS
18 VEE_DIG 19 FS1/LD 20 VCC_PLL 21 TNK_LO 22 VEE_PLL 23 LF 29 GAIN_LNA 27 VEE_LNA 25 OUT_PA 26 IN_LNA 30 IN_MIX 31 VEE_IF 24 28 OUT_LNA
C5 R2 R1 CB5 C6
TH7122
INT1 5 INT2/PDO 4 IN_DEM 3 VCC_IF 2 32 OUT_MIX IN_IFA 1
CTX4 LTX0 CTX1 CTX2
RL0 CERFIL
CB2
CTX0 LRX2 LTX1
CRX0
C2 C1 L1 CB1
VCC
50
TX_OUT RX_IN
Software Settings for ASK
Channel frequency 315.00 MHz 434.00 MHz 915.00 MHz fRO = 8.0000MHz RR 80 80 80 NR 3043 4233 9043 RT 8 8 8 NT 315 434 915 CPCUR RX 260A 260A 260A TX 1300A 1300A 1300A VCOCUR RX 300 A 300 A 300 A TX 900A 900A 900A
39012 07122 02 Rev. 005
Page 19 of 24
VCC
RB1
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
4.3.1
Part
C0 C1 C2 C5 C6 CB0 CB1 CB2 CB5 CB6 CB7 CF1 CF2 CPS CX1 CRX0 CTX0 CTX1 CTX2 CTX4 R1 R2 RB1 RF RP RL0 RPS RS1...RS3 L0
Board Component Values for ASK (peak detector option)
Size
0603 0603 0603 0603 0603 1210 0603 0603 0603 0603 0603 0603 0603 0603 0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
Value @ 315 MHz
1.8 pF 3.9 pF 1.5 pF 1.5 nF 100 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 100 pF 10 pF 10 pF 10 pF 12 pF 100 k 680 k 100 33 k 3.3 K 390 18 k 10 k 47 nH
Value @ 434 MHz
2.2 pF 4.7 pF 1.0 pF 1.5 nF 100 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 100 pF 10 pF 6.8 pF 6.8 pF 4.7 pF 100 k 680 k 100 33 k 3.3 K 390 33 k 10 k 27 nH
Value @ 915 MHz
1.8 pF 1 pF 1.5 pF 1.5 nF 100 nF 10 F 10 nF 330 pF 100 nF 100 pF 100 nF 100 pF 39 pF 1 nF 18 pF 10 pF 10 pF 4.7 pF 3.9 pF 1.8 pF 100 k 680 k 100 33 k 3.3 K 390 43 k 10 k 3.9 nH
Tol.
5% 5% 5% 10% 10% 20% 10% 10% 10% 10% 10% 10% 5% 10% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
Description
VCO tank capacitor LNA output tank capacitor MIX input matching capacitor RSSI output low pass capacitor PKDET capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor de-coupling capacitor loop filter capacitor loop filter capacitor power-select capacitor RO capacitor RX coupling capacitor TX coupling capacitor TX impedance matching capacitor TX impedance matching capacitor TX impedance matching capacitor PKDET resistor PKDET resistor protection resistor loop filter resistor CERDIS loading resistor CERFIL loading, optionally power-select resistor protection resistor VCO tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part LNA output tank inductor from Wurth-Elektronik (WE-KI series) or equivalent part impedance matching inductor from Wurth-Elektronik (WE-KI series) or equivalent part fundamental-mode crystal from: Telcona/Hong Kong X'tals C5L8000000D10F3EHK01 ceramic filter from Murata, or equivalent part
L1 LRX2 LTX0 LTX1 XTAL CERFIL
0603 0603 0603 0603 HC49 SMD 7x5 SMD 3.45x3.1
33 nH 82 nH 15 nH 33 nH
15 nH 56 nH 15 nH 33 nH
4.7 nH 15 nH 3.9 nH 10 nH
5% 5% 5% 5%
8.0000 MHz 20ppm cal., 20ppm temp. SFECF10M7HA00 B3dB = 180 kHz
39012 07122 02 Rev. 005
Page 20 of 24
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description
4.3.2 Component Arrangement Top Side for ASK Reception (peak detector option)
OUT DEM
1
R2 R1 C6
IN DTA
SDTA
GND
OUT DTA
GND
SDEN
SCLK
RSSI
GND
VCC
GND
GND
1
1
1
CB0
RS1 RS3 RS2
ASK/FSK
C5
GND LD VCC
3
1
1
1
1
1
XTAL
FS1
FS0
RE
TE
CB7
CB6 CF1 CF2
C0
RF RPS CPS C2 CTX0 CRX0 CTX4 CB2 LTX0 C1 L1 CB1 RB1
L0
CX1
CB5 RL0
CTX1
EVB7122_003
LTX1
LRX2
1
CTX2
TX_output
39012 07122 02 Rev. 005
Page 21 of 24
RX_input
Board size is 39.5mm x 56.5mm
Melexis
EVB Description June/07
GND
EVB7122
27 to 930MHz Transceiver Evaluation Board Description 5 Evaluation Board Layouts
* Board layout data in Gerber format is available, board size is 39.5mm x 56.5mm.
OUT DEM
OUT DTA
SDTA
GND
IN DTA
SDEN
RSSI
GND
GND
VCC
GND
GND
SCLK
GND LD VCC
FS1
FS0
EVB7122_003
RE
TE
ASK/FSK
Melexis
GND
PCB top view
PCB bottom view
6
Board Variants
Type EVB7122 Frequency/MHz -315 -433 -868 -915 Note: available EVB setups -FSK -ASK -FM according to section 4.2 / 4.3 Modulation -A -C Board Execution antenna version connector version
39012 07122 02 Rev. 005
Page 22 of 24
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description 7 Package Description
The device TH7122 is RoHS compliant.
D D1 24 25 17 A
16
b
E
E1
e
32
9
1
8 A2 A1 0.25 (0.0098)
12 +1
c
12 +1
L
.10 (.004)
Fig. 4:
LQFP32 (Low profile Quad Flat Package)
All Dimension in mm, coplanarity < 0.1mm E1, D1
min max min max 7.00
E, D
9.00
A
1.40 1.60 0.055 0.063
A1
0.05 0.15 0.002 0.006
A2
1.35 1.45 0.053 0.057
e
0.8
b
0.30 0.45 0.012 0.018
c
0.09 0.20 0.0035 0.0079
L
0.45 0.75 0.018 0.030
0 7 0 7
All Dimension in inch, coplanarity < 0.004"
0.276 0.354 0.031
7.1
Soldering Information
* The device TH7122 is qualified for MSL3 with soldering peak temperature 260 deg C according to JEDEC J-STD-20
39012 07122 02 Rev. 005
Page 23 of 24
EVB Description June/07
EVB7122
27 to 930MHz Transceiver Evaluation Board Description 8 Disclaimer
1) The information included in this documentation is subject to Melexis intellectual and other property rights. Reproduction of information is permissible only if the information will not be altered and is accompanied by all associated conditions, limitations and notices. 2) Any use of the documentation without the prior written consent of Melexis other than the one set forth in clause 1 is an unfair and deceptive business practice. Melexis is not responsible or liable for such altered documentation. 3) The information furnished by Melexis in this documentation is provided 'as is'. Except as expressly warranted in any other applicable license agreement, Melexis disclaims all warranties either express, implied, statutory or otherwise including but not limited to the merchantability, fitness for a particular purpose, title and non-infringement with regard to the content of this documentation. 4) Notwithstanding the fact that Melexis endeavors to take care of the concept and content of this documentation, it may include technical or factual inaccuracies or typographical errors. Melexis disclaims any responsibility in connection herewith. 5) Melexis reserves the right to change the documentation, the specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. 6) Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the information in this documentation. 7) The product described in this documentation is intended for use in normal commercial applications. Applications requiring operation beyond ranges specified in this documentation, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. 8) Any supply of products by Melexis will be governed by the Melexis Terms of Sale, published on www.melexis.com. (c) Melexis NV. All rights reserved.
For the latest version of this document, go to our website at:
www.melexis.com
Or for additional information contact Melexis Direct: Europe, Africa:
Phone: +32 1367 0495 E-mail: sales_europe@melexis.com
Americas:
Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com
Asia:
Phone: +32 1367 0495 E-mail: sales_asia@melexis.com
ISO/TS 16949 and ISO14001 Certified 39012 07122 02 Rev. 005 Page 24 of 24 EVB Description June/07

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