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CY2SSTV8575
Differential Clock Buffer/Driver
Features
* Operating frequency: 60 MHz to 170 MHz * Supports 266 MHz DDR SDRAM * 5 differential outputs from 1 differential input * Spread Spectrum compatible * Low jitter (cycle-to-cycle): < 75 * Very low skew: < 100 ps * Power Management Control input * High-impedance outputs when input clock < 20 MHz * 2.5V operation * 32-pin TQFP JEDEC MS-026 C
Description
The CY2SSTV8575 is a high-performance, low-skew, low jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV8575 generates five differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV8575 features differential feedback clock outputs and inputs. This allows the CY2SSTV8575 to be used as a zero-delay buffer. When used as a zero-delay buffer in nested clock trees, the CY2SSTV8575 locks onto the input reference and translates with near zero delay to low-skew outputs.
Block Diagram
Pin Configuration
FBOUT#
FBOUT
FBIN#
VSS OE
VDDQ
FBIN
2 1
OE AVDD
23 8
32 31 30 29 28 27 26 25
VSS VDDQ Y3 Y3# VDDQ Y4 Y4#
9 10 11 12 13 14 15 16 AVDD
Test and Powerdown Logic
12 11 15 16 27 28 30 31 18 19
Y0 Y0# Y1 Y1# Y2 Y2# Y3 Y3# Y4 Y4# FBOUT FBOUT#
24 23 22 21 20 19 18 17 Y2# Y2 VSS VDDQ Y1 Y1# VSS AVSS
CY2SSTV8575
TQFP-32 JEDEC MS-026 C
CLK CLK# FBIN FBI # N
5 6 21 22
PLL
VSS
12345678 VDDQ CK CK# Y0# Y0 VDDQ VDDQ
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
VSS
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CY2SSTV8575
Pin Description
Pin 5,6 21 22 2,12,15,27,30 1,11,16,28,31 18 Name CLK, CLK# FBIN# FBIN Y(0:4) Y(0:4)# FBOUT I/O I I I O O O Differential Outputs Differential Outputs Type LV Differential Input Differential Input Description Differential Clock Input Feedback Clock Input. Connect to FBOUT# for accessing the PLL. Feedback Clock Input. Connect to FBOUT for accessing the PLL. Clock + Outputs Clock - Outputs Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Feedback Clock Output. Connect to FBIN# for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Output Enable Input. When OE is set HIGH, all Q and Q# outputs are enabled and switch at the same frequency as CLK. When set LOW, all Q and Q# outputs are disabled (Hi-Z) and the PLL is powered down. 2.5V Nominal 2.5V Nominal 2.5V Power Supply for Output Clock Buffers 2.5V Power Supply for PLL. When AVDD is at GND, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (OE = 0), the PLL is powered down. Common Ground Analog Ground
19
FBOUT#
O
23
OE
I
3,4,7,13,20,26, 29 8
VDDQ AVDD
10,14,17,24,25, 32 9
VSS AVSS
0.0V Ground 0.0V Analog Ground
Table 1. Function Table INPUTS AVDD GND GND X X 2.5V 2.5V 2.5V OE H H L L H H H CLK L H L H L H < 20 MHz CLK# H L H L H L < 20 MHz Y L H Z Z L H Hi-Z Y# H L Z Z H L Hi-Z OUTPUTS FBOUT L H Z Z L H Hi-Z FBOUT# H L Z Z H L HI-Z BYPASSED/OFF BYPASSED/OFF Off OFF On On Off PLL
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CY2SSTV8575
Power Management Functions
Output enable/disable control of the CY2SSTV8575 allows the user to implement power management schemes into the design. Outputs are three-stated/disabled when OE is asserted low, see Table 1. The enabling and disabling of outputs is done in such a manner to eliminate the possibility of the partial "runt" clocks. PLL reference. The CY2SSTV8575 can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with tine input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When AVDD is strapped LOW, the PLL is turned off and bypassed for test purposes.
Zero Delay Buffer
When used as a zero delay buffer the CY2SSTV8575 will likely be in a nested clock tree application. For these applications the CY2SSTV8575 offers a differential clock input pair as a
= 2.5" DDR _SDRAM represents a capacitive load CLK 120 Ohm CLK# Yx Yx# FBIN 120 Ohm FBIN# FBOUT FBOUT# PLL
= 0.6" (Split to Terminator)
DDR SDRAM
VTR 120 Ohm VCP DDR SDRAM 0.3"
Figure 1. Clock Structure 1[1]
Note: 1. Output load capacitance for 2 DDR-SDRAM loads: 5 pF < CL < 8 pF.
Rev 1.0, November 25, 2006
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CY2SSTV8575
= 2.5" DDR-SDRAM represents a capacitive load CLK 120 Ohm CLK# Yx Yx# FBIN 120 Ohm PLL
= 0.6" (Split to Terminator)
DDR-SDRAM
DDR-SDRAM Stack
DDR-SDRAM
VTR 120 Ohm VCP
DDR-SDRAM
FBIN#
FBOUT FBOUT# 0.3"
DDR-SDRAM
DDR-SDRAM Stack
Figure 2. Clock Structure 2[2]
VDD
VD D
V D D/2 14 pF
OUT
60 O hm
VT R R T = 120 O hm
OUT#
60 O hm VC P
14 pF V D D /2
R eceiver
Figure 3. Differential Signal Using Direct Termination Resistor
Governing Agencies
The following agencies provide specifications that apply to the CY2SSTV8575. The agency name and relevant specification is listed below; Agency Name ....................................................................... JEDEC................................................................. MS - 026-C
Note: 2. Output load capacitance for 4 DDR-SDRAM loads: 10 pF < CL < 16 pF.
Specification
Rev 1.0, November 25, 2006
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CY2SSTV8575
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Table 2. Parameter Vdd VDD Vin Vout Ts Ta OJc OJa ESDh FIT Description Supply Voltage Operating Voltage Input Voltage Output Voltage Temperature, Storage Temperature, Operating Ambient Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Conditions Non Functional Functional Relative to VSS Relative to VSS Non Functional Functional Functional Functional Min. -0.3 2.38 -0.3 -0.3 -65 0 - - - - Max. 3.5 2.63 2.63 2.63 150 +85 18 48 2K 10 Unit VDC VDC VDC VDC C C C/W C/W Volts ppm For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD (VDDQ Voltage) Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDDQ).
DC Parameters (AVDD = VDDO = 2.5 5%, Temperature = 0C to +85C)
Parameter VIL VIH VOL VOH IOL IOH IDDQ IPDS Cin Description Input Voltage, Low[3] Input Voltage, High[3] Output Voltage, Low Output Voltage, High Output Low Current Output High Current Dynamic Supply Current[4] Power Down Current Input pin capacitance VDDQ = 2.375V, IOL = 12 mA VDDQ = 2.375V, IOH = -12 mA VDDQ = 2.375V, VOUT = 1.2V VDDQ = 2.375V, VOUT = 1V ALL VDDQ, FO = 170 MHz OE = 0 or CLK/CLK# 20 MHz OE Conditions Min. - 1.75 - 1.7 26 28 - - - Typ. - - - - 35 -32 235 - - Max. 0.75 - 0.6 - - - 300 100 4 Unit V V V V mA mA mA. A. pF
Notes: 3. Unused inputs must be held high or low to prevent them from floating. 4. All outputs switching loaded with 16pF in 60 environment. See Figure 3.
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CY2SSTV8575
AC Input Parameters (AVDD = VDDQ = 2.5 5%, TA = 0C to +85C)
Parameter Fin DTYC Description Input Frequency Input Duty Cycle 1.25 AVDD, VDD = 2.5V0.2V Conditions Min. 60 40 Typ. - - Max. 170 60 Unit MHz %
AC Output Parameters (AVDD= VDDQ = 2.5 5%, Temperature = 0C to +85C)[5,6]
Parameter FOR tLOCK DTYC TR TF tSKEW TPLH TPHL TODIS TOENB TJIT(CC) TPHASE TJIT(PHASE) Description Output frequency range Maximum PLL Lock Time Duty Cycle[7] Conditions AVDD, VDD = 2.5V0.2V AVDD, VDD = 2.5V0.2V 60 MHz to 100 MHz 101 MHz to 170 MHz Rise Time Fall Time Any Output to Any Output Skew[9] 20% to 80% of VOD 20% to 80% of VOD All outputs equally loaded CLK to Y CLK to Y All outputs All outputs All outputs @ 66 MHz Min. 60 - 49.5 49 1 1 - 1.5 1.5 - - -100 -150 All outputs @ 66 MHz -50 Typ. - - 50 - - - - 3.5 3.5 3 3 - - - Max. 170 100 50.5 51 2 2 100 6 6 - - -100 150 50 Unit MHz S % % V/ns V/ns ps ns ns ns ns ps ps ps
Propagation Delay (Low to High) Propagation Delay (High to Low) Output Disable Output Enable Time[8] Time[8]
Cycle to Cycle Jitter Phase Error Phase Error Jitter
Notes: 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. 6. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 50 kHz with a down spread of -0.5%. 7. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC, where the cycle time (tC) decreases as the frequency goes up. 8. Refers to transition of non-inverting output. 9. All differential input and output terminals are terminated with 120 /16 pF as shown in Figure 2.
Rev 1.0, November 25, 2006
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CY2SSTV8575
Ordering Information
Part Number CY2SSTV8575AC CY2SSTV8575ACT 32-pin TQFP 32-pin TQFP -Tape & Reel Package Type Product Flow Commercial, 0 to 85 C Commercial, 0 to 85 C
Package Drawing and Dimension
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51 85063 *B
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 25, 2006
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