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| Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers AD8605/AD8606/AD8608 FEATURES Low offset voltage: 65 V maximum Low input bias currents: 1 pA maximum Low noise: 8 nV/Hz Wide bandwidth: 10 MHZ High open-loop gain: 1000 V/mV Unity gain stable Single-supply operation: 2.7 V to 5.5 V 5-ball WLCSP for single (AD8605) and 8-ball WLCSP for dual (AD8606) FUNCTIONAL BLOCK DIAGRAMS BALL A1 CORNER OUTA A1 V+ A2 OUTB A3 -INA B1 -INB B3 +INA OUT 1 V- 2 V- C2 +INB 02731-057 AD8605 TOP VIEW (Not to Scale) 5 V+ C1 C3 +IN 3 4 -IN 02731-001 APPLICATIONS Photodiode amplification Battery-powered instrumentation Multipole filters Sensors Barcode scanners Audio AD8606 TOP VIEW (BALL SIDE DOWN) Figure 1. 5-Lead SOT-23 (RJ Suffix) TOP VIEW (BUMP SIDE DOWN) OUT 1 V- 2 +IN 3 -IN 02731-006 Figure 2. 8-Ball WLCSP (CB Suffix) OUT A 1 -IN A 2 +IN A 3 V+ 4 +IN B 5 -IN B 6 OUT B 7 14 OUT D 13 -IN D V+ 5 AD8608 TOP VIEW (Not to Scale) 12 +IN D 11 V- 10 +IN C 02731-004 GENERAL DESCRIPTION The AD8605, AD8606, and AD8608 1 are single, dual, and quad rail-to-rail input and output, single-supply amplifiers. They feature very low offset voltage, low input voltage and current noise, and wide signal bandwidth. They use the Analog Devices, Inc. patented DigiTrim(R) trimming technique, which achieves superior precision without laser trimming. The combination of low offsets, low noise, very low input bias currents, and high speed makes these amplifiers useful in a wide variety of applications. Filters, integrators, photodiode amplifiers, and high impedance sensors all benefit from the combination of performance features. Audio and other ac applications benefit from the wide bandwidth and low distortion. Applications for these amplifiers include optical control loops, portable and loop-powered instrumentation, and audio amplification for portable devices. The AD8605, AD8606, and AD8608 are specified over the extended industrial temperature range (-40C to +125C). The AD8605 single is available in 5-lead SOT-23 and 5-ball WLCSP packages. The AD8606 dual is available in an 8-lead MSOP, an 8-ball WLSCP, and a narrow SOIC surface-mounted package. The AD8608 quad is available in a 14-lead TSSOP package and a narrow 14-lead SOIC package. The 5-ball and 8-ball WLCSP offer the smallest available footprint for any surface-mounted operational amplifier. The WLCSP, SOT-23, MSOP, and TSSOP versions are available in tape-and-reel only. 1 4 9 -IN C 8 OUT C AD8605 ONLY Figure 3. 5-Ball WLCSP (CB Suffix) Figure 4. 14-Lead SOIC_N (R Suffix) OUT A -IN A +IN A V+ +IN B -IN B OUT B 1 14 OUT D -IN D +IN D V- +IN C -IN C OUT C 7 8 Figure 5. 8-Lead MSOP (RM Suffix), 8-Lead SOIC_N (R Suffix) Figure 6. 14-Lead TSSOP (RU Suffix) Protected by U.S. Patent No. 5,969,657; other patents pending. Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2002-2008 Analog Devices, Inc. All rights reserved. 02731-002 OUT A -IN A +IN A V- 1 AD8606 8 TOP VIEW (Not to Scale) 4 5 V+ OUT B -IN B +IN B AD8608 TOP VIEW (Not to Scale) 02731-003 AD8605/AD8606/AD8608 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 3 5 V Electrical Specifications ............................................................ 4 2.7 V Electrical Specifications ......................................................... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution .................................................................................. 8 Typical Performance Characteristics ............................................. 9 Applications Information .............................................................. 15 Output Phase Reversal ............................................................... 15 Maximum Power Dissipation ................................................... 15 Input Overvoltage Protection ................................................... 15 THD + Noise ............................................................................... 15 Total Noise Including Source Resistors ................................... 16 Channel Separation .................................................................... 16 Capacitive Load Drive ............................................................... 16 Light Sensitivity .......................................................................... 17 WLCSP Assembly Considerations ........................................... 17 I-V Conversion Applications ........................................................ 18 Photodiode Preamplifier Applications .................................... 18 Audio and PDA Applications ................................................... 18 Instrumentation Amplifiers ...................................................... 19 DAC Conversion ........................................................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 22 Rev. H | Page 2 of 24 AD8605/AD8606/AD8608 REVISION HISTORY 2/08--Rev. G to Rev. H Changes to Features ..................................................................... 1 Changes to Table 1 ....................................................................... 4 Changes to Table 2 ....................................................................... 6 Changes to Figure 11 ................................................................... 9 Changes to Figure 13, Figure 14, and Figure 16 Captions .... 10 Changes to Figure 15, Figure 17, and Figure 18 ..................... 10 Changes to Figure 34 and Figure 35 Captions........................ 13 Changes to Figure 36 ................................................................. 13 Changes to Figure 37 Caption .................................................. 14 Changes to Figure 38 and Figure 41 ........................................ 14 Changes to Figure 45 ................................................................. 15 Changes to Audio and PDA Applications Section ................. 18 Changes to Figure 52 ................................................................. 18 Changes to Ordering Guide ...................................................... 22 10/07--Rev. F to Rev. G Changes to Figure 2...................................................................... 1 Updated Outline Dimensions ................................................... 20 8/07--Rev. E to Rev. F Added 8-Ball WLCSP Package ..................................... Universal Changes to Features ..................................................................... 1 Changes to Table 1 ....................................................................... 3 Changes to Table 2 ....................................................................... 5 Changes to Table 4 ....................................................................... 7 Updated Outline Dimensions ................................................... 19 Changes to Ordering Guide ...................................................... 21 1/06--Rev. D to Rev. E Changes to Table 1 ....................................................................... 3 Changes to Table 2 ....................................................................... 5 Changes to Table 4 ....................................................................... 6 Changes to Figure 12 Caption .................................................... 8 Changes to Figure 26 and Figure 27 Captions........................ 11 Changes to Figure 33 Caption .................................................. 12 Changes to Figure 44 ................................................................. 14 Updated Outline Dimensions ................................................... 19 Changes to Ordering Guide ...................................................... 20 5/04--Rev. C to Rev. D Updated Format.............................................................. Universal Edit to Light Sensitivity Section ............................................... 16 Updated Outline Dimensions................................................... 19 Changes to Ordering Guide ...................................................... 20 7/03--Rev. B to Rev. C Changes to Features .......................................................................1 Change to General Description....................................................1 Addition to Functional Block Diagrams .....................................1 Addition to Absolute Maximum Ratings ....................................4 Addition to Ordering Guide .........................................................4 Change to Equation in Maximum Power Dissipation Section .......................................................................................... 11 Added Light Sensitivity Section ................................................ 12 Added New Figure 8; Renumbered Subsequently .................. 13 Added New MicroCSP Assembly Considerations Section.... 13 Changes to Figure 9 .................................................................... 13 Change to Equation in Photodiode Preamplifier Applications Section .................................................................. 13 Changes to Figure 12 .................................................................. 14 Change to Equation in D/A Conversion Section.................... 14 Updated Outline Dimensions ................................................... 15 3/03--Rev. A to Rev. B Changes to Functional Block Diagram .......................................1 Changes to Absolute Maximum Ratings.....................................4 Changes to Ordering Guide ........................................................ 4 Changes to Figure 9 ................................................................... 13 Updated Outline Dimensions.................................................... 15 11/02--Rev. 0 to Rev. A Change to Electrical Characteristics............................................2 Changes to Absolute Maximum Ratings.....................................4 Changes to Ordering Guide .........................................................4 Change to TPC 6 ...........................................................................5 Updated Outline Dimensions.................................................... 15 5/02--Revision 0: Initial Version Rev. H | Page 3 of 24 AD8605/AD8606/AD8608 5 V ELECTRICAL SPECIFICATIONS VS = 5 V, VCM = VS/2, TA = 25C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage AD8605/AD8606 (Except WLCSP) AD8608 AD8605/AD8606/AD8608 Input Bias Current AD8605/AD8606 AD8605/AD8606 AD8608 AD8608 Input Offset Current Symbol VOS VS = 3.5 V, VCM = 3 V VS = 3.5 V, VCM = 2.7 V VS = 5 V, VCM = 0 V to 5 V -40C < TA < +125C IB -40C < TA < +85C -40C < TA < +125C -40C < TA < +85C -40C < TA < +125C IOS -40C < TA < +85C -40C < TA < +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift AD8605/AD8606 AD8608 INPUT CAPACITANCE Common-Mode Input Capacitance Differential Input Capacitance OUTPUT CHARACTERISTICS Output Voltage High CMRR AVO VOS/T VOS/T CCOM CDIFF VOH IL = 1 mA IL = 10 mA -40C < TA < +125C IL = 1 mA IL= 10 mA -40C < TA < +125C f = 1 MHz, AV = 1 4.96 4.7 4.6 VCM = 0 V to 5 V -40C < TA < +125C RL = 2 k, VO = 0.5 V to 4.5 V -40C < TA < +125C -40C < TA < +125C 0 85 75 300 100 90 1000 1 1.5 8.8 2.6 4.98 4.79 20 170 80 1 40 210 290 4.5 6.0 0.1 20 20 80 0.2 65 75 300 750 1 50 250 100 300 0.5 20 75 5 V V V V pA pA pA pA pA pA pA pA V dB dB V/mV V/C V/C pF pF V V V mV mV mV mA Conditions Min Typ Max Unit Output Voltage Low VOL Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio AD8605/AD8606 AD8605/AD8606 WLCSP AD8608 Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Unity Gain Bandwidth Product Phase Margin IOUT ZOUT PSRR ISY VS = 2.7 V to 5.5 V VS = 2.7 V to 5.5 V VS = 2.7 V to 5.5 V -40C < TA < +125C IOUT = 0 mA -40C < TA < +125C RL = 2 k, CL = 16 pF To 0.01%, 0 V to 2 V step, AV = 1 80 75 77 70 95 92 92 90 1 1.2 1.4 dB dB dB dB mA mA V/s s MHz Degrees SR tS GBP M 5 <1 10 65 Rev. H | Page 4 of 24 AD8605/AD8606/AD8608 Parameter NOISE PERFORMANCE Peak-to-Peak Noise Voltage Noise Density Current Noise Density Symbol en p-p en en in Conditions f = 0.1 Hz to 10 Hz f = 1 kHz f = 10 kHz f = 1 kHz Min Typ 2.3 8 6.5 0.01 Max 3.5 12 Unit V p-p nV/Hz nV/Hz pA/Hz Rev. H | Page 5 of 24 AD8605/AD8606/AD8608 2.7 V ELECTRICAL SPECIFICATIONS VS = 2.7 V, VCM = VS/2, TA = 25C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage AD8605/AD8606 (Except WLCSP) AD8608 AD8605/AD8606/AD8608 Input Bias Current AD8605/AD8606 AD8605/AD8606 AD8608 AD8608 Input Offset Current Symbol VOS VS = 3.5 V, VCM = 3 V VS = 3.5 V, VCM = 2.7 V VS = 2.7 V, VCM = 0 V to 2.7 V -40C < TA < +125C IB -40C < TA < +85C -40C < TA < +125C -40C < TA < +85C -40C < TA < +125C IOS -40C < TA < +85C -40C < TA < +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift AD8605/AD8606 AD8608 INPUT CAPACITANCE Common-Mode Input Capacitance Differential Input Capacitance OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio AD8605/AD8606 AD8605/AD8606 WLCSP AD8608 Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Unity Gain Bandwidth Product Phase Margin CMRR AVO VOS/T VOS/T CCOM CDIFF VOH VOL IOUT ZOUT PSRR VS = 2.7 V to 5.5 V VS = 2.7 V to 5.5 V VS = 2.7 V to 5.5 V -40C < TA < +125C IOUT = 0 mA -40C < TA < +125C RL = 2 k, CL = 16 pF To 0.01%, 0 V to 1 V step, AV = 1 80 75 77 70 95 92 92 90 1.15 dB dB dB dB mA mA V/s s MHz Degrees IL = 1 mA -40C < TA < +125C IL = 1 mA -40C < TA < +125C f = 1 MHz, AV = 1 2.6 2.6 VCM = 0 V to 2.7 V -40C < TA < +125C RL = 2 k, VO = 0.5 V to 2.2 V -40C < TA < +125C -40C < TA < +125C 0 80 70 110 95 85 350 1 1.5 8.8 2.6 2.66 25 30 1.2 40 50 4.5 6.0 0.1 20 20 80 0.2 65 75 300 750 1 50 250 100 300 0.5 20 75 2.7 V V V V pA pA pA pA pA pA pA pA V dB dB V/mV V/C V/C pF pF V V mV mV mA Conditions Min Typ Max Unit ISY 1.4 1.5 SR tS GBP M 5 <0.5 9 50 Rev. H | Page 6 of 24 AD8605/AD8606/AD8608 Parameter NOISE PERFORMANCE Peak-to-Peak Noise Voltage Noise Density Current Noise Density Symbol en p-p en en in Conditions f = 0.1 Hz to 10 Hz f = 1 kHz f = 10 kHz f = 1 kHz Min Typ 2.3 8 6.5 0.01 Max 3.5 12 Unit V p-p nV/Hz nV/Hz pA/Hz Rev. H | Page 7 of 24 AD8605/AD8606/AD8608 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Input Voltage Differential Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range All Packages Operating Temperature Range All Packages Junction Temperature Range All Packages Lead Temperature (Soldering, 60 sec) Rating 6V GND to VS 6V Observe Derating Curves -65C to +150C -40C to +125C -65C to +150C 300C Table 4. Package Type 5-Ball WLCSP (CB) 5-Lead SOT-23 (RJ) 8-Ball WLCSP (CB) 8-Lead MSOP (RM) 8-Lead SOIC_N (R) 14-Lead SOIC_N (R) 14-Lead TSSOP (RU) 1 JA1 170 240 115 206 157 105 148 JC 92 44 56 36 23 Unit C/W C/W C/W C/W C/W C/W C/W JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. H | Page 8 of 24 AD8605/AD8606/AD8608 TYPICAL PERFORMANCE CHARACTERISTICS 4500 VS = 5V 4000 TA = 25C VCM = 0V TO 5V 3500 0.30 0.25 0.20 0.15 0.10 VOS (mV) NUMBER OF AMPLIFIERS 3000 2500 2000 1500 1000 02731-007 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 0 0.5 1.0 1.5 2.0 2.5 3.0 VCM (V) 3.5 4.0 4.5 02731-010 500 0 -300 -200 -100 0 100 OFFSET VOLTAGE (V) 200 300 5.0 Figure 7. Input Offset Voltage Distribution 24 Figure 10. Input Offset Voltage vs. Common-Mode Voltage (200 Units, 5 Wafer Lots, Including Process Skews) 360 320 VS = 5V 20 VS = 5V TA = -40C TO +125C VCM = 2.5V 16 INPUT BIAS CURRENT (pA) NUMBER OF AMPLIFIERS 280 240 AD8605/AD8606 200 160 AD8608 120 80 02731-011 12 8 4 02731-008 40 0 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 TCVOS (V/C) 3.6 4.0 4.4 4.8 0 25 50 75 TEMPERATURE (C) 100 125 Figure 8. AD8608 Input Offset Voltage Drift Distribution Figure 11. Input Bias Current vs. Temperature 20 18 16 OUTPUT SATURATION VOLTAGE (mV) VS = 5V TA = -40C TO +125C VCM = 2.5V 1k VS = 5V TA = 25C 100 NUMBER OF AMPLIFIERS 14 12 10 8 6 4 2 0 0 02731-009 10 SOURCE 1 02731-012 SINK 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 TCVOS (V/C) 0.1 0.001 0.01 0.1 LOAD CURRENT (mA) 1 10 Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution Figure 12. Output Saturation Voltage vs. Load Current Rev. H | Page 9 of 24 AD8605/AD8606/AD8608 5.00 VOH @ 1mA LOAD VS = 5V 4.90 6 4.95 OUTPUT VOLTAGE (V) 5 OUTPUT SWING (V p-p) 4 4.85 3 VS = 5V VIN = 4.9V p-p TA = 25C RL = 2k AV = 1 4.80 VOH @ 10mA LOAD 4.75 02731-013 2 1 02731-016 4.70 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 1k 10k TEMPERATURE (C) 100k FREQUENCY (Hz) 1M 10M Figure 13. Output Voltage Swing High vs. Temperature Figure 16. Closed-Loop Output Voltage Swing (FPBW) 0.25 VS = 5V 0.20 OUTPUT IMPEDANCE () OUTPUT VOLTAGE (V) 100 VOL @ 10mA LOAD 90 80 70 60 50 40 30 20 02731-014 VS = 5V 0.15 AV = 100 0.10 AV = 10 AV = 1 0.05 VOL @ 1mA LOAD 0 -40 10 0 1k 10k 100k 1M FREQUENCY (Hz) 10M -25 -10 5 20 35 50 65 80 95 110 125 100M TEMPERATURE (C) Figure 14. Output Voltage Swing Low vs. Temperature Figure 17. Output Impedance vs. Frequency 100 80 60 40 GAIN (dB) 20 0 -20 -40 -60 -80 -100 10k 100k 1M FREQUENCY (Hz) 10M 40M VS = 2.5V RL = 2k CL = 20pF M = 64 225 180 135 90 PHASE (Degrees) CMRR (dB) 120 110 100 90 80 70 60 50 40 02731-015 02731-018 VS = 5V 45 0 -45 -90 -135 -180 -225 30 20 1k 10k 100k 1M FREQUENCY (Hz) 10M Figure 15. Open-Loop Gain and Phase vs. Frequency Figure 18. Common-Mode Rejection Ratio (CMRR) vs. Frequency Rev. H | Page 10 of 24 02731-017 AD8605/AD8606/AD8608 140 120 100 80 PSRR (dB) 1.0 VS = 5V 0.9 SUPPLY CURRENT/AMPLIFIER (mA) 02731-019 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 02731-022 60 40 20 0 -20 -40 -60 1k 10k 100k FREQUENCY (Hz) 1M 10M SUPPLY VOLTAGE (V) Figure 19. PSRR vs. Frequency Figure 22. Supply Current/Amplifier vs. Supply Voltage 45 40 SMALL SIGNAL OVERSHOOT (%) 30 25 +OS 20 -OS 15 10 02731-020 VOLTAGE NOISE (1V/DIV) 35 VS = 5V RL = TA = 25C AV = 1 VS = 5V 5 0 10 100 CAPACITANCE (pF) 1k TIME (1s/DIV) Figure 20. Small Signal Overshoot vs. Load Capacitance Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise 2.0 SUPPLY CURRENT/AMPLIFIER (mA) VS = 2.7V 1.0 VS = 5V 0.5 02731-021 02731-024 0 -40 VOLTAGE (50mV/DIV) 1.5 VS = 2.5V RL = 10k CL = 200pF AV = 1 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 TIME (200ns/DIV) Figure 21. Supply Current/Amplifier vs. Temperature Figure 24. Small Signal Transient Response Rev. H | Page 11 of 24 02731-023 AD8605/AD8606/AD8608 VS = 2.5V RL = 10k CL = 200pF AV = 1 VOLTAGE (1V/DIV) 36 VS = 2.5V 32 VOLTAGE NOISE DENSITY (nV/ Hz) 28 24 20 16 12 02731-028 02731-025 8 4 TIME (400ns/DIV) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (kHz) Figure 25. Large Signal Transient Response Figure 28. Voltage Noise Density vs. Frequency VOUT VOLTAGE NOISE DENSITY (nV/ Hz) 2.5V VS = 2.5V RL = 10k AV = -100 VIN = 50mV 53.6 VS = 2.5V 46.9 40.2 33.5 26.8 20.1 13.4 02731-029 0V 0V VIN -50mV 02731-026 6.7 0 0 1 2 3 4 5 6 FREQUENCY (kHz) 7 8 9 10 TIME (400ns/DIV) Figure 26. Positive Overload Recovery 119.2 Figure 29. Voltage Noise Density vs. Frequency 0V VOLTAGE NOISE DENSITY (nV/ Hz) VS = 2.5V RL = 10k AV = -100 VIN = 50mV VS = 2.5V 104.3 89.4 74.5 59.6 44.7 29.8 02731-030 -2.5V 50mV 0V 02731-027 14.9 0 0 10 20 30 40 50 60 FREQUENCY (Hz) 70 80 90 TIME (1s/DIV) 100 Figure 27. Negative Overload Recovery Figure 30. Voltage Noise Density vs. Frequency Rev. H | Page 12 of 24 AD8605/AD8606/AD8608 1800 1600 1400 OUTPUT VOLTAGE (V) 2.680 VS = 2.7V TA = 25C VCM = 0V TO 2.7V VS = 2.7V 2.675 NUMBER OF AMPLIFIERS 1200 1000 800 600 400 2.670 2.665 VOH @ 1mA LOAD 2.660 2.655 02731-031 0 -300 -200 -100 0 100 200 300 2.650 -40 -25 -10 5 20 35 50 65 80 95 110 125 OFFSET VOLTAGE (V) TEMPERATURE (C) Figure 31. Input Offset Voltage Distribution Figure 34. Output Voltage Swing High vs. Temperature 300 VS = 2.7V TA = 25C 200 0.045 VS = 2.7V 0.040 0.035 INPUT OFFSET VOLTAGE (V) 100 OUTPUT VOLTAGE (V) 0.030 0.025 0.020 0.015 0.010 VOL @ 1mA LOAD 0 -100 -200 02731-032 -300 0 0 0.9 1.8 2.7 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 COMMON-MODE VOLTAGE (V) TEMPERATURE (C) Figure 32. Input Offset Voltage vs. Common-Mode Voltage (200 Units, 5 Wafer Lots, Including Process Skews) 1k VS = 2.7V TA = 25C 100 Figure 35. Output Voltage Swing Low vs. Temperature 100 80 60 40 GAIN (dB) SOURCE 225 VS = 2.7V RL = 2k CL = 20pF M = 52.5 180 135 90 45 0 -45 -90 -135 -180 100k 1M FREQUENCY (Hz) 10M -225 40M 02731-036 OUTPUT SATURATION VOLTAGE (mV) 20 0 -20 -40 -60 10 SINK 1 02731-033 -80 -100 10k 0.1 0.001 0.01 0.1 LOAD CURRENT (mA) 1 10 Figure 33. Output Saturation Voltage vs. Load Current Figure 36. Open-Loop Gain and Phase vs. Frequency Rev. H | Page 13 of 24 PHASE (Degrees) 02731-035 0.005 02731-034 200 AD8605/AD8606/AD8608 3.0 VS = 2.7V 2.5 OUTPUT SWING (V p-p) 2.0 1.5 VS = 2.7V VIN = 2.6V p-p TA = 25C RL = 2k AV = 1 1.0 0 1k 10k 100k FREQUENCY (Hz) 1M 02731-037 10M TIME (1s/DIV) Figure 37. Closed-Loop Output Voltage Swing vs. Frequency (FPBW) Figure 40. 0.1 Hz to 10 Hz Input Voltage Noise 100 90 80 VS = 2.7V OUTPUT IMPEDANCE () VS = 1.35V RL = 10k CL = 200pF AV = 1 AV = 100 AV = 10 70 60 50 40 30 20 10 0 1k 10k 100k 1M FREQUENCY (Hz) 10M 02731-038 AV = 1 VOLTAGE (50mV/DIV) 100M TIME (200ns/DIV) Figure 38. Output Impedance vs. Frequency Figure 41. Small Signal Transient Response 60 VS = 2.7V TA = 25C AV = 1 VS = 1.35V RL = 10k CL = 200pF AV = 1 SMALL SIGNAL OVERSHOOT (%) 50 40 -OS 30 +OS 20 10 02731-039 02731-042 0 10 100 CAPACITANCE (pF) 1k VOLTAGE (1V/DIV) TIME (400ns/DIV) Figure 39. Small Signal Overshoot vs. Load Capacitance Figure 42. Large Signal Transient Response Rev. H | Page 14 of 24 02731-041 02731-040 0.5 VOLTAGE NOISE (1V/DIV) AD8605/AD8606/AD8608 APPLICATIONS INFORMATION OUTPUT PHASE REVERSAL Phase reversal is defined as a change in polarity at the output of the amplifier when a voltage that exceeds the maximum input common-mode voltage drives the input. Phase reversal can cause permanent damage to the amplifier; it can also cause system lockups in feedback loops. The AD8605 does not exhibit phase reversal even for inputs exceeding the supply voltage by more than 2 V. VS = 2.5V VIN = 6V p-p AV = 1 RL = 10k VOUT VOLTAGE (2V/DIV) VIN MAXIMUM POWER DISSIPATION Power dissipated in an IC causes the die temperature to increase, which can affect the behavior of the IC and the application circuit performance. The absolute maximum junction temperature of the AD8605/ AD8606/AD8608 is 150C. Exceeding this temperature could damage or destroy the device. POWER DISSIPATION (W) 02731-043 TIME (4s/DIV) Figure 43. No Phase Reversal 1.8 1.7 SOIC-14 1.6 1.5 1.4 TSSOP-14 1.3 1.2 1.1 1.0 SOIC-8 0.9 0.8 0.7 0.6 MSOP-8 0.5 WLCSP-5 0.4 0.3 5-LEAD SOT-23 0.2 0.1 0 -45 -20 5 55 30 80 AMBIENT TEMPERATURE (C) The maximum power dissipation of the amplifier is calculated according to PDISS = TJ - TA JA Figure 44 compares the maximum power dissipation with temperature for the various AD860x family packages. 105 130 Figure 44. Maximum Power Dissipation vs. Ambient Temperature 0.1 VSY = 2.5V AV = 1 BW = 80kHz INPUT OVERVOLTAGE PROTECTION The AD8605 has internal protective circuitry. However, if the voltage applied at either input exceeds the supplies by more than 2.5 V, external resistors should be placed in series with the inputs. The resistor values can be determined by VIN - VS 5 mA RS + 200 The remarkable low input offset current of the AD8605 (<1 pA) allows the use of larger value resistors. With a 10 k resistor at the input, the output voltage has less than 10 nV of error voltage. A 10 k resistor has less than 13 nV/Hz of thermal noise at room temperature. THD + NOISE (%) 0.01 0.001 0.0001 20 100 THD + NOISE Total harmonic distortion is the ratio of the input signal in V rms to the total harmonics in V rms throughout the spectrum. Harmonic distortion adds errors to precision measurements and adds unpleasant sonic artifacts to audio systems. The AD8605 has a low total harmonic distortion. Figure 45 shows that the AD8605 has less than 0.005% or -86 dB of THD + N over the entire audio frequency range. The AD8605 is configured in positive unity gain, which is the worst case, and with a load of 10 k. Rev. H | Page 15 of 24 1k FREQUENCY (Hz) 10k 20k Figure 45. THD + Noise vs. Frequency 02731-045 02731-044 where: TJ is the junction temperature. TA is the ambient temperature. JA is the junction-to-ambient thermal resistance. AD8605/AD8606/AD8608 TOTAL NOISE INCLUDING SOURCE RESISTORS The low input current noise and input bias current of the AD8605 make it the ideal amplifier for circuits with substantial input source resistance, such as photodiodes. Input offset voltage increases by less than 0.5 nV per 1 k of source resistance at room temperature and increases to 10 nV at 85C. The total noise density of the circuit is en , TOTAL = en 2 + (in RS ) 2 + 4k TRS A snubber network, shown in Figure 48, helps reduce the signal overshoot to a minimum and maintain stability. Although this circuit does not recover the loss of bandwidth induced by large capacitive loads, it greatly reduces the overshoot and ringing. This method does not reduce the maximum output swing of the amplifier. 0 -20 CHANNEL SEPARATION (dB) -40 -60 -80 -100 -120 -140 02731-046 where: en is the input voltage noise density of the AD8605. in is the input current noise density of the AD8605. RS is the source resistance at the noninverting terminal. k is Boltzmann's constant (1.38 x 10-23 J/K). T is the ambient temperature in Kelvin (T = 273 + C). For example, with RS = 10 k, the total voltage noise density is roughly 15 nV/Hz. For RS < 3.9 k, en dominates and en, TOTAL en. The current noise of the AD8605 is so low that its total density does not become a significant term unless RS is greater than 6 M. The total equivalent rms noise over a specific bandwidth is expressed as -160 -180 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M Figure 46. Channel Separation vs. Frequency En = en, TOTAL ( ) BW VOLTAGE (100mV/DIV) VS = 2.5V AV = 1 RL = 10k CL = 1000pF where BW is the bandwidth in hertz. Note that the previous analysis is valid for frequencies greater than 100 Hz and assumes relatively flat noise, above 10 kHz. For lower frequencies, flicker noise (1/f) must be considered. CHANNEL SEPARATION Channel separation, or inverse crosstalk, is a measure of the signal feed from one amplifier (channel) to another on the same IC. The AD8606 has a channel separation of greater than -160 dB up to frequencies of 1 MHz, allowing the two amplifiers to amplify ac signals independently in most applications. TIME (10s/DIV) Figure 47. AD8606 Capacitive Load Drive Without Snubber CAPACITIVE LOAD DRIVE The AD860x can drive large capacitive loads without oscillation. Figure 47 shows the output of the AD8606 in response to a 200 mV input signal. In this case, the amplifier is configured in positive unity gain, worst case for stability, while driving a 1000 pF load at its output. Driving larger capacitive loads in unity gain can require the use of additional circuitry. V+ 4 2 200mV VIN 3 1 RS 8 V- CS RL CL 02731-049 AD8605 Figure 48. Snubber Network Configuration Rev. H | Page 16 of 24 02731-047 AD8605/AD8606/AD8608 Figure 49 shows a scope of the output at the snubber circuit. The overshoot is reduced from over 70% to less than 5%, and the ringing is eliminated by the snubber. Optimum values for RS and CS are determined experimentally. VS = 2.5V AV = 1 RL = 10k RS = 90 CL = 1000pF CS = 700pF 5000 4500 4000 INPUT BIAS CURRENT (pA) 3500 3000 2500 3mW/cm2 2mW/cm2 2000 1500 1000 500 0 350 450 550 650 WAVELENGTH (nm) 750 02731-050 VOLTAGE (100mV/DIV) 1mW/cm2 850 02731-048 Figure 50. AD8605ACB Input Bias Current Response to Direct Illumination of Varying Intensity and Wavelength TIME (10s/DIV) Figure 49. Capacitive Load Drive with Snubber Table 5 summarizes a few optimum values for capacitive loads. Table 5. CL (pF) 500 1000 2000 RS () 100 70 60 CS (pF) 1000 1000 800 An alternate technique is to insert a series resistor inside the feedback loop at the output of the amplifier. Typically, the value of this resistor is approximately 100 . This method also reduces overshoot and ringing but causes a reduction in the maximum output swing. LIGHT SENSITIVITY The AD8605ACB (WLCSP package option) is essentially a silicon die with additional postfabrication dielectric and intermetallic processing designed to contact solder bumps on the active side of the chip. With this package type, the die is exposed to ambient light and is subject to photoelectric effects. Light sensitivity analysis of the AD8605ACB mounted on standard PCB material reveals that only the input bias current (IB) parameter is impacted when the package is illuminated directly by high intensity light. No degradation in electrical performance is observed due to illumination by low intensity (0.1 mW/cm2) ambient light. Figure 50 shows that IB increases with increasing wavelength and intensity of incident light; IB can reach levels as high as 4500 pA at a light intensity of 3 mW/cm2 and a wavelength of 850 nm. The light intensities shown in Figure 50 are not normal for most applications, that is, even though direct sunlight can have intensities of 50 mW/cm2, office ambient light can be as low as 0.1 mW/cm2. When the WLCSP package is assembled on the board with the bump side of the die facing the PCB, reflected light from the PCB surface is incident on active silicon circuit areas and results in the increased IB. No performance degradation occurs due to illumination of the backside (substrate) of the AD8605ACB. The AD8605ACB is particularly sensitive to incident light with wavelengths in the near infrared range (NIR, 700 nm to 1000 nm). Photons in this waveband have a longer wavelength and lower energy than photons in the visible (400 nm to 700 nm) and near ultraviolet (NUV, 200 nm to 400 nm) bands; therefore, they can penetrate more deeply into the active silicon. Incident light with wavelengths greater than 1100 nm has no photoelectric effect on the AD8605ACB because silicon is transparent to wavelengths in this range. The spectral content of conventional light sources varies. Sunlight has a broad spectral range, with peak intensity in the visible band that falls off in the NUV and NIR bands; fluorescent lamps have significant peaks in the visible but not the NUV or NIR bands. Efforts have been made at a product level to reduce the effect of ambient light; the under bump metal (UBM) has been designed to shield the sensitive circuit areas on the active side (bump side) of the die. However, if an application encounters any light sensitivity with the AD8605ACB, shielding the bump side of the WLCSP package with opaque material should eliminate this effect. Shielding can be accomplished using materials such as silica-filled liquid epoxies that are used in flip-chip underfill techniques. WLCSP ASSEMBLY CONSIDERATIONS For detailed information on the WLCSP PCB assembly and reliability, see Application Note AN-617, MicroCSPTM Wafer Level Chip Scale Package. Rev. H | Page 17 of 24 AD8605/AD8606/AD8608 I-V CONVERSION APPLICATIONS PHOTODIODE PREAMPLIFIER APPLICATIONS The low offset voltage and input current of the AD8605 make it an excellent choice for photodiode applications. In addition, the low voltage and current noise make the amplifier ideal for application circuits with high sensitivity. CF 10pF RF 10M At room temperature, the AD8605 has an input bias current of 0.2 pA and an offset voltage of 100 V. Typical values of RD are in the range of 1 G. For the circuit shown in Figure 51, the output error voltage is approximately 100 V at room temperature, increasing to about 1 mV at 85C. The maximum achievable signal bandwidth is f MAX = ft 2R F C F PHOTODIODE VOS CD 50pF where ft is the unity gain frequency of the amplifier. AD8605 VOUT 02731-051 RD ID AUDIO AND PDA APPLICATIONS The low distortion and wide dynamic range of the AD860x make it a great choice for audio and PDA applications, including microphone amplification and line output buffering. Figure 52 shows a typical application circuit for headphone/ line-out amplification. R1 and R2 are used to bias the input voltage at half the supply, which maximizes the signal bandwidth range. C1 and C2 are used to ac couple the input signal. C1, R1, and R2 form a highpass filter whose corner frequency is 1/[2(R1||R2)C1]. The high output current of the AD8606 allows it to drive heavy resistive loads. The circuit in Figure 52 is tested to drive a 16 headphone. The THD + N is maintained at approximately -60 dB throughout the audio range. 5V Figure 51. Equivalent Circuit for Photodiode Preamp The input bias current of the amplifier contributes an error term that is proportional to the value of RF. The offset voltage causes a dark current induced by the shunt resistance of the Diode RD. These error terms are combined at the output of the amplifier. The error voltage is written as R E O = VOS 1 + F R D + RF I B Typically, RF is smaller than RD, thus RF/RD can be ignored. C1 1F R1 20k 3 8 R2 V1 20k 500mV 1/2 AD8606 4 C3 100F 1 R4 20 R3 HEADPHONES 1k 2 5V C2 1F R7 20k 5 8 R8 V2 500mV 20k 1/2 AD8606 4 C4 100F 7 R6 20 R5 1k 6 Figure 52. Single-Supply Headphone/Speaker Amplifier Rev. H | Page 18 of 24 02731-052 AD8605/AD8606/AD8608 INSTRUMENTATION AMPLIFIERS The low offset voltage and low noise of the AD8605 make it an ideal amplifier for instrumentation applications. Difference amplifiers are widely used in high accuracy circuits to improve the common-mode rejection ratio. Figure 53 shows a simple difference amplifier. Figure 54 shows the commonmode rejection for a unity gain configuration and for a gain of 10. Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields a CMRR of 74 dB and minimizes the gain error at the output. V1 R1 1k 5V R4 R2 = R3 R1 VOUT = R2 (V2 - V1) R1 R2 10k VREF R R R CF RF R2 R2 R2 VOS V+ AD8605 V- Figure 55. Simplified Circuit of the DAC8143 with AD8605 Output Buffer AD8605 VOUT 02731-053 V2 R3 1k R4 10k To optimize the performance of the DAC, insert a capacitor in the feedback loop of the AD8605 to compensate the amplifier for the pole introduced by the output capacitance of the DAC. Typical values for CF range from 10 pF to 30 pF; it can be adjusted for the best frequency response. The total error at the output of the op amp can be computed by Figure 53. Difference Amplifier, AV = 10 120 VSY = 2.5V 100 AV = 10 R E O = VOS 1 + F Req 80 CMRR (dB) AV = 1 where Req is the equivalent resistance seen at the output of the DAC. As previously mentioned, Req is code dependent and varies with the input. A typical value for Req is 15 k. Choosing a feedback resistor of 10 k yields an error of less than 200 V. Figure 56 shows the implementation of a dual-stage buffer at the output of a DAC. The first stage is used as a buffer. Capacitor C1 with Req creates a low-pass filter, and thus, provides phase lead to compensate for frequency response. The second stage of the AD8606 is used to provide voltage gain at the output of the buffer. Grounding the positive input terminals in both stages reduces errors due to the common-mode output voltage. Choosing R1, R2, and R3 to match within 0.01% yields a CMRR of 74 dB and maintains minimum gain error in the circuit. 60 40 20 02731-054 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 54. Difference Amplifier CMRR vs. Frequency DAC CONVERSION The low input bias current and offset voltage of the AD8605 make it an excellent choice for buffering the output of a current output DAC. Figure 55 shows a typical implementation of the AD8605 at the output of a 12-bit DAC. The DAC8143 output current is converted to a voltage by the feedback resistor. The equivalent resistance at the output of the DAC varies with the input code, as does the output capacitance. 15V RCS C1 33pF R3 20k R2 10k R1 10k VDD VREF RFB OUT1 AGND DB11 AD7545 VOUT VIN RP 1/2 AD8606 R4 5k 1/2 AD8606 02731-056 Figure 56. Bipolar Operation Rev. H | Page 19 of 24 02731-055 AD8605/AD8606/AD8608 OUTLINE DIMENSIONS 0.94 0.90 0.86 0.37 0.36 0.35 0.50 REF SEATING PLANE 0.87 BALL 1 IDENTIFIER 1.33 1.29 1.25 0.23 0.18 0.14 0.21 0.50 2 1 A B C TOP VIEW (BALL SIDE DOWN) 0.17 0.14 0.12 0.50 BOTTOM VIEW (BALL SIDE UP) 0.20 101607-A Figure 57. 5-Ball Wafer Level Chip Scale Package [WLCSP] (CB-5-1) Dimensions shown in millimeters 2.90 BSC 5 4 1.60 BSC 1 2 3 2.80 BSC PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC 1.45 MAX 0.22 0.08 10 5 0 0.60 0.45 0.30 0.15 MAX 0.50 0.30 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178-A A Figure 58. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 3.20 3.00 2.80 3.20 3.00 2.80 PIN 1 8 5 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 59. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. H | Page 20 of 24 AD8605/AD8606/AD8608 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 1 5 4 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45 0.51 (0.0201) 0.31 (0.0122) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 60. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 1.480 1.430 1.380 0.675 0.595 0.515 SEATING PLANE 3 2 1 012407-A BALL 1 IDENTIFIER 1.825 1.775 1.725 0.340 0.320 0.300 A B 0.50 BALL PITCH TOP VIEW (BALL SIDE DOWN) C Figure 61. 8-Ball Wafer Level Chip Scale Package [WLCSP] (CB-8-1) Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 14 1 8 7 4.00 (0.1575) 3.80 (0.1496) 6.20 (0.2441) 5.80 (0.2283) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45 COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 62. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. H | Page 21 of 24 060606-A 090706-B 0.380 0.355 0.330 BOTTOM VIEW 0.27 0.24 0.21 (BALL SIDE UP) AD8605/AD8606/AD8608 5.10 5.00 4.90 14 8 4.50 4.40 4.30 1 7 6.40 BSC PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 SEATING COPLANARITY PLANE 0.10 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 63. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model AD8605ACB-REEL AD8605ACB-REEL7 AD8605ACBZ-REEL1 AD8605ACBZ-REEL71 AD8605ART-R2 AD8605ART-REEL AD8605ART-REEL7 AD8605ARTZ-R2 1 AD8605ARTZ-REEL1 AD8605ARTZ-REEL71 AD8606ARM-R2 AD8606ARM-REEL AD8606ARMZ-R21 AD8606ARMZ-REEL1 AD8606AR AD8606AR-REEL AD8606AR-REEL7 AD8606ARZ1 AD8606ARZ-REEL1 AD8606ARZ-REEL71 AD8606ACBZ-REEL1 AD8606ACBZ-REEL71 AD8608AR AD8608AR-REEL AD8608AR-REEL7 AD8608ARZ1 AD8608ARZ-REEL1 AD8608ARZ-REEL71 AD8608ARU AD8608ARU-REEL AD8608ARUZ1 AD8608ARUZ-REEL1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 5-Ball WLCSP 5-Ball WLCSP 5-Ball WLCSP 5-Ball WLCSP 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 5-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Ball WLCSP 8-Ball WLCSP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Package Option CB-5-1 CB-5-1 CB-5-1 CB-5-1 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 RJ-5 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 CB-8-1 CB-8-1 R-14 R-14 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14 Branding B3A B3A A1J A1J B3A B3A B3A B3A# B3A# B3A# B6A B6A B6A# B6A# B6A# B6A# Z = RoHS Compliant Part, # denotes RoHS compliant (except for CB-5-1). Product may be top or bottom marked. Rev. H | Page 22 of 24 AD8605/AD8606/AD8608 NOTES Rev. H | Page 23 of 24 AD8605/AD8606/AD8608 NOTES (c)2002-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02731-0-2/08(H) Rev. H | Page 24 of 24 |
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