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LOW SKEW, 1-TO-4, CRYSTAL-TOLVCMOS/LVTTL FANOUT BUFFER
ICS83904-02
GENERAL DESCRIPTION
The ICS83904-02 is a low skew, high perforIC S mance 1-to-4 Crystal Oscillator/Crystal-to-LVCMOS HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS83904-02 has selectable single-ended clock or two crystal-oscillator inputs. There is an output enable to disable the outputs by placing them into a high-impedance state. Guaranteed output and par t-to-par t skew characteristics make the ICS83904-02 ideal for those applications demanding well defined performance and repeatability.
FEATURES
* Four LVCMOS/LVTTL outputs, 19 typical output impedance @ VDD = VDDO = 3.3V * Two Crystal oscillator input pairs One LVCMOS/LVTTL clock input * Crystal input frequencry range: 12MHz - 38.88MHz * Output frequency: 200MHz (maximum) * Output Skew: 40ps (maximum) @ VDD = VDDO = 3.3V * RMS phase jitter @ 25MHz output, using a 25MHz crystal (100Hz - 1MHz): 0.16ps (typical) @ VDD = VDDO = 3.3V * RMS phase noise at 25MHz: Offset Noise Power 100Hz ............. -118.4 dBc/Hz 1kHz ............. -141.5 dBc/Hz 10kHz ............. -157.2 dBc/Hz 100kHz ............. -157.2 dBc/Hz * Supply Voltage Modes: (Core/Output) 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V
BLOCK DIAGRAM
OE CLK_SEL0 Pullup Pulldown
* 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
CLK_SEL1 Pulldown
XTAL_IN0
PIN ASSIGNMENT
OSC
00
Q0 CLK_SEL0 XTAL_OUT0 XTAL_IN0 VDD XTAL_IN1 XTAL_OUT1 CLK_SEL1 CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDDO Q0 Q1 GND Q2 Q3 VDDO OE
XTAL_OUT0
Q1
XTAL_IN1
OSC
01
Q2
XTAL_OUT1
ICS83904-02
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
CLK
Pulldown
10 11
Q3
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TABLE 1. PIN DESCRIPTIONS
Number 1, 7 2, 3 4 5, 6 8 9 10, 16 11, 12, 14, 15 13 Name CLK_SEL0, CLK_SEL1 XTAL_OUT0, XTAL_IN0 VDD XTAL_IN1, XTAL_OUT1 CLK OE VDDO Q3, Q2, Q1, Q0 GN D Type Input Input Power Input Input Input Power Output Power Description Clock select inputs. See Table 3, Input Reference Function Table. Pulldown LVCMOS / LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output. Positive supply pin. Cr ystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output. Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. When LOW, outputs are in HIGH impedance state. Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Output supply pins. Single-ended clock outputs. LVCMOS/LVTTL interface levels. Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) VDDO = 3.465V VDDO = 2.625V VDDO = 2.0V VDDO = 3.3V ROUT Output Impedance VDDO = 2.5V VDDO = 1.8V Test Conditions Minimum Typical 4 51 51 8 7 7 19 21 32 Maximum Units pF k k pF pF pF
TABLE 3. INPUT REFERENCE FUNCTION TABLE
Control Inputs CLK_SEL1 CLK_SEL0 0 0 0 1 1 1 0 1 Reference XTAL0 (default) XTAL1 CLK CLK
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 100.3C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Power Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current No Load & XTALx selected @ 12MHz No Load & CLK selected No Load & CLK selected Test Conditions Minimum 3.135 3.135 Typical 3.3 3. 3 Maximum 3.465 3.465 7 1 1 Units V V mA mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO I DD IDDO Parameter Power Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current No Load & XTALx selected @ 12MHz No Load & CLK selected No Load & CLK selected Test Conditions Minimum 3.135 2.375 Typical 3. 3 2. 5 Maximum 3.465 2.625 7 1 1 Units V V mA mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol V DD VDDO IDD IDDO Parameter Power Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current No Load & XTALx selected @ 12MHz No Load & CLK selected No Load & CLK selected Test Conditions Minimum 3.135 1.6 Typical 3. 3 1.8 Maximum 3.465 2.0 7 1 1 Units V V mA mA mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol V DD VDDO I DD IDDO Parameter Power Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current No Load & XTALx selected @ 12MHz No Load & CLK selected No Load & CLK selected Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 3 1 1 Units V V mA mA mA
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TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Power Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current No Load & XTALx selected @ 12MHz No Load & CLK selected No Load & CLK selected Test Conditions Minimum 2.375 1.6 Typical 2. 5 1.8 Maximum 2.625 2.0 3 1 1 Units V V mA mA mA
TABLE 4F. DC CHARACTERISTICS, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage CLK, CLK_SEL0:1 OE CLK, CLK_SEL0:1 OE Test Conditions VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V 5% VDD = 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDD = 3.3V or 2.5V 5% VDDO = 3.3V 5%; NOTE 1 VOH Output HighVoltage VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 VDDO = 3.3V 5%; NOTE 1 VOL Output Low Voltage VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 -5 -150 2.6 1.8 1.2 0.6 0.5 0. 4 Minimum 2.2 1.6 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 1.3 0.9 150 5 Units V V V V A A A A V V V V V V
Input High Current
IIL
Input Low Current
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 12 Test Conditions Minimum Typical Maximum 38.88 50 7 1 Units MHz pF mW Fundamental
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TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = 0C TO 70C
Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(O) t R / tF odc tEN w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Output Duty Cycle w/external XTAL w/external CLK < 150MHz 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% Output Frequency w/external XTAL Test Conditions Minimum 12 Typical Maximum 38.88 200 1.4 1.9 2.4 40 700 0.16 100 45 46 800 55 54 10 10 Units MHz MHz ns ps ps ps ps % % ns ns
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0C TO 70C
Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(O) t R / tF odc tEN w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Output Duty Cycle w/external XTAL w/external CLK < 150MHz 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% Output Frequency w/external XTAL Test Conditions Minimum 12 Typical Maximum 38.88 200 1.5 2.0 2.5 40 700 0.16 100 45 46 800 55 54 10 10 Units MHz MHz ns ps ps ps ps % % ns ns
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
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TABLE 6C. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(O) t R / tF odc tEN w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Output Duty Cycle w/external XTAL w/external CLK < 150MHz 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% Output Frequency w/external XTAL Test Conditions Minimum 12 Typical Maximum 38.88 200 1.7 2.2 2.7 40 700 0.16 100 45 46 1000 55 54 10 10 Units MHz MHz ns ps ps ps ps % % ns ns
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6D. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = 0C TO 70C
Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(O) t R / tF odc tEN w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Output Duty Cycle w/external XTAL w/external CLK < 150MHz 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% Output Frequency w/external XTAL Test Conditions Minimum 12 Typical Maximum 38.88 200 1.5 2.2 3.0 40 700 0.20 100 45 48 800 55 52 10 10 Units MHz MHz ns ps ps ps ps % % ns ns
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
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TABLE 6E. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter fMAX tpLH t sk(o) t sk(pp) t jit(O) t R / tF odc tEN w/external CLK Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2 Par t-to-Par t Skew; NOTE 2, 3 RMS Phase Jitter, Random; NOTE 2, 4 Output Rise/Fall Time Output Duty Cycle w/external XTAL w/external CLK < 150MHz 25MHz, Integration Range: 100Hz - 1MHz 20% to 80% Output Frequency w/external XTAL Test Conditions Minimum 12 Typical Maximum 38.88 200 1.7 2.5 3.3 40 700 0.19 100 45 46 1000 55 54 10 10 Units MHz MHz ns ps ps ps ps % % ns ns
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5 tDIS NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
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TYPICAL PHASE NOISE AT 25MHZ
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M
25MHz
RMS Phase Jitter (Random) 100Hz to 1MHz = 0.16ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
OFFSET FREQUENCY (HZ)
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PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO
Qx
SCOPE
VDD, VDDO
Qx
SCOPE
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V5% 1.25V5%
2.4V0.065V 0.9V0.1V
VDD VDDO
GND Qx
SCOPE
VDD VDDO
GND Qx
SCOPE
LVCMOS
LVCMOS
-1.25V5%
-0.9V0.1V
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.6V0.025V 0.9V0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
Part 1 VDD VDDO
GND Qx
SCOPE
V
DDO
Qx
2
Part 2 Qy
V
DDO
LVCMOS
2 tsk(pp)
-0.9V0.1V
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
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V
DDO
Qx
2
VDD
VDD 2 VDDO VDDO 2 tpHL
CLK
V
DDO
2
Qy
2 tsk(o)
Q0:Q3
2 tpLH
OUTPUT SKEW
PROPAGATION DELAY
V
DDO
Q0:Q3 t PW
t
2
80%
PERIOD
80% 20%
odc =
t PW t PERIOD
x 100%
Clock Outputs
20% tR tF
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
Figure 1 shows an example of ICS83904-02 crystal interface with a parallel resonant crystal. The frequency accuracy can be fine tuned by adjusting the C1 and C2 values. For a parallel crystal with loading capacitance CL = 18pF, we suggest C1 = 15pF and C2 = 15pF to start with. These values may be slightly fine tuned further to optimize the frequency accuracy for different board layouts. Slightly increasing the C1 and C2 values will slightly reduce the frequency. Slightly decreasing the C1 and C2 values will slightly increase the frequency. For the oscillator circuit below, R1 can be used, but is not required. For new designs, it is recommended that R1 not be used.
XTAL_IN C1 15p X1 18pF Parallel Cry stal 0 XTAL_OUT C2 15p R1 (optional)
FIGURE 1. Crystal Input Interface
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 2. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 2. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT For applications not requiring the use of the clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. SELECT PINS All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached.
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RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 100.3C/W
1
96.0C/W
2.5
93.9C/W
TRANSISTOR COUNT
The transistor count for ICS83904-02 is: 205
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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TABLE 9. ORDERING INFORMATION
Part/Order Number ICS83904AG-02 ICS83904AG-02T ICS83904AG-02LF ICS83904AG-02LFT Marking 83904A02 83904A02 3904A02L 3904A02L Package 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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