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| 74LVC1G99 Ultra-configurable multiple function gate; 3-state Rev. 01 -- 3 January 2008 Product data sheet 1. General description The 74LVC1G99 provides a low voltage, ultra-configurable, multiple function gate with 3-state output. The device can be configured as one of several logic functions including, AND, OR, NAND, NOR, XOR, XNOR, inverter, buffer and MUX. No external components are required to configure the device as all inputs can be connected directly to VCC or GND. The 3-state output is controlled by the output enable input (OE). A HIGH level at OE causes the output (Y) to assume a high-impedance OFF-state. When OE is LOW, the output state is determined by the signals applied to the Schmitt-trigger inputs (A, B, C and D). Due to the use of Schmitt-trigger inputs the device is tolerant of slowly changing input signals, transforming them into sharply defined, jitter free output signals. By eliminating leakage current paths to VCC and GND, the inputs and disabled output are also over-voltage tolerant, making the device suitable for mixed-voltage applications. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G99 is fully specified over the supply range from 1.65 V to 5.5 V. 2. Features I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C. I I I I I I I I NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC1G99DP 74LVC1G99GT 74LVC1G99GM -40 C to +125 C -40 C to +125 C -40 C to +125 C TSSOP8 XSON8 XQFN8U Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 x 1.95 x 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 4. Marking Table 2. Marking Marking code V99 V99 V99 Type number 74LVC1G99DP 74LVC1G99GT 74LVC1G99GM 5. Functional diagram OE A B Y C D 001aah322 Fig 1. Logic symbol 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 2 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 6. Pinning information 6.1 Pinning 74LVC1G99 OE A B GND 1 2 3 4 001aah323 8 7 6 5 VCC Y D C Fig 2. Pin configuration SOT505-2 (TSSOP8) 74LVC1G99 74LVC1G99 OE 1 8 VCC terminal 1 index area Y 1 VCC 8 7 OE A 2 7 Y D 2 6 A B 3 6 D C 3 4 5 B GND GND 4 5 C 001aah325 001aah324 Transparent top view Transparent top view Fig 3. Pin configuration SOT833-1 (XSON8) Fig 4. Pin configuration SOT902-1 (XQFN8U) 6.2 Pin description Table 3. Symbol Pin description Pin SOT505-2 and SOT833-1 OE A B GND C D Y VCC 1 2 3 4 5 6 7 8 SOT902-1 7 6 5 4 3 2 1 8 output enable input OE (active LOW) data input data input ground (0 V) data input data input data output supply voltage Description 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 3 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 7. Functional description Table 4. Input OE L L L L L L L L L L L L L L L L H [1] Function table [1] Output D L L L L L L L L H H H H H H H H X C L L L L H H H H L L L L H H H H X B L L H H L L H H L L H H L L H H X A L H L H L H L H L H L H L H L H X Y L H L H L L H H H L H L H H L L Z H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 4 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 7.1 Logic configurations Table 5. Function selection table Complementary function Primary function 3-state buffer 3-state inverter 3-state 2-input multiplexer 3-state 2-input multiplexer with inverting output 3-state 2-input AND 3-state 2-input AND with one inverting input 3-state 2-input AND with two inverting inputs 3-state 2-input NAND 3-state 2-input NAND with one inverting input 3-state 2-input NAND with two inverting inputs 3-state 2-input XOR 3-state 2-input XNOR 3-state 2-input XOR with one inverting input 3-state 2-input NOR with two inverting inputs 3-state 2-input NOR with one inverting input 3-state 2-input NOR 3-state 2-input OR with two inverting inputs 3-state 2-input OR with one inverting input 3-state 2-input OR 7.2 3-state buffer functions available Table 6. Function table [1] See Figure 5. Function 3-state buffer Input OE L L L L L L L [1] H = HIGH voltage level; L = LOW voltage level. A input H or L L H H H or L L B H or L input H L H or L L L C L H input input L H H or L D L L L H input input input OE input Y 001aah326 Fig 5. 3-state buffer function 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 5 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 7.3 3-state inverter functions available Table 7. Function table [1] See Figure 6. Function 3-state inverter Input OE L L L L L L L [1] H = HIGH voltage level; L = LOW voltage level. X = don't care. A input X L H H H or L H B H or L input H L H or L H H C L H input input L H H or L D H H H L input input input OE input Y 001aah327 Fig 6. 3-state inverter function 7.4 3-state multiplexer functions available Table 8. Function table [1] See Figure 7. Function 3-state 2-input multiplexer Input OE L L L L [1] H = HIGH voltage level; L = LOW voltage level. A input 1 input 2 input 1 input 2 B input 2 input 1 input 2 input 1 C input 1 or input 2 input 2 or input 1 input 1 or input 2 input 2 or input 1 D L L H H OE input 1 Y input 2 A/B OE input 1 Y input 2 A/B 001aah328 Fig 7. 3-state 2-input multiplexer function 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 6 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 7.5 3-state AND/NOR functions available Table 9. Function table [1] See Figure 8. Number of inputs Function AND/NAND 2 2 [1] Input OR/NOR 3-state NOR 3-state NOR OE L L A L L B input 1 input 2 C input 2 input 1 D L L 3-state AND 3-state AND H = HIGH voltage level; L = LOW voltage level. OE OE input 1 Y input 2 input 1 Y input 2 001aah329 Fig 8. 3-state AND/NOR function Table 10. Function table [1] See Figure 9. Number of inputs Function AND/NAND 2 2 [1] Input OR/NOR 3-state NOR 3-state NOR OE L L A input 2 H B L input 1 C input 1 input 2 D L H 3-state AND 3-state AND H = HIGH voltage level; L = LOW voltage level. OE OE input 1 Y input 2 input 1 Y input 2 001aah330 Fig 9. 3-state AND/NOR function 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 7 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state Table 11. Function table [1] See Figure 10. Number of inputs Function AND/NAND 2 2 [1] Input OR/NOR 3-state NOR 3-state NOR OE L L A input 1 H B L input 2 C input 2 input 1 D L H 3-state AND 3-state AND H = HIGH voltage level; L = LOW voltage level. OE OE input 1 Y input 2 input 1 Y input 2 001aah331 Fig 10. 3-state AND/NOR function Table 12. Function table [1] See Figure 11. Number of inputs Function AND/NAND 2 2 [1] Input OR/NOR 3-state NOR 3-state NOR OE L L A input 1 input 2 B H H C input 2 input 1 D L L 3-state AND 3-state AND H = HIGH voltage level; L = LOW voltage level. OE OE input 1 Y input 2 input 1 Y input 2 001aah332 Fig 11. 3-state AND/NOR function 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 8 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 7.6 3-state NAND/OR functions available Table 13. Function table [1] See Figure 12. Number of inputs Function AND/NAND 2 2 [1] Input OR/NOR 3-state OR 3-state OR OE L L A L L B input 1 input 2 C input 2 input 1 D H H 3-state NAND 3-state NAND H = HIGH voltage level; L = LOW voltage level. OE OE input 1 Y input 2 input 1 Y input 2 001aah333 Fig 12. 3-state NAND/OR function Table 14. Function table [1] See Figure 13. Number of inputs Function AND/NAND 2 2 [1] Input OR/NOR 3-state OR 3-state OR OE L L A input 2 H B L input 1 C input 1 input 2 D H L 3-state NAND 3-state NAND H = HIGH voltage level; L = LOW voltage level. OE OE input 1 Y input 2 input 1 Y input 2 001aah334 Fig 13. 3-state AND/NOR function 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 9 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state Table 15. Function table [1] See Figure 14. Number of inputs Function AND/NAND 2 2 [1] Input OR/NOR 3-state OR 3-state OR OE L L A input 1 H B L input 2 C input 2 input 1 D H L 3-state NAND 3-state NAND H = HIGH voltage level; L = LOW voltage level. OE OE input 1 Y input 2 input 1 Y input 2 001aah335 Fig 14. 3-state AND/NOR function Table 16. Function table [1] See Figure 15. Number of inputs Function AND/NAND 2 2 [1] Input OR/NOR 3-state OR 3-state OR OE L L A input 1 input 2 B H H C input 2 input 1 D L L 3-state NAND 3-state NAND H = HIGH voltage level; L = LOW voltage level. OE OE input 1 Y input 2 input 1 Y input 2 001aah336 Fig 15. 3-state AND/NOR function 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 10 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 7.7 3-state XOR/XNOR functions available Table 17. Function table [1] See Figure 16. Function 3-state XOR Input OE L L L L L L [1] H = HIGH voltage level; L = LOW voltage level. A input 1 input 2 H or L H or L L L B H or L H or L input 1 input 2 H H C L L H H input 1 input 2 D input 2 input 1 input 2 input 1 input 2 input 1 OE input 1 Y input 2 001aah337 Fig 16. 3-state XOR function Table 18. Function table [1] See Figure 17. Function 3-state XOR [1] Input OE L A H B L C input 1 D input 2 H = HIGH voltage level; L = LOW voltage level. OE input 1 Y input 2 001aah338 Fig 17. 3-state XOR function 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 11 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state Table 19. Function table [1] See Figure 18. Function 3-state XOR [1] Input OE L A H B L C input 1 D input 2 H = HIGH voltage level; L = LOW voltage level. OE input 1 Y input 2 001aah339 Fig 18. 3-state XOR function Table 20. Function table [1] See Figure 19. Function 3-state XNOR Input OE L L [1] H = HIGH voltage level; L = LOW voltage level. A H H B L L C input 1 input 2 D input 2 input 1 OE input 1 Y input 2 001aah340 Fig 19. 3-state XNOR function 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 12 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 8. Limiting values Table 21. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Ptot Tstg [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current total power dissipation storage temperature Conditions VI < 0 V [1] Min -0.5 -50 -0.5 [1][2] [1][2] Max +6.5 +6.5 50 VCC + 0.5 +6.5 50 100 250 +150 Unit V mA V mA V V mA mA mA mW C VO > VCC or VO < 0 V Active mode Power-down mode VO = 0 V to VCC -0.5 -0.5 -100 Tamb = -40 C to +125 C [3] -65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. For TSSOP8 package: above 110 C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 and XQFN8U packages: above 45 C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 22. Symbol VCC VI VO Tamb t/V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 4.5 V VCC = 4.5 V to 5.5 V Active mode Power-down mode; VCC = 0 V Conditions Min 1.65 0 0 0 -40 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 5 Unit V V V V C ns/V ns/V ns/V 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 13 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 10. Static characteristics Table 23. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +85 C VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II IOZ IOFF ICC ICC CI VOH input leakage current OFF-state output current power-off leakage current supply current additional supply current input capacitance HIGH-level output voltage VCC = 0 V to 5.5 V; VI = 5.5 V or GND VCC = 3.6 V; VI = VIH or VIL; VO = 5.5 V or GND VCC = 0 V; VI or VO = 5.5 V VCC = 1.65 V to 5.5 V; VI = 5.5 V or GND; IO = 0 A per pin; VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A VCC = 3.3 V; VI = GND to VCC VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V 74LVC1G99_1 Conditions Min Typ[1] Max Unit VCC - 0.1 1.2 1.9 2.2 2.3 3.8 - 0.1 0.1 0.1 0.1 5 2.5 0.1 0.45 0.3 0.4 0.55 0.55 5 10 10 10 500 - V V V V V V V V V V V V A A A A A pF Tamb = -40 C to +125 C VCC - 0.1 0.95 1.7 1.9 2.0 3.4 0.1 0.70 0.45 0.60 0.80 0.80 V V V V V V V V V V V V (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 14 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state Table 23. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter II IOZ IOFF ICC ICC input leakage current OFF-state output current power-off leakage current supply current additional supply current Conditions VCC = 0 V to 5.5 V; VI = 5.5 V or GND VCC = 3.6 V; VI = VIH or VIL; VO = 5.5 V or GND VCC = 0 V; VI or VO = 5.5 V VCC = 1.65 V to 5.5 V; VI = 5.5 V or GND; IO = 0 A per pin; VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A Min Typ[1] Max 100 200 200 200 5000 Unit A A A A A [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 11. Dynamic characteristics Table 24. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22. Symbol Parameter Conditions Min tpd propagation delay A to Y; see Figure 20 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V B to Y; see Figure 20 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V C to Y; see Figure 20 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V D to Y; see Figure 20 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 74LVC1G99_1 25 C Typ[1] Max -40 C to +125 C Min Max Max (85 C) (125 C) 30.8 11.7 9.0 8.4 5.5 28.9 11.3 9.0 8.2 5.4 29.8 12.3 9.6 8.6 5.7 25.7 10.7 9.2 7.6 5.2 38.5 14.6 11.3 10.5 6.9 36.2 14.2 11.3 10.3 6.8 37.3 15.4 12.0 10.8 7.2 32.2 13.4 11.5 9.5 6.5 Unit [2] [2] 7.5 5.0 5.4 4.5 3.8 7.5 5.0 5.4 4.5 3.8 7.8 5.2 5.3 4.6 3.8 7.0 4.6 4.8 4.1 3.4 - 2.8 2.0 2.0 1.8 1.8 2.8 2.0 2.0 1.8 1.8 3.2 2.3 2.3 2.3 1.8 2.8 2.0 2.0 1.8 1.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns [2] [2] - (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 15 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state Table 24. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22. Symbol Parameter Conditions Min ten enable time OE to Y; see Figure 21 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tdis disable time OE to Y; see Figure 21 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance per buffer (output enabled); fi = 10 MHz; CL = 50 pF; VI = GND to VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V [1] [2] [3] [4] [5] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs. [5] [4] [3] 25 C Typ[1] Max -40 C to +125 C Min Max Max (85 C) (125 C) 25.2 11.3 8.6 7.0 4.7 15.0 5.8 6.6 5.9 4.5 32.0 14.0 11.0 9.0 6.0 19.0 7.3 8.2 7.4 5.6 Unit - 5.7 3.8 4.2 3.5 2.7 5.7 3.6 4.5 4.5 3.4 - 2.0 1.4 1.4 1.4 1.4 3.0 2.0 2.0 2.1 1.0 ns ns ns ns ns ns ns ns ns ns - 14 16 18 25 30 - - - - pF pF pF pF pF 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 16 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 12. Waveforms VI A, B, C, D input GND tPHL VOH Y output VOL tPLH VOH Y output VOL VM VM 001aah341 VM VM tPLH VM tPHL VM Measurement points are given in Table 25. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 20. The data input (A, B, C, D) to output (Y) propagation delays VI OE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled mna644 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 25. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 21. 3-state enable and disable times Table 25. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V 74LVC1G99_1 Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.15 V VOH - 0.15 V VOH - 0.3 V VOH - 0.3 V VOH - 0.3 V (c) NXP B.V. 2008. All rights reserved. Supply voltage Product data sheet Rev. 01 -- 3 January 2008 17 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 26. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 22. Load circuitry for switching times Table 26. Test data Input VI 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VCC VCC 2.7 V 2.7 V VCC tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 k 500 500 500 500 VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2VCC 2VCC 6V 6V 2VCC Supply voltage 13. Transfer characteristics Table 27. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22 Symbol Parameter VT+ positive-going threshold voltage Conditions see Figure 23, Figure 24, Figure 25, Figure 26 and Figure 27 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V 0.70 1.11 1.50 2.16 2.61 1.02 1.42 1.79 2.52 2.99 1.20 1.60 2.00 2.74 3.33 0.67 1.08 1.47 2.13 2.58 1.20 1.60 2.00 2.74 3.33 V V V V V -40 C to +85 C Min Typ[1] Max -40 C to +125 C Min Max Unit 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 18 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state Table 27. Transfer characteristics ...continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 22 Symbol Parameter VT- negative-going threshold voltage Conditions see Figure 23, Figure 24, Figure 25, Figure 26 and Figure 27 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V VH hysteresis voltage (VT+ - VT-); see Figure 23, Figure 24, Figure 25, Figure 26 and Figure 27 VCC = 1.8 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V [1] All typical values are measured at Tamb = 25 C -40 C to +85 C Min Typ[1] Max -40 C to +125 C Min Max Unit 0.30 0.58 0.80 1.21 1.45 0.53 0.77 1.04 1.55 1.86 0.72 1.00 1.30 1.90 2.29 0.30 0.58 0.80 1.21 1.45 0.75 1.03 1.33 1.93 2.32 V V V V V 0.30 0.40 0.50 0.71 0.71 0.48 0.64 0.75 0.97 1.13 0.62 0.80 1.00 1.20 1.40 0.23 0.34 0.44 0.65 0.65 0.62 0.80 1.00 1.20 1.40 V V V V V 14. Waveforms transfer characteristics VO VT+ VI VT- VH VH VT- VT+ VI mna207 VO mna208 Fig 23. Transfer characteristic Fig 24. Definition of VT+, VT- and VH 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 19 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state VO VI VT+ VT- VH VH VT- VT+ VI mnb154 VO mnb155 Fig 25. Transfer characteristic Fig 26. Definition of VT+, VT- and VH 16 I CC (mA) 12 001aab594 8 4 0 0 1 2 VI (V) 3 Fig 27. Typical 74LVC1G99 transfer characteristic; VCC = 3.0 V 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 20 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 28. Package outline SOT505-2 (TSSOP8) 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 21 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4x L (2) L1 e 8 e1 7 e1 6 e1 5 8x (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 29. Package outline SOT833-1 (XSON8) 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 22 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e v M C A B w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 30. Package outline SOT902-1 (XQFN8U) 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 23 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 16. Abbreviations Table 28. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 17. Revision history Table 29. Revision history Release date 20080103 Data sheet status Product data sheet Change notice Supersedes Document ID 74LVC1G99_1 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 24 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC1G99_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 3 January 2008 25 of 26 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Logic configurations . . . . . . . . . . . . . . . . . . . . . 5 3-state buffer functions available . . . . . . . . . . . 5 3-state inverter functions available . . . . . . . . . . 6 3-state multiplexer functions available . . . . . . . 6 3-state AND/NOR functions available. . . . . . . . 7 3-state NAND/OR functions available. . . . . . . . 9 3-state XOR/XNOR functions available . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Recommended operating conditions. . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 15 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transfer characteristics. . . . . . . . . . . . . . . . . . 18 Waveforms transfer characteristics . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 January 2008 Document identifier: 74LVC1G99_1 |
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