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19-1024; Rev 0; 10/07 DisplayPort to DVI/HDMI Level Shifter General Description The MAX9406 high-speed, low-skew, quad differential input to current-mode logic (CML) translator features high-speed signal conversion of the DisplayPort (DP) to High-Definition Multimedia Interface (HDMITM) technology. This device features ultra-low propagation delay of 350ps and channel-to-channel skew of less than 20ps. The MAX9406 supports typical data rates of 2Gbps. The MAX9406 provides the level shift for HDMI's Display Data Channel (DDC) and hot-plug detection (HPD), which converts the 5V single-ended logic to 3.3V single-ended logic. The MAX9406 operates from a 3V to 3.6V core supply and is specified over the -40C to +85C extended temperature range. This device is available in 48-pin, 7mm x 7mm thin QFN and 32-pin, 5mm x 5mm thin QFN packages. 350ps Propagation Delay 20ps Channel-to-Channel Skew at 2Gbps Low Jitters: DJ = 11psP-P and RJ = 0.5psRMS Bidirectional Level Shifter of 5V to 3.3V for DDC Pins Level Shifter of 5V to 3.3V for I/Os Integrated 50 Input Terminations and Biasing -40C to +85C Operating Temperature Range Features 500mV Differential HDMI Output at 2Gbps Data Rate MAX9406 Applications Level Conversion for DP to HDMI Data and Clock Driver and Buffer Backplane Data and Clock Distribution Base Stations ATE MAX9406ETM+ MAX9406ETJ+ PART Ordering Information TEMP RANGE PIN-PACKAGE 32 Thin QFN-EP* (5mm x 5mm x 0.8mm) 48 Thin QFN-EP* (7mm x 7mm x 0.8mm) PKG CODE T3255-4 -40C to +85C -40C to +85C T4877-6 +Denotes a lead-free package. HDMI is a trademark of HDMI Licensing, LCC. *EP = Exposed paddle. Pin Configurations HPD_SNK SDA_SNK SCL_SNK DDC_EN SDA_SNK GND GND 18 VCC TOP VIEW 24 23 22 21 20 19 GND OUT_D1OUT_D1+ VCC OUT_D2OUT_D2+ GND OUT_D3OUT_D3+ VCC OUT_D4OUT_D4+ SCL_SNK GND GND GND DDC_EN N.C. N.C. VCC VCC TOP VIEW HPD_SNK OE 36 35 34 33 32 31 30 29 28 27 26 25 GND IN_D1IN_D1+ VCC IN_D2IN_D2+ GND IN_D3IN_D3+ VCC IN_D4IN_D4+ 37 38 39 40 41 42 43 44 45 46 47 48 1 GND 2 VCC 3 N.C. 4 N.C. 5 GND 6 N.C. 7 HPD_SRC 8 SDA_SRC 9 SCL_SRC 10 11 12 N.C. VCC GND EP* 24 IN_D1- 25 IN_D1+ 26 IN_D2- 27 IN_D2+ 28 IN_D3- 29 IN_D3+ 30 IN_D4- 31 IN_D4+ 32 1 GND 23 22 21 20 19 17 16 OUT_D115 OUT_D1+ 14 OUT_D213 OUT_D2+ MAX9406 18 17 16 15 MAX9406 OE 12 OUT_D311 OUT_D3+ 10 OUT_D49 OUT_D4+ 8 GND + 2 VCC EP* + 14 13 3 GND 4 HPD_SRC 5 SDA_SRC 6 SCL_SRC 7 VCC 48 TQFN-EP 7mm x 7mm *EP EXPOSED PADDLE. CONNECT EP TO GND. 32 TQFN-EP 5mm x 5mm *EP EXPOSED PADDLE. CONNECT EP TO GND. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. DisplayPort to DVI/HDMI Level Shifter MAX9406 ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.3V to +4V All Pins to GND...........................................-0.3V to (VCC + 0.3V) Short-Circuit Duration (all outputs).............................Continuous Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (derate 21.3mW/C above +70C) .1702mW 48-Pin Thin QFN (derate 27.8mW/C above +70C) .2222mW Junction-to-Case Thermal Resistance (JC) (Note 1) 32-Pin Thin QFN........................................................+1.7C/W 48-Pin Thin QFN........................................................+0.8C/W Junction-to-Ambient Thermal Resistance (JA) (Note 1) 32-Pin Thin QFN.........................................................+29C/W 48-Pin Thin QFN.........................................................+25C/W Operating Temperature Range .......................-40C to +85C Junction Temperature .............................................+150C Storage Temperature Range ........................-65C to +150C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) IN_D_ and OUT_D_ to GND..........................................1.5kV Lead Temperature (soldering, 10s)............................+300C Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer board. For detailed information on package thermal considerations, refer to Application Note 4083 at www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 3V to 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C.) PARAMETER OE INPUT Input High Level Input Low Level Input Current DDC_EN INPUT Input High Level Input Low Level Input Current HPD INPUT AND OUTPUT Input High Level Input Low Level Input Current HPD_SNK Pulldown Resistance Output High Level Output Low Level DIFFERENTIAL INPUTS (IN_) Differential Input High Threshold Differential Input Low Threshold Common Input Voltage Common-Mode AC Tolerance Differential Input Termination VIDH VIDL VCOM RIN VID = VIN+ - VINVID = VIN+ - VINVCOD = DC Avg [(VIN+ + VIN-) / 2] -50 0 40 1.43 2 100 60 50 mV mV V mV VIH2 VIL2 IIN2 RHPD VOH-HPDB VOL-HPDB VIN = 0 to VCC 40 2.5 0 0.18 80 60 VCC 0.4 2.4 5.3 0.8 V V A k V V VIH1 VIL1 IIN-DDC VIN = 0 to VCC 100 2.4 0.5 V V A VIH1 VIL1 IIN-EN VIN = 0 to VCC 24 2.4 0.5 V V A SYMBOL CONDITIONS MIN TYP MAX UNITS VCM_AC_P-P VCM_AC_P-P = (VIN+ + VIN-) / 2 - VCOD 2 _______________________________________________________________________________________ DisplayPort to DVI/HDMI Level Shifter DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 3V to 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C.) PARAMETER DIFFERENTIAL OUTPUTS (OUT_) Single-Ended Output Swing Single-Ended Output High Single-Ended Output Low Single-Ended Output Current in High-Z Output Short-Circuit Current POWER CONSUMPTION Supply Current ICC IPD Includes 4 channels CML termination supply current, OE = 0 OE = 1 77 5 90 mA VOSW VOH3 VOL3 IOFF IOS Output pins connected to VCC or GND With a 50 load to VCC at both pins With a 50 load to VCC at both pins With a 50 load to VCC at both pins 450 VCC 10mV VCC 600mV -10 -20 600 VCC + 10mV VCC 400mV +10 +20 mV mV V A mA SYMBOL CONDITIONS MIN TYP MAX UNITS MAX9406 AC ELECTRICAL CHARACTERISTICS (VCC = 3V to 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C.) (Note 2) PARAMETER DIFFERENTIAL SIGNAL Maximum Data Rate Differential Propagation Delay Channel-to-Channel Skew Output Rise/Fall Time Added Random Jitter Added Deterministic Jitter SINGLE-ENDED SIGNAL CLK Frequency HPD_SRC Rise/Fall Time HPD Propagation Delay fSCK tRF-HPDB tHPD Supports I2C fast mode 1 400 20 200 kHz ns ns rD tPD tSK tR/F tRJ tDJ 1GHz clock input rD = 2Gbps, 223 - 1 PRBS pattern 180 0.5 11 1.85 350 20 500 50 515 1 30 Gbps ps ps ps psRMS psP-P SYMBOL CONDITIONS MIN TYP MAX UNITS Note 2: AC parameters are guaranteed by design and characterization. _______________________________________________________________________________________ 3 DisplayPort to DVI/HDMI Level Shifter MAX9406 Typical Operating Characteristics (VCC = 3.3V, outputs terminated with 50, TA = +25C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9406 toc01 EYE DIAGRAM 1.65Gbps PRBS MAX9406 toc02 85 +85C 84 +25C 83 ICC (mA) 82 -40C 81 80 79 3.0 3.2 VCC (V) 3.4 50mV/div 3.6 200ps/div 4 _______________________________________________________________________________________ DisplayPort to DVI/HDMI Level Shifter Pin Description PIN 32-PIN TQFN 1, 3, 8, 18, 22 48-PIN TQFN 1, 5, 12, 18, 24, 27, 31, 36, 37,43 2, 11, 15, 21, 26, 33, 40, 46 3, 4, 6, 10, 34, 35 7 8 9 13 14 16 17 19 20 22 23 25 28 29 30 32 38 39 41 42 44 45 47 48 -- NAME FUNCTION MAX9406 GND Ground 2, 7, 24 VCC Power-Supply Input. Bypass VCC to GND with 0.1F and 0.01F capacitors as close to the supply pins as possible. No Connection. Not internally connected; leave unconnected. Hot-Plug Detection at 3.3V Logic Serial Data Line. I2C data line at 3.3V logic. Serial Clock Line. I2C clock line at 3.3V logic. Differential Output Port 4+ Differential Output Port 4Differential Output Port 3+ Differential Output Port 3Differential Output Port 2+ Differential Output Port 2Differential Output Port 1+ Differential Output Port 1Output Enable. Drive OE low to enable the outputs. Drive OE high to disable the outputs. Serial Data Line. I2C data line at 5V logic. Serial Clock Line. I2C clock line at 5V logic. Hot-Plug Detection at +5V Logic DDC Link Enable Differential Input Port 1Differential Input Port 1+ Differential Input Port 2Differential Input Port 2+ Differential Input Port 3Differential Input Port 3+ Differential Input Port 4Differential Input Port 4+ Exposed Paddle. Connect EP to ground. -- 4 5 6 9 10 11 12 13 14 15 16 17 19 20 21 23 25 26 27 28 29 30 31 32 -- N.C. HPD_SRC SDA_SRC SCL_SRC OUT_D4+ OUT_D4OUT_D3+ OUT_D3OUT_D2+ OUT_D2OUT_D1+ OUT_D1OE SCL_SNK SDA_SNK HPD_SNK DDC_EN IN_D1IN_D1+ IN_D2IN_D2+ IN_D3IN_D3+ IN_D4IN_D4+ EP _______________________________________________________________________________________ 5 DisplayPort to DVI/HDMI Level Shifter MAX9406 Functional Diagram VCC GND OE DDC_EN High-Speed Signal Enables OE controls the power through the entire length of the four high-speed signal paths. Setting OE low enables all of the high-speed signal paths. Setting OE high disables all high-speed links and disconnects the internal biasing supply and brings the device to the low-power state. In the low-power state, however, the DDC and HPD ports are still functioning. VT 50 x2 IN_D1IN_D1+ VT 50 x2 IN_D2IN_D2+ VT 50 x2 IN_D3IN_D3+ VT 50 x2 IN_D4IN_D4+ SDA_SRC SCK_SRC HPD_SRC DDC LEVEL SHIFTER HPD BUFFER 60k OUT_D4OUT_D4+ SDA_SNK SCK_SNK HPD_SNK OUT_D3OUT_D3+ OUT_D2OUT_D2+ OUT_D1OUT_D1+ Display Data Channel (DDC) The MAX9406 allows the translation between 5V and 3V of the lower speed DDC lines. Whenever one side is pulled to GND, the other side follows and vice versa. DDC_EN controls the gating to the DDC link. Setting DDC_EN high enables data to pass through the DDC, while setting DDC_EN low disables the DDC link. Hot-Plug Detection (HPD) The MAX9406 translates the HPD 5V logic into 3V logic. Applications Information DVI/HDMI Driver The MAX9406 can be used as the driver for the HDMI signal on the motherboard. The MAX9406 CML output provides a > 400mV differential HDMI output and supports 3.3V pullup at the differential outputs. The level shifter boosts the differential signal from the graphics chip to the HDMI connector, located on the edge of the motherboard. High-Speed Signal Line Enable/Disable The MAX9406 allows use of the DDC lines independent of the state of the high-speed signal lines and the OE pin. This allows communication through DDC without any high-speed signals. MAX9406 Detailed Description The MAX9406 high-speed, low-skew, quad differential input to CML translator is designed for high-speed signal conversion of the DP to HDMI technology. This device features ultra-low propagation delay of 350ps and channel-to-channel skew of less than 20ps. The MAX9406 supports typical data rates of 2Gbps. The MAX9406 provides the level shift for HDMI's DDC and HPD, which converts the 5V single-ended logic to 3.3V single-ended logic. Output Termination Terminate CML outputs through 50 to VCC or use an equivalent Thevinin termination. Terminate both outputs and use identical terminations on each for the lowest output-to-output skew. Power-Supply Bypassing Adequate power-supply bypassing is necessary to maximize the performance and noise immunity. Bypass VCC to GND with high-frequency surface-mount 0.01F ceramic capacitors as close to the device as possible. Use multiple bypass vias for connection to minimize inductance. 6 _______________________________________________________________________________________ DisplayPort to DVI/HDMI Level Shifter Printed-Circuit Board (PCB) Traces Input and output trace characteristics affect the performance of the MAX9406. Connect each of the inputs and outputs to a 50 characteristic impedance trace. Avoid discontinuities in differential impedance and maximize common-mode noise immunity by maintaining the distance between differential traces, avoiding sharp corners. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Minimize skew by matching the electrical length of the traces. Exposed Paddle The thin QFN packages used for the MAX9406 have exposed paddles on the bottom. Connect the exposed paddle to ground using a landing pad large enough to accommodate the entire exposed paddle. Add vias from the exposed paddle's land area to a copper polygon on the other side of the PCB to provide lower thermal impedance from the MAX9406 to the ambient air. MAX9406 Chip Information PROCESS: BiPolar _______________________________________________________________________________________ 7 DisplayPort to DVI/HDMI Level Shifter MAX9406 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) E E/2 DETAIL A (NE-1) X e k e D/2 D (ND-1) X e C L D2 D2/2 b L E2/2 k C L E2 C L C L L e e L A1 A2 A PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 F 1 2 8 _______________________________________________________________________________________ 32, 44, 48L QFN.EPS DisplayPort to DVI/HDMI Level Shifter Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX9406 PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 F 2 2 _______________________________________________________________________________________ 9 DisplayPort to DVI/HDMI Level Shifter MAX9406 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 10 ______________________________________________________________________________________ QFN THIN.EPS DisplayPort to DVI/HDMI Level Shifter Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX9406 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. |
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