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| DF6805 8-bit FAST Microcontrollers Family ver 1.04 OVERVIEW Document contains brief description of DF6805 core functionality. The DF6805 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6805 soft core is binary-compatible with the industry standard 68HC05 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two configurations of DF6805: Harvard where data and program buses are separated, and von Neumann with common program and data bus DF6805 has FAST architecture that is 4.1 times faster compared to original implementation. Core in standard configuration has integrated on chip major peripheral function. The DF6805 Microcontroller Core contains full-duplex UART (Asynchronous serial communications interface (SCI), and can also be equipped with the Synchronous Serial Peripheral Interface SPI. The main 16-bit, free-running timer system has implemented two input capture lines and two output-compare lines. Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a nonmaskable interrupt if illegal opcode is detected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve All trademarks mentioned in this document are trademarks of their respective owners. additional power. These modes make the DF6805 IP Core especially attractive for automotive and battery-driven applications. DF6805 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow. CPU FEATURES FAST architecture, 4.1 times faster than the original implementation Software compatible with industry standard 68HC05 Configurable Harvard or Von Neumann architectures 64 bytes of System Function Registers space (SFRs) Up to 64k bytes of Program Memory Up to 64k bytes of Data Memory De-multiplexed Address/Data Bus to allow easy connection to memory Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories Fully synthesizable, static synchronous design with no internal tri-states http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. No internal reset generator or gated clock Scan test ready Technology independent HDL source code Core can be fully customized 1 GHz virtual clock frequency compared to original implementation Dedicated Interrupt vector for each interrupt source Main16-bit timer/counter system 16 bit free running counter Timer clocked by internal source 16-bit Compare/Capture Unit Two independent input-capture functions Two output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring DESIGN FEATURES ONE GLOBAL SYSTEM CLOCK SYNCHRONOUS RESET ALL ASYNCHRONOUS INPUT SIGNALS ARE SYNCHRONIZED BEFORE INTERNAL USE DATA MEMORY: The DF6805 can address up to 64K bytes of Data Memory. The lowest 64 Bytes is reserved for Special Function Registers area. Data Memory can be implemented as synchronous or asynchronous RAM SYSTEM FUNCTION REGISTERS: Full-duplex UART - SCI Standard Nonreturn to Zero format (NRZ) 8 or 9 bit data transfer Integrated baud rate generator Noise, Overrun and Framing error detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up Up to 64 System Function Registers(SFRs) may be implemented in the DF6805 design. PROGRAM MEMORY: from IDLE condition Three SCI related interrupts Up to 64kB of Program Memory may be implemented to the DF6805 design. Program Memory can be implemented as synchronous or asynchronous ROM. ALL CORE IS DESIGNED AS SYNCHRONOUS LOGIC WITHOUT ANY MICROCODE. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance PERIPHERALS The peripherals listed below are implemented in standard configuration of DF6805. DoCDTM on Chip Debugger Processor execution control Read, write all processor contents Hardware execution breakpoints Three wire communication interface Four 8-bit I/O Ports Interrupt Controller 7 interrupt sources 7 priority levels All trademarks mentioned in this document are trademarks of their respective owners. Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. CONFIGURATION The following parameters of the DF6805 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. TM * DoCD Hardware Debugger LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Sour- - used unused Harvard Von Neumann Synchronous Asynchronou used unused used unused used unused used unused used unused used unused used unused used unused * Architecture type * Memories type * Data Memory wait-states * Power saving STOP mode * WATCHDOG Timer * Timer system * Compare Capture channels * PORTS A, B, C, D * SCI - UART Interface * Support for MUL Instruction ce Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. PINS DESCRIPTION PIN clk rst prgdata[7:0] datai[7:0] ufrdatai[7:0] ready irq portai[7:0] portbi[7:0] portci[7:0] portdi[7:0] cap1,2 rxd clkdocd docddatai prgaddr[15:0] prgoe datao[7:0] addr[15:0] ramwe ramoe ufraddr[5:0] ufrwe ufroe halt portao[7:0] portbo[7:0] portco[7:0] portdo[7:0] ddra[7:0] ddrb[7:0] ddrc[7:0] ddrd[7:0] cmp1,2 txd docddatao docdclk prgwe ACTIVE Low Low * Low Low Low Low Low Low High * Low TYPE input input input input input input input input input input input input input input input output output output output output output output output output output output output output output output output output output output output output output output DESCRIPTION Global system clock Global system reset Program memory bus input Memory bus input UFRs data bus input Code and Data memory Ready Interrupt input Port A input Port B input Port C input Port D input Capture inputs SCI receiver data input DoCD DoCD TM TM SYMBOL clk rst prgdata(7:0) prgaddr(15:0) prgoe datao(7:0) datai(7:0) addr(15:0) ramwe ramoe ufraddr(5:0) ufrwe ufroe halt portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) ddra(7:0) ddrb(7:0) ddrc(7:0) ddrd(7:0) cap1 cap2 rxd clkdocd docddatai DoCD TM ufrdatai(7:0) ready irq portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) clock input serial Data input Program memory address bus Program memory output enable Data memory & UFR bus output Data memory address bus Data memory write enable Data memory output enable UFR's address bus UFRs write enable UFRs output enable Halt clock system (STOP inst.) Port A output Port B output Port C output Port D output Port A data direction control Port B data direction control Port C data direction control Port D data direction control Compare outputs SCI transmitter data output DoCD DoCD DoCD TM TM TM cmp1 cmp2 txd docddatao docdclk prgwe Interface BLOCK DIAGRAM Control Unit - Performs the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages execution of STOP instruction and wakes-up the processor from the STOP mode. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index registers (X) and related logic like arithmetic unit, logic unit and multiplier. Serial Data Output Serial Clock Output Program Memory Write * Kind of activity is configurable All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Bus Controller - Program Memory, Data Memory & SFR's (Special Function Register) interface controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register, and related logic. clk rst Opcode Decoder halt Control Unit BUS Controller ready prgdata(7:0) prgaddr(15:0) prgoe datai(7:0) datao(7:0) addr(23:0) ramwe ramoe ufraddr(5:0) ufrwe ufroe portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) ddra(7:0) ddrb(7:0) ddrc(7:0) ddrd(7:0) cap1 cap2 cmp1 cmp2 any ports pins cause data to be stored in the data registers. If any port pins are configured as output then data registers are driven out of those pins. Reads from port pins configured as input causes that input pin is read. If port pins is configured as output, during read data register is read. Writes to any ports pins not configured as outputs do not cause data to be driven out of those pins, but the data is stored in the output registers. Thus, if the pins later become outputs, the last data written to port will be driven out the port pins. Timer & Compare - The programmable timer is based on free-running 16-bit counter with a fixed divide by four prescaler. plus input capture/output compare circuitry. The timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals. The timer has 16bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contains the high and low byte of that functional block. Accessing the low byte of a specific timer function allows full control of that function, however, an access of the high byte inhibits that specific timer function until the byte is also accessed. Each of the input-capture channel has its own 16-bit time capture latch (input-capture register) and each of the output-compare channel has its own 16-bit compare register. Additional control bits permit software to control the edge(s) that trigger each input-capture function and the automatic actions that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications although it is not as efficient as dedicated hardware for some specific timing applications. Watchdog Timer - The Watchdog Timer consist of a free running Timer CLK/213 , plus control logic. The Watchdog Timer can be enabled by software by writing `1' to the WDOG bit in MISC register ($000C). Once enabled the WDT Timer cannot be disabled by software. In addition the WDOG bit acts as a reset mechanism for the WDT Timer. Writing logic one `1' to the WDOG bit clears Watchdog counter and inhibits Watchdog timeout irq Interrupt Controller ALU Watchdog Timer I/O Ports rxd txd clkdocd docddatai docddatao docdclk prgwe SCI Unit DoCD Debugger TM Timer with Compare / Capture Unit Interrupt Controller - DF6805 extended IC has implemented 7-level interrupt priority control. The interrupt requests may come from external pin (IRQ) as well as from particular peripherals. The DF6805 peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized according to default arrangement established during reset. When interrupt condition occurs, an interrupt status flag is set to indicate the condition. I/O Ports - All ports are 8-bit general-purpose bi-directional I/O system. The PORTA, PORTB, PORTC, PORTD data registers have their corresponding data direction registers DDRA, DDRB, DDRC, DDRD to control ports data flow. It assures that all DF6805's ports have full I/O selectable registers. Writes to All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. SCI - The SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The DF6805 resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multi-drop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag, this SCI also provides a transmit complete (TC) indication that can be used in applications with a modem. DoCD - Debug Unit - it's a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCDTM provides nonintrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. All trademarks mentioned in this document are trademarks of their respective owners. TM OPTIONAL PERIPHERALS There are also available an optional peripherals, not included in presented DF6805 Microcontroller Core. The optional peripherals, can be implemented in microcontroller core upon customer request. SPI - Master and Slave Serial Peripheral Interface Supports speeds up 1/4 of system clock Mode fault error Write collision error Software selectable polarity and phase of se- rial clock SCK System errors detection Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) Interrupt generation I2C bus controller - Master 7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation I2C bus controller - Slave NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies User defined data setup time on I2C lines Interrupt generation PWM - Pulse Width Modulation Timer Fixed-Point arithmetic coprocessor arithmetic coprocessor Floating-Point IEEE-754 standard single precision Floating-Point math coprocessor - IEEE754 standard single precision real, word and short integers http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA(R) devices after Place & Route: Speed Logic Cells Fmax grade CYCLONE -6 1689 79 MHz STRATIX -5 1690 83 MHz MERCURY -5 1671 85 MHz APEX II -7 1850 63 MHz APEX20KC -7 1698 55 MHz APEX20KE -1 1698 47 MHz ACEX1K -1 1739 41 MHz FLEX10KE -1 1739 41 MHz Core performance in ALTERA(R) devices Device IMPROVEMENT For user the most important is application speed improvement. The most commonly used arithmetic functions and theirs improvement are shown in table below. Improvement was computed as {M68HC04 clock periods} divided by {DF6805 clock periods} required to execute an identical function. More details are available in core documentation Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 16-bit addition (immediate data) 16-bit addition (direct addressing) 16-bit addition (indirect addressing 16-bit subtraction (immediate data) 16-bit subtraction (direct addressing) 16-bit subtraction (indirect addressing Multiplication Division Improvement 4 4 3,6 4 4 3,6 4 4 3,6 4 4 3,6 5 5 Area utilized by the each unit of DF6805 core in vendor specific technologies is summarized in table below. Component [LC] Area [FFs] CPU* Main Timer COM/CAP Watchdog UART - SCI I/O Ports Total area 1134 110 150 29 272 161 1856 153 55 60 14 124 64 470 *CPU - consisted of ALU, Control Unit and Instruction Decoder, Bus Controller with support for 64KB RAM, External IRQ pin Interrupt Controller Core components area utilization DF68XX FAMILY OVERVIEW The main features of each DF68XX family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Size - ASIC gates 6 700 8 900 12 000 6 500 Compare\Capture SPI M/S Interface Motorola Memory Expansion Logic Interrupt sources DoCD Debugger Pulse accumulator * + Watchdog Timer Main Timer System Real Time Interrupt I\O Ports Design DF6805 DF6808 DF6811 DF6811CPU 64k 64k 64k 64k 64k 64k 16M 16M - 7 7 20 3 7 7 17 3 + 1* 1* * * * * 2/2* 22* 5/3* + 1* 1* 1* + * * * + 4 4 4 + + * + + * * * DF68XX family of High Performance Microcontroller Cores + optional * configurable All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Interface for additional SFRs READY for Pro. and Data mem. Physical Linear memory space Paged Data Memory space Interrupt levels Data Pointers SCI (UART) CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND n fo @ d c d .p l e-mail: iinfo@dcd.pl tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. |
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