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| 8 Bit Microcontroller TLCS-870/X Series TMP88PH41UG The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2007 TOSHIBA CORPORATION All Rights Reserved Revision History Date 2007/7/20 Revision 1 First Release Table of Contents TMP88PH41UG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Functional Description 2.1 Functions of the CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Address Map............................................................................................................................... Program Memory (ROM) .......................................................................................................................... Data Memory (RAM) ................................................................................................................................. System Clock Control Circuit .................................................................................................................... Clock Generator Timing Generator Standby Control Circuit Controlling Operation Modes External Reset Input Adress Trap Reset Watchdog Timer Reset System Clock Reset 2.1.1 2.1.2 2.1.3 2.1.4 7 8 8 9 2.1.5 2.1.4.1 2.1.4.2 2.1.4.3 2.1.4.4 2.1.5.1 2.1.5.2 2.1.5.3 2.1.5.4 Reset Circuit ........................................................................................................................................... 21 3. Interrupt Control Circuit 3.1 3.2 3.3 Interrupt latches (IL38 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Interrupt acceptance processing is packaged as follows........................................................................ 28 Saving/restoring general-purpose registers ............................................................................................ 29 Using Automatic register bank switcing Using register bank switching Using PUSH and POP instructions Using data transfer instructions 3.2.1 3.2.2 Interrupt master enable flag (IMF) .......................................................................................................... 25 Individual interrupt enable flags (EF38 to EF3) ...................................................................................... 25 3.3.1 3.3.2 3.4 3.5 3.3.3 3.3.2.1 3.3.2.2 3.3.2.3 3.3.2.4 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Address error detection .......................................................................................................................... 32 Debugging .............................................................................................................................................. 32 Interrupt return ........................................................................................................................................ 31 3.4.1 3.4.2 4. Special Function Register 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 i 5. Input/Output Ports 5.1 5.2 5.3 5.4 5.5 Port P1 (P15 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P37 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 41 42 43 44 6. Time Base Timer (TBT) and Divider Output (DVO) 6.1 6.2 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7. Watchdog Timer (WDT) 7.1 7.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... 52 53 54 54 55 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 8. 16-Bit TimerCounter 1 (TC1) 8.1 8.2 8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Timer mode............................................................................................................................................. External Trigger Timer Mode .................................................................................................................. Event Counter Mode ............................................................................................................................... Window Mode ......................................................................................................................................... Pulse Width Measurement Mode............................................................................................................ Programmable Pulse Generate (PPG) Output Mode ............................................................................. 60 62 64 65 66 69 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 9. 16-Bit Timer (CTC) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Timer mode with software start............................................................................................................... Timer mode with external trigger start .................................................................................................... Event counter mode................................................................................................................................ Programmable Pulse Generate (PPG) output mode .............................................................................. 77 78 79 80 9.3.1 9.3.2 9.3.3 9.3.4 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ii 10.2 10.3 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3.1 Timer mode........................................................................................................................................... 87 Figure 10-3 ...................................................................................................................................................... 89 10.3.3 Capture Mode ....................................................................................................................................... 90 11. 8-Bit TimerCounter 4 (TC4) 11.1 11.2 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Timer Mode........................................................................................................................................... Event Counter Mode ............................................................................................................................. Programmable Divider Output (PDO) Mode ......................................................................................... Pulse Width Modulation (PWM) Output Mode ...................................................................................... 93 93 93 94 11.3.1 11.3.2 11.3.3 11.3.4 12. Motor Control Circuit (PMD: Programmable motor driver) 12.1 12.2 12.3 Outline of Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Configuration of the Motor Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Position Detection Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Configuration of the position detection unit......................................................................................... 102 Position Detection Circuit Register Functions..................................................................................... 103 Outline Processing in the Position Detection Unit .............................................................................. 106 12.4 12.5 12.3.1 12.3.2 12.3.3 12.4.1 Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Configuration of the Timer Unit ........................................................................................................... 108 Timer Circuit Register Functions Outline Processing in the Timer Unit 12.4.1.1 12.4.1.2 Three-phase PWM Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Configuration of the three-phase PWM output unit............................................................................. 112 Pulse width modulation circuit (PWM waveform generating unit) Commutation control circuit 12.5.1 12.5.2 12.5.3 12.5.4 12.5.5 12.6.1 12.5.1.1 12.5.1.2 12.6 Electrical Angle Timer and Waveform Arithmetic Circuit . . . . . . . . . . . . . . . . . . 124 Electrical Angle Timer and Waveform Arithmetic Circuit .................................................................... 125 Functions of the Electrical Angle Timer and Waveform Arithmetic Circuit Registers List of PMD Related Control Registers Register Functions of the Waveform Synthesis Circuit....................................................................... Port output as set with UOC/VOC/WOC bits and UPWM/VPWM/WPWM bits................................... Protective Circuit................................................................................................................................. Functions of Protective Circuit Registers ............................................................................................ 116 118 120 122 12.6.1.1 12.6.1.2 13. Asynchronous Serial interface (UART) 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 142 Data Receive Operation ..................................................................................................................... 142 137 138 140 141 141 142 142 142 13.8.1 13.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 iii 13.9.1 13.9.2 13.9.3 13.9.4 13.9.5 13.9.6 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full ..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 143 143 143 144 144 145 14. Synchronous Serial Interface (SIO) 14.1 14.2 14.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Clock source ....................................................................................................................................... 149 Shift edge............................................................................................................................................ 151 Leading edge Trailing edge Internal clock External clock 14.3.1.1 14.3.1.2 14.3.2.1 14.3.2.2 14.3.1 14.3.2 14.4 14.5 14.6 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4-bit and 8-bit transfer modes ............................................................................................................. 152 4-bit and 8-bit receive modes ............................................................................................................. 154 8-bit transfer / receive mode ............................................................................................................... 155 14.6.1 14.6.2 14.6.3 15. 10-bit AD Converter (ADC) 15.1 15.2 15.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Software Start Mode ........................................................................................................................... 161 Repeat Mode ...................................................................................................................................... 161 Register Setting ................................................................................................................................ 162 15.4 15.5 15.6 15.3.1 15.3.2 15.3.3 STOP mode during AD Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 164 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Analog input pin voltage range ........................................................................................................... 165 Analog input shared pins .................................................................................................................... 165 Noise Countermeasure ....................................................................................................................... 165 15.6.1 15.6.2 15.6.3 16. OTP operation 16.1 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 MCU mode.......................................................................................................................................... 167 Program Memory Data Memory Input/Output Circuiry 16.1.1.1 16.1.1.2 16.1.1.3 16.1.2.1 16.1.2.2 16.1.1 16.1.2 PROM mode ....................................................................................................................................... 168 Programming Flowchart (High-speed program writing) Program Writing using a General-purpose PROM Programmer 17. Input/Output Circuitry 17.1 Control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 iv 17.2 17.3 Input/output ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 NC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 18. Electrical Characteristics 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics, AC Characteristics (PROM mode). . . . . . . . . . . . . . . . . . . Read operation in PROM mode.......................................................................................................... 178 Program operation (High-speed) ........................................................................................................ 179 175 176 176 177 177 178 18.6.1 18.6.2 Recommended Oscillation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 19. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/X (LSI). v vi TMP88PH41UG CMOS 8-Bit Microcontroller TMP88PH41UG The TMP88PH41UG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 16384 bytes of One-Time PROM. It is pin-compatible with the TMP88CH41UG (Mask ROM version). The TMP88PH41UG can realize operations equivalent to those of the TMP88CH41UG by programming the on-chip PROM. Product No. ROM (EPROM) 16384 bytes RAM 512+128 bytes Package MASK ROM MCU TMP88PH41UG LQFP44-P-1010-0.80B TMP88CH41UG 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/X series - Instruction execution time : 0.20 s (at 20 MHz) - 181 types & 842 basic instructions 2. 25 interrupt sources (External : 6 Internal : 19) 3. Input / Output ports (33 pins) Large current output: 16pins (Typ. 20mA), LED direct drive 4. Prescaler - Time base timer Divider output function (DVO) 5. Watchdog Timer Select of "internal reset request" or "interrupt request". 6. 16-bit timer counter: 1 ch - Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 7. 16-bit timer/counter(CTC): 1ch - CTC:Timer,event counter or PPG (Programmable Pulse) output * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP88PH41UG 8. 8-bit timer counter : 1 ch - Timer, Event counter, Capture modes 9. 8-bit timer counter : 1 ch - Timer, Event counter, Pulse width modulation (PWM) output, Programmable divider output (PDO) modes 10. Programmable motor driver (PMD) : 1 ch - Sine wave drive circuit (built-in sine wave data-table RAM) Rotor position detect function Motor contro timer and capture function Overload protective function Auto commutation and auto position detection start function 11. 8-bit UART/SIO : 1 ch 12. 10-bit successive approximation type AD converter - Analog input: 8 ch 13. Clock oscillation circuit : 1 set 14. Low power consumption operation (2 modes) - STOP mode: Oscillation stops. (Battery/Capacitor back-up.) - IDLE mode: CPU stops. Only peripherals operate using high frequency clock. Release by interruputs (CPU restarts). 15. Operation voltage: 4.5 V to 5.5 V at 20MHz Page 2 TMP88PH41UG 1.2 Pin Assignment VSS XIN XOUT TEST VDD (INT3/TC3) P21 (PWM4/PDO4/INT4/TC4) P22 Figure 1-1 Pin Assignment Page 3 (STOP/INT5) P20 (Z1) P30 (Y1) P31 RESET 1 2 3 4 5 6 7 8 9 10 11 VAREF AVDD AVSS (INT0) P10 (INT1) P11 (TC1/INT2) P12 (DVO) P13 (PPG1) P14 P15 NC NC 33 32 31 30 29 28 27 26 25 24 23 P67 (AIN7/DBOUT1) P66 (AIN6) P65 (AIN5) P64 (AIN4) P63 (AIN3) P62 (AIN2) P61 (AIN1) P60 (AIN0) P47 (CTC) P46 (PPG2) P45 (SO/TXD) 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 P44(SI/RXD) P43(SCK) P42(PDU1) P41(PDV1) P40(PDW1) P37(CL1) P36(EMG1) P35(U1) P34(V1) P33(W1) P32(X1) 1.3 Block Diagram TMP88PH41UG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP88PH41UG 1.4 Pin Names and Functions The TMP88PH41UG has MCU mode and PROM mode. Table 1-1 shows the pin functions in MCU mode. The PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/2) Pin Name P15 P14 PPG1 Pin Number 42 Input/Output IO IO O IO O IO I I IO I IO I IO I I O IO I I IO I I IO I IO I IO O IO O IO O IO O IO O IO O IO I IO I PORT15 PORT14 PPG1 output PORT13 Divider Output PORT12 External interrupt 2 input TC1 input PORT11 External interrupt 1 input PORT10 External interrupt 0 input PORT22 TC4 input External interrupt 4 input PWM4/PDO4 output PORT21 TC3 pin input External interrupt 3 input Functions 41 P13 DVO 40 P12 INT2 TC1 P11 INT1 P10 INT0 39 38 37 P22 TC4 INT4 PWM4/PDO4 7 P21 TC3 INT3 P20 INT5 STOP 6 9 PORT20 External interrupt 5 input STOP mode release signal input PORT37 PMD over load protection input1 PORT36 PMD emergency stop input1 PORT35 PMD control output U1 PORT34 PMD control output V1 PORT33 PMD control output W1 PORT32 PMD control output X1 PORT31 PMD control output Y1 PORT30 PMD control output Z1 PORT47 CTC input PORT46 PPG2 output P37 CL1 17 P36 EMG1 16 P35 U1 P34 V1 P33 W1 P32 X1 P31 Y1 P30 Z1 P47 CTC P46 PPG2 15 14 13 12 11 10 25 24 Page 5 1.4 Pin Names and Functions TMP88PH41UG Table 1-1 Pin Names and Functions(2/2) Pin Name P45 SO TXD P44 SI RXD P43 SCK Pin Number Input/Output IO O O IO I I IO IO IO I IO I IO I IO I O IO I IO I IO I IO I IO O IO I IO I I O I PORT45 Serial Data Output UART data output PORT44 Serial Data Input UART data input PORT43 Serial Clock I/O PORT42 PMD control input U1 PORT41 PMD control input V1 PORT40 PMD control input W1 PORT67 Analog Input7 PMD debug output1 PORT66 Analog Input6 PORT65 Analog Input5 PORT64 Analog Input4 PORT63 Analog Input3 PORT62 Analog Input2 PORT61 Analog Input1 PORT60 Analog Input0 Functions 23 22 21 P42 PDU1 P41 PDV1 P40 PDW1 P67 AIN7 DBOUT1 P66 AIN6 P65 AIN5 P64 AIN4 P63 AIN3 P62 AIN2 P61 AIN1 P60 AIN0 XIN XOUT RESET 20 19 18 33 32 31 30 29 28 27 26 2 3 8 Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal Test pin for out-going test and the Serial PROM mode control pin. Usually fix to low level. Fix to high level when the Serial PROM mode starts. Analog Base Voltage Input Pin for A/D Conversion Analog Power Supply Analog Power Supply +5V 0(GND) Non Connection Non Connection TEST 4 I VAREF AVDD AVSS VDD VSS NC NC 34 35 36 5 25 43 44 I I I I IO I I Page 6 TMP88PH41UG 2. Functional Description 2.1 Functions of the CPU Core The CPU core consists mainly of the CPU, system clock control circuit, and interrupt control circuit. This chapter describes the CPU core, program memory, data memory, and reset circuit of the TMP88PH41UG. 2.1.1 Memory Address Map The memory of the TMP88PH41UG consists of four blocks: ROM, RAM, SFR (Special Function Registers), and DBR (Data Buffer Registers), which are mapped into one 1-Mbyte address space. The general-purpose registers consist of 16 banks, which are mapped into the RAM address space. Figure 2-1 shows a memory address map of the TMP88PH41UG. SFR RAM (128 bytes) RAM ( 512 bytes) 002BFH 01F80H 00000H 0003FH 00040H 000BFH 000C0H 64 bytes 128 bytes 512 bytes Special Function Register General-purpose Register Bank (8 registers x 16 banks) Random-Access Memory DBR 128 bytes 01FFFH 04000H Data Buffer Register (peripheral hardware control register / status register) 16128 bytes Program Memory ROM ( 16K Kbytes) 07EFFH FFF00H FFF3FH FFF40H FFF7FH FFF80H FFFFFH 64 bytes 64 bytes 128 bytes Interrupt Vector Table Vector Table for Vector Call Instructions Interrupt Vector Table SFR: Special Function Registers Input/output port Peripheral hardware control register Peripheral hardware status register RAM: Random Access Memory System control register Data memory Interrupt control register Stack Program status word General-purpose register bank ROM: Read-Only Memory Program memory Vector Table DBR: Data Buffer Registers Input/output port Peripheral hardware control register Peripheral hardware status register Figure 2-1 Memory address map Page 7 2. Functional Description 2.1 Functions of the CPU Core TMP88PH41UG 2.1.2 Program Memory (ROM) The TMP88PH41UG contains 16Kbytes program memory (OTP) located at addresses 04000H to 07EFFH and addresses FFF00H to FFFFFH. 2.1.3 Data Memory (RAM) The TMP88PH41UG contains 512bytes +128bytes RAM. The first 128bytes location (00040H to 000BFH) of the internal RAM is shared with a general-purpose register bank. The content of the data memory is indeterminate at power-on, so be sure to initialize it in the initialize routine. Example :Clearing the internal RAM of the TMP88PH41UG (clear all RAM addresses to 0, except bank 0) LD LD LD SRAMCLR: LD DEC JRS HL, 0048H A, 00H BC, 277H (HL+), A BC F, SRAMCLR ; Set the start address ; Set the initialization data (00H) ; Set byte counts (-1) Note:Because general-purpose registers exist in the RAM, never clear the current bank address of RAM. In the above example, the RAM is cleared except bank 0. Page 8 TMP88PH41UG 2.1.4 System Clock Control Circuit The System Clock Control Circuit consists of a clock generator, timing generator, and standby control circuit. Timing generator control register Clock generator XIN High-frequency clock oscillator circuit XOUT fc Timing generator Standby control circuit 00038H SYSCR1 System clocks 00039H SYSCR2 TBTCR 00036H System control register Figure 2-2 System Clock Control Circuit 2.1.4.1 Clock Generator The Clock Generator generates the fundamental clock which serves as the reference for the system clocks supplied to the CPU core and peripheral hardware units. The high-frequency clock (frequency fc) can be obtained easily by connecting a resonator to the XIN and XOUT pins. Or a clock generated by an external oscillator can also be used. In this case, enter the external clock from the XIN pin and leave the XOUT pin open. The TMP88PH41UG does not support the CR network that produces a time constant. High-frequency Clock XIN XOUT XIN XOUT (Open) (a) Using a crystal or ceramic resonator (b) Using an external oscillator Figure 2-3 Example for Connecting a Resonator Adjusting the oscillation frequency Note: Although no hardware functions are provided that allow the fundamental clock to be monitored directly from the outside, the oscillation frequency can be adjusted by forwarding the pulse of a fixed frequency (e.g., clock output) to a port and monitoring it in a program while interrupts and the watchdog timer are disabled. For systems that require adjusting the oscillation frequency, an adjustment program must be created beforehand. 2.1.4.2 Timing Generator The Timing Generator generates various system clocks from the fundamental clock that are supplied to the CPU core and peripheral hardware units. The Timing Generator has the following functions: Page 9 2. Functional Description 2.1 Functions of the CPU Core TMP88PH41UG 1. Generate a divider output (DVO) pulse 2. Generate the source clock for the time base timer 3. Generate the source clock for the watchdog timer 4. Generate the internal source clock for the timer counter 5. Generate a warm-up clock when exiting STOP mode (1) Configuration of the Timing Generator The Timing Generator a 3-stage prescaler, 21-stage dividers, and a machine cycle counter. When reset and when entering/exiting STOP mode, the prescaler and dividers are cleared to 0. Machine cycle counter DV1CK Prescaler fc S A Y B Selector Divider Divider 012 123456 7 8 9 10111213141516171819 2021 Standby control circuit Watchdog timer Timer counter Time base timer Divider Output etc. Figure 2-4 Configuration of the Timing Generator Page 10 TMP88PH41UG Divider Control Register CGCR (0030H) 7 0 6 0 5 DV1CK 4 3 2 0 1 0 0 0 (Initial value: 000* *000) DV1CK Selects input clock to the first divider stage 0: fc/4 1: fc/8 R/W Note 1: fc: the high-frequency clock [Hz], *: Don't care Note 2: The CGCR Register bits 4 and 3 show an indeterminate value when read. Note 3: Be sure to write "0" to CGCR Register bits 7, 6, 2, 1 and 0. Timing Generator Control Register TBTCR (0036H) 7 DVOEN 6 DVOCK 5 4 0 3 TBTEN 2 1 TBTCK 0 (Initial value: 0000 0000) Note 1: *: Don't care Note 2: Be sure to write "0" to TBTCR Register bit 4. (2) Machine cycle Instruction execution and the internal hardware operations are synchronized to the system clocks. The minimum unit of instruction execution is referred to as the "mgmachine cycle". The TLCS870/X series has 15 types of instructions, from 1-cycle instructions which are executed in one machine cycle up to 15-cycle instructions that require a maximum of 15 machine cycles. A machine cycle consists of four states (S0 to S3), with each state comprised of one main system clock cycle. 1/fc Main system clock States S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle (0.20 s at 20 MHz) Figure 2-5 Machine Cycles Page 11 2. Functional Description 2.1 Functions of the CPU Core TMP88PH41UG 2.1.4.3 Standby Control Circuit The Standby Control Circuit starts/stops the high-frequency clock oscillator circuit and selects the main system clock. The System Control Registers (SYSCR1, SYSCR2) are used to control operation modes of this circuit. Figure 2-6 shows an operation mode transition diagram, followed by description of the System Control Registers. (1) Single clock mode Only the high-frequency clock oscillator circuit is used. Because the main system clock is generated from the high-frequency clock, the machine cycle time in single clock mode is 4/fc [s]. 1. NORMAL mode In this mode, the CPU core and peripheral hardware units are operated with the high-frequency clock. The TMP88PH41UG enters this NORMAL mode after reset. 2. IDLE mode In this mode, the CPU and watchdog timer are turned off while the peripheral hardware units are operated with the high-frequency clock. IDLE mode is entered into by using System Control Register 2. The device is placed out of this mode and back into NORMAL mode by an interrupt from the peripheral hardware or an external interrupt. When IMF (interrupt master enable flag) = 1 (interrupt enabled), the device returns to normal operation after the interrupt has been serviced. When IMF = 0 (interrupt disabled), the device restarts execution beginning with the instruction next to one that placed it in IDLE mode. 3. STOP mode The entire system operation including the oscillator circuit is halted, retaining the internal state immediately before being stopped, with a minimal amount of power consumed. STOP mode is entered into by using System Control Register 1, and is exited by STOP pin input (level or edge selectable). After an elapse of the warm-up time, the device restarts execution beginning with the instruction next to one that placed it in STOP mode. Table 2-1 Single Clock Mode Oscillator Circuit Operation Mode High Frequency Low Frequency CPU Core Peripheral Circuit Machine Cycle Time RESET Single Clock NORMAL IDLE Oscillate - Reset Operate Reset 4/fc [s] Operate Stop STOP Stop Stop - RESET Reset deasserted Instruction NORMAL mode Interrupt Input for releasing mode STOP mode Instruction IDLE mode Figure 2-6 Operation Mode Transition Diagram Page 12 TMP88PH41UG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP Place the device in STOP mode Select method by which the device is released from STOP mode Select operation mode after exiting STOP mode Select port output state during STOP mode 0: Keep the CPU core and peripheral hardware operating 1: Stop the CPU core and peripheral hardware (placed in STOP mode) 0: Released by a rising edge on STOP pin input 1: Released by a high level on STOP pin input 0: Returns to NORMAL mode 1: Reserved 0: High-impedance state 1: Hold output When Returning to NORMAL Mode DV1CK = 0 DV1CK = 1 3 x 217/fc 217/fc 215/fc Reserved R/W RELM RETM OUTEN WUT Unit of warm-up time when exiting STOP mode 00 01 10 11 3 x 216/fc 216/fc 214/fc Reserved Note 1: When entering from NORMAL mode into STOP mode, always be sure to set SYSCR1 System Control Register 2 SYSCR2 (0039H) 7 XEN 6 0 5 SYSCK 4 IDLE 3 2 1 0 (Initial value: 1000 ****) XEN Control high-frequency oscillator Select (write)/monitor (read) system clock Place the device in IDLE mode 0: Stop oscillation 1: Continue or start oscillating 0: High-frequency clock (NORMAL/IDLE) 1: Reserved 0: Keep the CPU and WDT operating 1: Stop the CPU and WDT (IDLE mode entered) R/W SYSCK R/W IDLE R/W RETM 0 1 Operation Mode after Releasing STOP Mode NORMAL mode No operation XEN 1 0 SYSCK 0 1 Note 1: When exiting STOP mode, SYSCR2 Page 13 2. Functional Description 2.1 Functions of the CPU Core TMP88PH41UG 2.1.4.4 Controlling Operation Modes (1) STOP mode STOP mode is controlled by System Control Register 1 (SYSCR1) and the STOP pin input. The STOP pin is shared with P20 port and INT5 (external interrupt input 5). STOP mode is entered into by setting STOP (SYSCR1 Register bit 7) to 1. During STOP mode, the device retains the following state. 1. Stop oscillation, thereby stopping operation of all internal circuits. 2. The data memory, register, program status word, and port output latch hold the state in which they were immediately before entering STOP mode. 3. Clear the prescaler and divider for the timing generator to 0. 4. The program counter holds the instruction address two instructions ahead the one that placed the device in STOP mode (e.g., "SET (SYSCR1).7"). The device is released from STOP mode by the active level or edge on STOP pin input as selected by SYSCR1 Note: Before entering STOP mode, be sure to disable interrupts. This is because if the signal on an external interrupt pin changes state during STOP (from entering STOP mode till completion of warm-up) the interrupt latch is set to 1, so that the device may accept the interrupt immediately after exiting STOP mode. Also, when reenabling interrupts after exiting STOP mode, be sure to clear the unnecessary interrupt latches beforehand. a. Released by level (when RELM = 1) The device is released from STOP mode by a high level on STOP pin input. Any instruction to place the device in STOP mode is ignored when executed while STOP pin input level is high, and the device immediately goes to a release sequence (warm-up) without entering STOP mode. Therefore, before STOP mode can be entered while RELM = 1, the STOP pin input must be verified to be low in a program. There are following methods to do this verification. 1. Testing the port status 2. INT5 interrupt (interrupt generated at a falling edge on INT5 pin input) Example 1 :Entering STOP mode from NORMAL mode by testing P20 port LD SSTOPH : TEST JRS DI SET (SYSCR1) . 7 (SYSCR1), 01010000B (P2DR) . 0 F, SSTOPH ; IMF 0 ; Place the device in STOP mode ; Select to be released from STOP mode by level ; Wait until STOP pin input goes low Example 2 :Entering STOP mode from NORMAL mode by INT5 interrupt PINT5 : TEST (P2DR) . 0 ; Do not enter STOP mode if P20 port input level is high, to eliminate noise ; Do not enter STOP mode if P20 port input level is high, to eliminate noise ; Select to be released from STOP mode by level ; IMF 0 (SYSCR1) . 7 ; Place the device in STOP mode JRS F, SINT5 LD DI SET SINT5 : RETI (SYSCR1), 01010000B Page 14 TMP88PH41UG STOP pin VIH XOUT pin NORMAL operation STOP mode Detect low on STOP pin input in a program before entering STOP mode Warm-up NORMAL operation Released from STOP mode in hardware Always released by a high level on STOP pin input Figure 2-7 Released from STOP Mode by Level Note 1: Once warm-up starts, the device does not return to STOP mode even when the STOP pin input is pulled low again. Note 2: If RELM is changed to 1 (level mode) after being set to 0 (edge mode), STOP mode remains unchanged unless a rising edge on STOP pin input is detected. a. Released by edge (when RELM = 0) The device is released from STOP mode by a rising edge on STOP pin input. This method is used in applications where a relatively short time of program processing is repeated at certain fixed intervals. Apply a fixed-period signal (e.g., clock from the low-power oscillating source) to the STOP pin. When RELM = 0 (edge mode), the device is placed in STOP mode even when the STOP pin input level is high. Example :Entering STOP mode from NORMAL mode DI ; IMF 0 ; Set to be released by edge when entering STOP mode LD (SYSCR1) , 10010000B STOP pin VIH XOUT pin NORMAL operation Placed into STOP mode in a program STOP mode Warm-up NORMAL operation STOP mode Released from STOP mode in hardware by a rising edge on STOP pin input. Figure 2-8 Released from STOP Mode by Edge Page 15 2. Functional Description 2.1 Functions of the CPU Core TMP88PH41UG The device is released from STOP mode following the sequence described below. 1. Only the high-frequency oscillator is oscillating. 2. A warm-up time is inserted in order to allow for the clock oscillation to stabilize. During warm-up, the internal circuits remain idle. The warm-up time can be selected from three choices according to the oscillator characteristics by using SYSCR1 Warm-up Time [ms] WUT When Returning to NORMAL Mode DV1CK = 0 00 01 10 11 9.831 3.277 0.819 Reserved DV1CK = 1 19.662 6.554 1.638 Reserved Note: Because the warm-up time is obtained from the fundamental clock by dividing it, if the oscillation frequency fluctuates while exiting STOP mode, the warm-up time becomes to have some error. Therefore, the warm-up time must be handled as an approximate value. The device can also be released from STOP mode by pulling the RESET pin input low, in which case the device is immediately reset as is normally reset by RESET. After reset, the device starts operating from NORMAL mode. Note: When exiting STOP mode while the device is retained at low voltage, the following caution is required. Before exiting STOP mode, the power supply voltage must be raised to the operating voltage. At this time, the RESET pin level also is high and rises along with the power supply voltage. If the device has a time-constant circuit added external to the chip, the voltage on RESET pin input does not rise as fast as the power supply voltage. Therefore, if the voltage level on RESET pin input is below the RESET pin's noninverted, high-level input voltage (hysteresis input), the device may be reset. Page 16 Oscillator circuit Oscillation Stop Main system clock a+3 Stop Program counter SET (SYSCR1). 7 a+2 Instruction execution n+1 n+2 n+3 n+4 Divider n 0 (a) Entering STOP mode (Example: Entered into by the SET (SYSCR1). 7 instruction placed at address a) Figure 2-9 Entering and Exiting STOP Mode (when DV1CK = 0) a+3 a+4 a+5 a+6 Instruction at address a + 2 Instruction at address a + 3 0 (b) Exiting STOP mode 1 2 3 Page 17 Warm-up STOP pin input Oscillator circuit Stop Oscillation Main system clock Program counter Instruction execution Stop Instruction at address a + 4 Divider 0 Count up TMP88PH41UG 2. Functional Description 2.1 Functions of the CPU Core TMP88PH41UG (2) IDLE mode IDLE mode is controlled by System Control Register 2 (SYSCR2) and a maskable interrupt. During IDLE mode, the device retains the following state. 1. The CPU and watchdog timer stop operating. The peripheral hardware continues operating. 2. The data memory, register, program status word, and port output latch hold the state in which they were immediately before entering IDLE mode. 3. The program counter holds the instruction address two instructions ahead the one that placed the device in IDLE mode. Example :Placing the device in IDLE mode SET (SYSCR2) . 4 Place the device in IDLE mode (by instruction) Stop the CPU and WDT Reset input ? No No Yes Reset Interrupt request ? Yes No IMF = 1 Yes (Released by interrupt) (Released normally) Interrupt handling Execute the instruction next to one that placed device IDLE mode Figure 2-10 IDLE Mode Page 18 TMP88PH41UG The device can be released from IDLE mode normally or by an interrupt as selected with the interrupt master enable flag (IMF). a. Released normally (when IMF = 0) The device can be released from IDLE mode by the interrupt source enabled by the interrupt individual enable flag (EF), and restarts execution beginning with the instruction next to one that placed it in IDLE mode. The interrupt latch (IL) for the interrupt source used to exit IDLE mode normally needs to be cleared to 0 using a load instruction. b. Released by interrupt (when IMF = 1) The device can be released from IDLE mode by the interrupt source enabled by the interrupt individual enable flag (EF), and enters interrupt handling. After interrupt handling, the device returns to the instruction next to one that placed it in IDLE mode. The device can also be released from IDLE mode by pulling the RESET pin input low, in which case the device is immediately reset as is normally reset by RESET. After reset, the device starts operating from NORMAL mode. Note: If a watchdog timer interrupt occurs immediately before entering IDLE mode, the device processes the watchdog timer interrupt without entering IDLE mode. Page 19 Main system clock 2. Functional Description 2.1 Functions of the CPU Core Interrupt request a+2 a+3 IDLE Program counter SET (SYSCR2). 4 Instruction execution Operating Watchdog timer (a) Entering IDLE mode (Example: Entered into by the SET instruction placed at address a) Main system clock Interrupt request a+3 a+4 Program counter Instruction at address a + 2 Figure 2-11 Entering and Exiting IDLE Mode Operating a+3 Interrupt accepted Operating Page 20 Instruction execution IDLE Watchdog timer IDLE 1. Released normally Main system clock Interrupt request Program counter Instruction execution IDLE Watchdog timer IDLE 2. Released by interrupt TMP88PH41UG (b) Exiting IDLE mode TMP88PH41UG 2.1.5 Reset Circuit The TMP88PH41UG has four ways to generate a reset: external reset input, address trap reset, watchdog timer reset, or system clock reset. Table 2-3 shows how the internal hardware is initialized by reset operation. At power-on time, the internal cause reset circuits (watchdog timer reset, address trap reset, and system clock reset) are not initialized. Table 2-3 Internal Hardware Initialization by Reset Operation Internal Hardware Program Counter (PC) Stack Pointer (SP) General-purpose Registers (W, A, B, C, D, E, H, L) Register Bank Selector (RBS) Jump Status Flag (JF) Zero Flag (ZF) Carry Flag (CF) Half Carry Flag (HF) Sign Flag (SF) Overflow Flag (VF) Interrupt Master Enable Flag (IMF) Interrupt Individual Enable Flag (EF) Interrupt Latch (IL) Interrupt Nesting Flag (INF) Initial Value (FFFFEH to FFFFCH) Not initialized Not initialized 0 Watchdog timer 1 Not initialized Not initialized Not initialized Output latch of input/output port Not initialized Not initialized 0 0 Control register 0 0 RAM See description of each control register. Not initialized See description of each input/output port. Enable Prescaler and divider for the timing generator 0 Internal Hardware Initial Value 2.1.5.1 External Reset Input The RESET pin is a hysteresis input with a pull-up resistor included. By holding the RESET pin low for at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operating voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initialized. When the RESET pin input is released back high, the device is freed from reset and starts executing the program beginning with the vector address stored at addresses FFFFCH to FFFFEH. VDD RESET Reset input Figure 2-12 Reset Circuit 2.1.5.2 Adress Trap Reset If the CPU should start looping for reasons of noise, etc. and attempts to fetch instructions from the internal RAM,SFR or DBR area, the device generats an internal reset. The addess trap permission/prohibition is set by the address trap reset control register (ATAS,ATKEY). The address trap is permited initially and the internal reset is generated by fetching from internal RAM,SFR or DBR area. If the address trap is prohibited, instructions in the internal RAM area can be executed. Page 21 2. Functional Description 2.1 Functions of the CPU Core TMP88PH41UG Address Trap Control Register ATAS (1F94H) 7 6 5 4 3 2 1 0 ATAS (initial value: **** ***0) ATAS Select the address trap permission / prohibition 0: Permit address trap 1: Prohibit address trap (It may be available after setting control code for ATKEY register) Write only Address Trap Control Code Register ATKEY (1F95H) 7 6 5 4 3 2 1 0 (initial value: **** ****) ATKEY Write control code to prohibit address trap D2H: Address trap prohibition code Others: Ineffective Write only Note: Read-modify-write instructions, such as a bit manipulation, cannot access ATAS or ATKEY register because these register are write only. Note 1: In development tools, address trap cannot be prohibited in the internal RAM,SFR or DBR area with the address trap control registers. When using development tools, even if the address trap permission/prohibition setting is changed in the user's program, this change is ineffective. To execute instructions from the RAM area, development tools must be set accordingly. Note 2: While the SWI instruction at an address immediately before the address trap area is executing, the program counter is incremented to point to the next address in the address trap area; an address trap is therefore taken immediately. Development tool setting * To prohibit the address trap: 1. Modify the iram (mapping attribute) area to (00040H to 000BFH) in the memory map window. 2. Set 000C0H to "address trap prohibition area" as a new eram (mapping attribute) area. 3. Load the user program 4. Execute the address trap prohibition code in the user's program 2.1.5.3 Watchdog Timer Reset Refer to the Section "Watchdog Timer." 2.1.5.4 System Clock Reset When SYSCR2 Page 22 TMP88PH41UG 3. Interrupt Control Circuit The TMP88PH41UG has a total of 25 interrupt sources excluding reset. Interrupts can be nested with priorities. Two of the internal interrupt sources are pseudo nonmaskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Factors Internal/External Internal Internal External External Internal Internal Internal Internal External Internal Internal Internal Internal Internal Internal Internal External External External Internal Internal Internal Internal Internal Internal (Reset) INTSWI (Software interrupt) INTWDT (Watchdog timer interrupt) INT0 (External interrupt 0) Reserved INT1 (External interrupt 1) INTTBT (TBT interrupt) Reserved INTEMG1 (ch1 Error detect interrupt) Reserved INTCLM1 (ch1 Overload protection interrupt) Reserved INTTMR31 (ch1 Timer 3 interrupt) Reserved Reserved INT5 (External interrupt 5) INTPDC1 (ch1 Posision detect interrupt) Reserved INTPWM1 (ch1 Waveform generater interrupt) Reserved INTEDT1 (ch1 Erectric angle Timer interrupt) Reserved INTTMR11 (ch1 Timer1 interrupt) Reserved INTTMR21 (ch1 Timer2 interrupt) Reserved INTTC1 (TC1 interrupt) INTCTC (CTC interrupt) Reserved INT2 (External interrupt 2) INT3 (External interrupt 3) INT4 (External interrupt 4) INTRX (UART receive interrupt) INTTX (UART transmit interrupt) INTSIO (SIO interrupt) INTTC3 (TC3 interrupt) INTTC4 (TC4 interrupt) Reserved INTADC (A/D converter interrupt) Enable Condition Nonmaskable Pseudo nonmaskable Pseudo nonmaskable IMF* EF3 = 1, INT0EN = 1 IMF* EF4 = 1 IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1 IMF* EF9 = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1 IMF* EF13 = 1 IMF* EF14 = 1 IMF* EF15 = 1 IMF* EF16 = 1 IMF* EF17 = 1 IMF* EF18 = 1 IMF* EF19 = 1 IMF* EF20 = 1 IMF* EF21 = 1 IMF* EF22 = 1 IMF* EF23 = 1 IMF* EF24 = 1 IMF* EF25 = 1 IMF* EF26 = 1 IMF* EF27 = 1 IMF* EF28 = 1 IMF* EF29 = 1 IMF* EF30 = 1 IMF* EF31 = 1 IMF* EF32 = 1 IMF* EF33 = 1 IMF* EF34 = 1 IMF* EF35= 1 IMF* EF36 = 1 IMF* EF37 = 1 IMF* EF38 = 1 Interrupt Latch - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 IL24 IL25 IL26 IL27 IL28 IL29 IL30 IL31 IL32 IL33 IL34 IL35 IL36 IL37 IL38 Vector Address FFFFC FFFF8 FFFF4 FFFF0 FFFEC FFFE8 FFFE4 FFFE0 FFFDC FFFD8 FFFD4 FFFD0 FFFCC FFFC8 FFFC4 FFFC0 FFFBC FFFB8 FFFB4 FFFB0 FFFAC FFFA8 FFFA4 FFFA0 FFF9C FFF98 FFF94 FFF90 FFF8C FFF88 FFF84 FFF80 FFF3C FFF38 FFF34 FFF30 FFF2C FFF28 FFF24 Priority High 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Low 38 Page 23 3. Interrupt Control Circuit 3.1 Interrupt latches (IL38 to IL2) TMP88PH41UG Note 1: To use the watchdog timer interrupt (INTWDT), clear WDTCR1 3.1 Interrupt latches (IL38 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 003CH, 003DH, 002EH, 002FH and 002BH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 should be set to "1". If the read-modifywrite instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. But interrupt latches are not set to "1" by an instruction. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LD LD LD LD LD EI (ILL), 1110100000111111B (ILH), 1110100000111111B (ILE), 1110100000111111B (ILD), 1110100000111111B (ILC), 1110100000111111B ; IMF 0 ; IL2 to IL7 0 ; IL8 to IL15 0 ; IL16 to IL23 0 ; IL24 to IL31 0 ; IL32 toIL38 0 ; IMF 1 Example 2 :Reads interrupt latches LD LD LD WA, (ILL) BC, (ILE) D, (ILC) ; W (ILH), A (ILL) ; B (ILD), C (ILE) ; D (ILC) Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump Page 24 TMP88PH41UG 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the pseudo nonmaskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Pseudo non-maskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH, 003BH, 002CH, 002DH and 002AH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled temporarily. IMF flag is set to "1" by the maskable interrupt return instruction [RETI] after executing the interrupt service program routine, and MCU can accept the interrupt again. The latest interrupt request is generated already, it is available immediately after the [RETI] instruction is executed. On the pseudo non-maskable interrupt, the non-maskable return instruction [RETN] is adopted. In this case, IMF flag is set to "1" only when it performs the pseudo non-maskable interrupt service routine on the interrupt acceptable status (IMF=1). However, IMF is set to "0" in the pseudo non-maskable interrupt service routine, it maintains its status (IMF="0"). The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". 3.2.2 Individual interrupt enable flags (EF38 to EF3) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF38 to EF3) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example :Enables interrupts individually and sets IMF DI SET CLR CLR CLR : EI ; IMF 1 (EIRL), .5 (EIRL), .6 (EIRH), .4 (EIRD), .0 ; IMF 0 ; EF5 1 ; EF6 0 ; EF12 0 ; EF24 0 Page 25 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP88PH41UG Interrupt Latches (Initial value: 0**0*0*0 *00*0000) ILH,ILL (003DH, 003CH) 15 IL15 14 13 12 IL12 11 10 IL10 9 8 IL8 7 6 IL6 5 IL5 4 3 IL3 2 IL2 1 INF 0 ILH (003DH) ILL (003CH) (Initial value: 000*00*0 *0*0*0*0) ILD,ILE (002FH, 002EH) 15 IL31 14 IL30 13 IL29 12 11 IL27 10 IL26 9 8 IL24 7 6 IL22 5 4 IL20 3 2 IL18 1 0 IL16 ILD (002FH) ILE (002EH) (Initial value: *0*00000) ILC (002BH) 7 6 IL38 5 4 IL36 3 IL35 2 IL34 1 IL33 0 IL32 ILE (002BH) Read IL38 to IL2 Interrupt latches 0: No interrupt request 1: Interrupt request 00: Out of interrupt service 01: On interrupt service of level 1 01: On interrupt service of more than level 2 01: On interrupt service of more than level 3 Write 0: Clears the interrupt request (Note1) 1: (Unable to set interrupt latch) 00: Reserved 01: Clear the nesting counter 10: Count-down 1 step for the nesting counter (Note2) 11: Reserved R/W INF Interrupt Nesting Flag Note 1: IL2 cannot alone be cleard. Note 2: Unable to detect the under-flow of counter. Note 3: The nesting counter is set "0" initially, it performs count-up by the interrupt acceptance and count-down by executing the interrupt return instruction. Note 4: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 5: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 0**0*0*0 *00*0**0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 13 12 EF12 11 10 EF10 9 8 EF8 7 6 EF6 5 EF5 4 3 EF3 2 1 0 IMF EIRH (003BH) EIRL (003AH) (Initial value: 000*00*0 *0*0*0*0) EIRD,EIRE (002DH, 002CH) 15 EF31 14 EF30 13 EF29 12 11 EF27 10 EF26 9 8 EF24 7 6 EF22 5 4 EF20 3 2 EF18 1 0 EF16 EIRD (002DH) EIRE (002CH) (Initial value: *0*00000) EIRE (002AH) 7 6 EF38 5 4 EF36 3 EF35 2 EF34 1 EF33 0 EF32 EIRE (002AH) Page 26 TMP88PH41UG EF38 to EF3 Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. R/W Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts IMF Note 1: Do not set IMF and the interrupt enable flag (EF38 to EF3) to "1" at the same time. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 27 3. Interrupt Control Circuit 3.3 Interrupt Sequence TMP88PH41UG 3.3 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 12 machine cycles (2.4 s @20 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSWH, PSWL, PCE, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 5. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. Read the RBS control code from the vector table, add its MSB(4bit) to the register bank selecter (RBS). f. Count up the interrupt nesting counter. g. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Interrupt service task 1-machine cycle Interrupt request Interrupt latch (IL) IMF Execute instruction PC Execute instruction a-1 a a+1 Execute instruction Interrupt acceptance Execute RETI instruction a b b+1 b+2 b+3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-4 n-5 n-4 n-3 n-2 n-1 n Note 1: a: Return address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 62/fc [s] at maximum (If the interrupt latch is set at the first machine cycle on 15 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Page 28 TMP88PH41UG Vector table address Entry address FFFE4H FFFE5H FFFE6H FFFE7H 45H 23H 01H 06H RBS control code Vector 12345H 12346H 12347H 12348H Interrupt service program Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. But don't use the read-modify-write instruction for EIRL(0003AH) on the pseudo non-maskable interrupt service task. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following four methods are used to save/restore the general-purpose registers. 3.3.2.1 Using Automatic register bank switcing By switching to non-use register bank, it can restore the general-purpose register at hige speed. Usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. To make up its data memory efficiency, the common bank is assigned for non-multiple intrrupt factor. It can return back to main-flow by executing the interrupt return instructions ([RETI]/[RETN]) from the current interrupt register bank automatically. Thus, no need to restore the RBS by a program. Example :Register bank switching PINTxx: (interrupt processing) RETI : VINTxx: DP DB PINTxx 1 ; PINTxx vector address setting ; RBS <- RBS + 1 RBS setting on PINTxx ; Begin of interrupt routine ; End of interrupt 3.3.2.2 Using register bank switching By switching to non-use register bank, it can restore the general-purpose register at hige speed. Usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. Page 29 3. Interrupt Control Circuit 3.3 Interrupt Sequence TMP88PH41UG Example :Register bank switching PINTxx: LD RBS, n ; RBS <- n Begin of interrupt routine (interrupt processing) RETI : VINTxx: DP DB PINTxx 0 ; PINTxx vector address setting ; RBS <- RBS + 0 RBS setting on PINTxx ; End of interrupt , restore RBS and interrupt return 3.3.2.3 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP A SP PCL PCH PSWL PSWH At acceptance of an interrupt W PCL PCH PSWL PSWH At execution of PUSH instruction SP PCL PCH PSWL PSWH At execution of POP instruction SP b-5 b-4 b-3 b-2 b-1 b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.3.2.4 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; Return Page 30 TMP88PH41UG Main task Bank m Interrupt acceptance Main task Interrupt service task Bank m Interrupt acceptance Switch to bank n by LD, RBS and n instruction Switch to bank n automatically Interrupt service task Saving registers Bank n Bank m Interrupt return Restore to bank m automatically by [RETI]/[RETN] Restoring registers Interrupt return (a) Saving/restoring by register bank changeover (b) Saving/restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI] Maskable Interrupt Return 1. The contents of the program counter and the program status word are restored from the stack. 2. The stack pointer is incremented 5 times. 3. The interrupt master enable flag is set to "1". 4. The interrupt nesting counter is decremented, and the interrupt nesting flag is changed. [RETN] Non-maskable Interrupt Return 1. The contents of the program counter and the program status word are restored from the stack. 2. The stack pointer is incremented 5 times. 3. The interrupt master enable flag is set to "1" only when a non-maskable interrupt is accepted in interrupt enable status. However, the interrupt master enable flag remains at "0" when so clear by an interrupt service program. 4. The interrupt nesting counter is decremented, and the interrupt nesting flag is changed. Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. Page 31 3. Interrupt Control Circuit 3.4 Software Interrupt (INTSW) TMP88PH41UG 3.4 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a non-maskable inerrupt is already underway, executing the SWI instruction will not generate a software interrupt but will result in the same operation as the NOP instruction. Use the SWI instruction only for detection of the address error or for debugging. 3.4.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM, DBR or SFR areas. 3.4.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. Page 32 TMP88PH41UG 3.5 External Interrupts The TMP88PH41UG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The INT0/P10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, and noise reject control and INT0/P10 pin function selection are performed by the external interrupt control register (EINTCR). Source Pin Sub-Pin Enable Conditions Release Edge (level) Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 6/fc [s] or more are considered to be signals. (at CGCR INT0 INT0 P10 IMF EF3 INT0EN=1 Falling edge INT1 INT1 P11 IMF EF5 = 1 INT2 INT2 P12/TC1 IMF EF29 = 1 Falling edge or Rising edge INT3 INT3 P21/TC3 IMF EF30 = 1 Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 24/fc [s] or more are considered to be signals.(at CGCR INT4 INT4 P22/TC4 IMF EF31 = 1 Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 6/fc [s] or more are considered to be signals. INT5 INT5 P20/STOP IMF EF15 = 1 Falling edge Note 1: In NORMAL or IDLE mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time" from the input signal's edge to set the interrupt latch. (1) INT1 pin 49/fc [s] ( at EINTCR Page 33 3. Interrupt Control Circuit 3.5 External Interrupts TMP88PH41UG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 INT4ES 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 0000 000*) INT1NC Noise reject time select 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P10 input/output port 1: INT0 pin (Port P10 should be set to an input mode) 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: H level 0: Rising edge 1: Falling edge R/W INT0EN P10/INT0 pin configuration R/W INT4 ES INT4 edge select R/W INT3 ES INT2 ES INT1 ES INT3 edge select INT2 edge select INT1 edge select R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying EINTCR Page 34 TMP88PH41UG 4. Special Function Register The TMP88PH41UG adopts the memory mapped I/O system, and all peripheral control and transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 1F80H to 1FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP88PH41UG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H TC3DRB TC3CR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TC4CR TC4DR TC3DRA Read Reserved P1DR P2DR P3DR P4DR Reserved P6DR Reserved Reserved Reserved Reserved P1CR Reserved Reserved Reserved TC1CR TC1DRAL TC1DRAH TC1DRBL TC1DRBH CTC1CR1 CTC1CR2 CTC1DRL CTC1DRH Write Page 35 4. Special Function Register 4.1 SFR TMP88PH41UG Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read ADCCRA ADCCRB ADCDRL ADCDRH EIRC ILC EIRE EIRD ILE ILD CGCR Reserved Reserved Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH PSWL PSWH Write - WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 36 TMP88PH41UG 4.2 DBR Address 1F80H 1F81H 1F82H 1F83H 1F84H 1F85H 1F86H 1F87H 1F88H 1F89H 1F8AH 1F8BH 1F8CH 1F8DH 1F8EH 1F8FH 1F90H 1F91H 1F92H 1F93H 1F94H 1F95H 1F96H 1F97H 1F98H 1F99H 1F9AH 1F9BH 1F9CH 1F9DH 1F9EH 1F9FH 1FA0H 1FA1H 1FA2H 1FA3H 1FA4H 1FA5H 1FA6H 1FA7H 1FA8H 1FA9H 1FAAH 1FABH 1FACH 1FADH 1FAEH 1FAFH for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 MCAPL MCAPH CMP1L CMP1H CMP2L CMP2H CMP3L CMP3H MDCRA MDCRB PDCRC SDREG MTCRA MTCRB - - UARTSR - RDBUF - - - SIOSR SIOBR0 SIOBR1 SIOBR2 SIOBR3 SIOBR4 SIOBR5 SIOBR6 SIOBR7 PDCRA PDCRB - PMD ch Read - - - P3ODE P4ODE - - - - P3CR P4CR - P6CR - - - UARTSEL UARTCRA UARTCRB TDBUF ATAS ATKEY SIOCR1 SIOCR2 Write Page 37 4. Special Function Register 4.2 DBR TMP88PH41UG Address 1FB0H 1FB1H 1FB2H 1FB3H 1FB4H 1FB5H 1FB6H 1FB7H 1FB8H 1FB9H 1FBAH 1FBBH 1FBCH 1FBDH 1FBEH 1FBFH 1FC0H 1FC1H 1FC2H 1FC3H 1FC4H 1FC5H 1FC6H 1FC7H 1FC8H 1FC9H 1FCAH 1FCBH 1FCCH to 1FFFH PMD ch for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 for PMD ch.1 Read EMGCRA EMGCRB MDOUTL MDOUTH MDCNTL MDCNTH MDPRDL MDPRDH CMPUL CMPUH CMPVL CMPVH CMPWL CMPWH DTR - EDCRA EDCRB EDSETL EDSETH ELDEGL ELDEGH AMPL AMPH EDCAPL EDCAPH - - Reserved : Reserved Write - - EMGREL - - WFMDR Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 38 TMP88PH41UG 5. Input/Output Ports The TMP88PH41UG contains 5 input/output ports comprised of 33 pins. Primary Function Port P1 Port P2 Port P3 Port P4 Port P6 6-bit I/O port 3-bit I/O port 8-bit I/O port 8-bit I/O port 8-bit I/O port Secondary Functions External interrupt input, Timer/counter input/output, divider output External interrupt input, Timer/counter input/output, and STOP mode release signal input Motor control input/output Timer/counter output, Serial interface input/output, motor control circuit input Analog input and motor control circuit output All output ports contain a latch, and the output data therefore are retained by the latch. But none of the input ports have a latch, so it is desirable that the input data be retained externally until it is read out, or read several times before being processed. Figure 5-1 shows input/output timing. The timing at which external data is read in from input/output ports is S1 state in the read cycle of instruction execution. Because this timing cannot be recognized from the outside, transient input data such as chattering needs to be dealt with in a program. The timing at which data is forwarded to input/output ports is S2 state in the write cycle of instruction execution. Fetch cycle S0 Instruction execution cycle S1 S2 S3 Fetch cycle S0 S1 S2 S3 S0 Read cycle S1 S2 S3 Example: LD A, (x) Input strobe Data input (a) Input timing Fetch cycle S0 Instruction execution cycle S1 S2 S3 Fetch cycle S0 S1 S2 S3 (x), A S0 Write cycle S1 S2 S3 Example: LD Output latch pulse Data output (b) Output timing Note: The read/write cycle positions vary depending on instructions. Figure 5-1 Example of Input/Output Timing Page 39 5. Input/Output Ports 5.1 Port P1 (P15 to P10) TMP88PH41UG When an operation is performed for read from any input/output port except programmable input/output ports, whether the input value of the pin or the content of the output latch is read depends on the instruction executed, as shown below. 1. Instructions which read the content of the output latch - XCH r, (src) - SET/CLR/CPL (src).b - SET/CLR/CPL (pp).g - LD (src).b, CF - LD (pp).b, CF - XCH CF, (src). b - ADD/ADDC/SUB/SUBB/AND/OR/XOR - ADD/ADDC/SUB/SUBB/AND/OR/XOR - MXOR (src), m 2. Instructions which read the input value of the pin Any instructions other than those listed above and ADD/ADDC/SUB/SUBB/AND/OR/XOR (src),(HL) instructions, the (HL) side thereof (src), n (src), (HL) instructions, the (src) side thereof 5.1 Port P1 (P15 to P10) Port P1 is an 6-bit input/output port shared with external interrupt input, timer/counter input/output, and divider output. This port is switched between input and output modes using the P1 port input/output control register (P1CR). When reset, the P1CR register is initialized to 0, with the P1 port set for input mode. Also, the output latch (P1DR) is initialized to 0 when reset. P1CRi Data input Data output Control output Control input DQ Output latch CR 01 External 0 0 0 input 1 1 0 P1i Control input values Note: i = 5 to 0 Figure 5-2 Port P1 P1 Port Input/Output Register 7 P1DR (00001H) 6 5 P15 4 P14 PPG1 3 P13 DVO 2 P12 INT2 TC1 2 1 P11 INT1 0 P10 INT0 Read/Write (Initial value: **00 0000) P1CR (0000BH) 7 6 5 4 3 1 0 (Initial value: **00 0000) Note 1: When a read instruction is excuted on P1 port, indeterminate values are read in from bits 7 to 6. Note 2: *: Don't care Page 40 TMP88PH41UG 5.2 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port shared with external interrupt input and STOP mode release signal. When using this port as these functional pins or an input port, set the output latch to 1. When reset, the output latch is initialized to 1. We recommend using the P20 pin as external interrupt input, STOP mode release signal input, or input port. When using this port as an output port, note that the interrupt latch is set by a falling edge of output pulse. And note that outputs on this port during STOP mode go to a high-impedance state even if SYSCR1 SET/CLR/CPL, etc. Data input Data output Control input DQ Output latch CMP/MCMP/TEST, etc. P20, P21, P22 Figure 5-3 Port P2 P2 Port Input/Output Registers 7 P2DR (00002H) 6 5 4 3 2 P22 TC4 INT4 PWM4 PDO4 1 P21 TC3 INT3 0 P20 INT5 STOP Read/Write (Initial value: **** *111) Note 1: When a read instruction is executed on P2 port, indeterminate values are read in from bits 7 to 3. Note 2: Port P20 is used as STOP pin. Therefore, when stop mode is started, SYCR1 Page 41 5. Input/Output Ports 5.1 Port P1 (P15 to P10) TMP88PH41UG 5.3 Port P3 (P37 to P30) Port P3 is an 8-bit input/output port. This port is switched between input and output modes using the P3 port Input/ output Control Register (P3CR). When reset, the P3CR Register is initialized to 0, with the P3 port set for input mode. Also, the Output Latch (P3DR) is initialized to 0 when reset. The P3 port contains bitwise programmable open-drain control. The P3 Port Open-drain Control Register (P3ODE) is used to select open-drain or tri-state mode for the port. When reset, the P3ODE Register is initialized to 0, with tri-state mode selected for the port. P3CRi Data input Data output Control output Control input DQ Output latch CR 01 External 0 0 0 input 1 1 0 P3i Control input values Note: i = 7 to 0 Figure 5-4 Port P3 P3 Port Input/Output Registers 7 P3DR (00003H) P3CR (01F89H) P37 CL1 6 P36 EMG1 5 P35 U1 5 4 P34 V1 4 3 P33 W1 3 2 P32 X1 2 1 P31 Y1 1 0 P30 Z1 0 (Initial value: 0000 0000) Read/Write (Initial value: 0000 0000) 7 6 P3CR P3 port input/output control (Specify bitwise) 0: Input mode 1: Output mode R/W P3ODE (01F83H) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P3ODE P3 port open-drain control (Specify bitwise) 0: Tri-state 1: Open drain R/W Note 1: Even when open-drain mode is selected, the protective diode remains connected. Therefore, do not apply voltages exceeding VDD. Note 2: Read-modify-write (RMW) operation executes at open-drain mode is selected, read out the output latch states. When any other instruction is executed, external pin states is read out. Note 3: For PMD circuit output, set the P3DR output latch to 1. Note 4: When using P3 port as an input/output port, disable the EMG1 circuit. Page 42 TMP88PH41UG 5.4 Port P4 (P47 to P40) Port P4 is an 8-bit input/output port shared with serial interface input/output. This port is switched between input and output modes using the P4 port input/output control register (P4CR). When reset, the P4CR register is initialized to 0, with the P4 port set for input mode. Also, the output latch (P4DR) is initialized to 0 when reset. The P4 port contains bitwise programmable open-drain control. The P4 port open-drain control register (P4ODE) is used to select open-drain or tri-state mode for the port. When reset, the P4ODE register is initialized to 0, with tristate mode selected for the port. P4CRi Data input Data output Control output Control input DQ Output latch CR 01 External 0 0 0 input 1 1 0 P4i Control input values Note: i = 7 to 0 Figure 5-5 Port P4 P4 Port Input/Output Registers 7 P4DR (00004H) P47 CTC 6 P46 PPG2 5 P45 SO TXD1 5 4 P44 SI RXD1 4 3 P43 SCK 2 P42 PDU1 1 P41 PDV1 0 P40 PDW1 (Initial value: 0000 0000) P4CR (01F8AH) 7 6 3 2 1 0 (Initial value: 0000 0000) P4CR P4 port input/output control (Specify bitwise) 0: Input mode 1: Output mode R/W P4ODE (01F84H) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P4ODE P4 port open-drain control (Specify bitwise) 0: Tri-state 1: Open drain R/W Note 1: Even when open-drain mode is selected, the protective diode remains connected. Therefore, do not apply voltages exceeding VDD. Note 2: Read-modify-write (RMW) operation executes at open-drain mode is selected, read out the output latch states. When any other instruction is executed, external pin states is read out. Note 3: When using the CTC 16-bit timer (CTC) as an ordinary timer, set P47 (CTC) for output mode. Page 43 5. Input/Output Ports 5.1 Port P1 (P15 to P10) TMP88PH41UG 5.5 Port P6 (P67 to P60) Port P6 is an 8-bit input/output port shared with AD converter analog input. This port is switched between input and output modes using the P6 port input/output control register (P6CR), P6 port output latch (P6DR), and ADCCRA Analog input AINDS SAIN P6CRi P6CRi input Data input (P6) Data output (P6) STOP D Q P6i Note 1: i = 7 to 0 Note 2: STOP exists in SYSCR1 register bit 7 Note 3: SAIN selects AD input channels. D Q Figure 5-6 Port P6 Page 44 TMP88PH41UG P6 Port Input/Output Registers 7 P6DR (00006H) P67 AIN7 DBOUT1 7 6 P66 AIN6 5 P65 AIN5 4 P64 AIN4 3 P63 AIN3 2 P62 AIN2 1 P61 AIN1 0 P60 AIN0 Read/Write (Initial value: 0000 0000) P6CR (01F8CH) 6 5 4 3 2 1 0 (Initial value: 0000 0000) AINDS = 1 (when not using AD) P6DR = "0" P6CR P6 port input/output control (Specify bitwise) 0 1 Inputs fixed to 0 P6DR = "1" Input mode AINDS = 0 (when using AD) P6DR = "0" Analog input mode (Note2) P6DR = "1" R/W Input mode Output mode Note 1: The pins used for analog input cannot be set for output mode (P6CR = 1) because they become shorted with external signals. Note 2: When a read instruction is executed on bits of this port which are set for analog input mode, data "0" is read in. Note 3: For DBOUT1 output, set the P6DR (P67) output latch to 1. Note 4: When using this port in input mode (including analog input), do not use bit manipulating or other read-modify-write instructions. When a read instruction is executed on the bits of this port that are set for input, the contents of the pins are read in, so that if a read-modify-write instruction is executed, their output latches may be rewritten, making the pins unable to accept input. (A read-modify-write instruction first reads data from all of the eight bits and after modifying them (bit manipulation), writes data for all of the eight bits to the output latches.) Page 45 5. Input/Output Ports 5.1 Port P1 (P15 to P10) TMP88PH41UG Page 46 TMP88PH41UG 6. Time Base Timer (TBT) and Divider Output (DVO) 6.1 Time Base Timer The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generator which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 6-2 ). The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disble from the enable state.) Both frequency selection and enabling can be performed simultaneously. MPX fc/223,fc/224 fc/221,fc/222 fc/216,fc/217 fc/214,fc/215 fc/213,fc/214 fc/212,fc/213 fc/211,fc/212 fc/29,fc/210 Source clock Falling edge detector INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 6-1 Time Base Timer configuration Source clock TBTCR INTTBT interrupt request Interrupt period Enable TBT Figure 6-2 Time Base Timer Interrupt Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET EI (EIRL) . 6 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 (Freq. set) ; TBTEN 1 (TBT enable) Page 47 6. Time Base Timer (TBT) and Divider Output (DVO) 6.1 Time Base Timer TMP88PH41UG Time Base Timer is controled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (00036H) (DVOEN) 6 (DVOCK) 5 4 0 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer Enable / Disable 0: Disable 1: Enable NORMAL, IDLE Mode DV1CK=0 000 001 fc/2 23 DV1CK=1 fc/224 fc/222 fc/217 fc/215 fc/214 fc/213 fc/212 fc/210 R/W fc/221 fc/216 fc/214 fc/213 fc/212 fc/211 fc/29 TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 Note 1: fc; High-frequency clock [Hz], *; Don't care Note 2: Always set "0" in bit4 on TBTCR register. Table 6-1 TBTCK Time Base Timer Interrupt Frequency ( Example : fc = 20.0 MHz ) Time Base Timer Interrupt Frequency [Hz] NORMAL, IDLE Mode DV1CK = 0 DV1CK = 1 1.20 4.78 153.50 610.35 1220.70 2441.40 4882.83 19531.25 000 001 010 011 100 101 110 111 2.38 9.53 305.18 1220.70 2441.40 4882.83 9765.63 39063.00 Page 48 TMP88PH41UG 6.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. Output latch Data output D Q DVO pin fc/213,fc/214 fc/212,fc/213 fc/211,fc/212 fc/210,fc/211 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 6-3 Divider Output The Divider Output is controlled by the Time Base Timer Control Register (TBTCR). Time Base Timer Control Register 7 TBTCR (00036H) DVOEN 6 DVOCK 5 4 "0" 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL, IDLE Mode DV1CK=0 DV1CK=1 fc/214 fc/213 fc/212 fc/211 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/2 13 fc/212 fc/211 fc/210 R/W Note 1: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Note 2: In case of using DVO output, set output mode by P1CR register after setting the related port output latch to "1" by P1DR register. Note 3: fc; High-frequency clock [Hz], *; Don't care Note 4: Be sure to write "0" to TBTCR Register bit 4. Page 49 6. Time Base Timer (TBT) and Divider Output (DVO) 6.2 Divider Output (DVO) TMP88PH41UG Example : 2.44 kHz pulse output (fc = 20.0 MHz) Port setting LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 6-2 Divider Output Frequency ( Example : fc = 20.0 MHz ) Divider Output Frequency [Hz] DVOCK NORMAL, IDLE Mode DV1CK=0 00 01 10 11 2.4415 k 4.8825 k 9.765 k 19.5325 k DV1CK=1 1.22075 k 2.4415 k 4.8825 k 9.765 k Page 50 TMP88PH41UG 7. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "pseudo nonmaskable interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 Watchdog Timer Configuration Reset release fc/2 ,fc/2 fc/221,fc/222 fc/219,fc/220 fc/217,fc/218 23 24 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 7-1 Watchdog Timer Configuration Page 51 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP88PH41UG 7.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 7.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 52 TMP88PH41UG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 4 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **** 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL mode DV1CK = 0 DV1CK = 1 226/fc 224/fc 222fc 220/fc Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTCR1 Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 7.2.2 Watchdog Timer Enable Setting WDTCR1 Page 53 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP88PH41UG 7.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW EI (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary coutner : WDTEN 0, WDTCR2 Disable code : IMF 1 Table 7-1 Watchdog Timer Detection Time (Example: fc = 20 MHz) Watchdog Timer Detection Time[s] WDTT DV1CK = 0 00 01 10 11 1.678 419.430 m 104.858 m 26.214 m NORMAL Mode DV1CK = 1 3.355 838.861 m 209.715 m 52.429 m Note: If the watchdog timer is disabled during watchdog timer interrupt processing, the watchdog timer interrupt will never be cleared. Therefore, clear the watchdog timer ( set the clear code (4EH) to WDTCR2 ) before disabling it, or disable the watchdog timer a sufficient time before it overflows. 7.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Page 54 TMP88PH41UG Example :Setting watchdog timer interrupt LD LD SP, 02BFH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 7.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11B) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs Write 4EH to WDTCR2 Figure 7-2 Watchdog timer Interrupt and Reset Page 55 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP88PH41UG Page 56 MCAP1 S INTTC1 interript A TC1S 8.1 Configuration Y B Start MPPG1 TC1S clear Clear PPG output mode 2 Decoder Set Q Command start Pulse width measurement mode External trigger External trigger start Rising Falling Edge detector METT1 TC1 Clear B A S Match CMP Y Source clock 16-bit up-counter Pulse width measurement mode 8. 16-Bit TimerCounter 1 (TC1) Port (Note) D Figure 8-1 TimerCounter 1 (TC1) Toggle Q Clear Selector S Q Set Capture TC1DRB TC1DRA 16-bit timer register A, B Toggle Enable Set Clear PPG output mode Internal reset Write to TC1CR TFF1 Page 57 fc/211, fc/212 A fc/27, fc/28 B Y fc/23, fc/24 C S 2 Window mode Port (Note) pin ACAP1 TC1CK TC1CR TC1 control register TMP88PH41UG Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". 8. 16-Bit TimerCounter 1 (TC1) 8.2 TimerCounter Control TMP88PH41UG 8.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register 15 TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC1DRAH (0011H) (Initial value: 1111 1111 1111 1111) TC1DRBH (0013H) (Initial value: 1111 1111 1111 1111) TC1DRAL (0010H) Read/Write TC1DRBL (0012H) Read/Write (Write enabled only in the PPG output mode) TimerCounter 1 Control Register 7 TC1CR (000FH) 6 ACAP1 MCAP1 METT1 MPPG1 5 4 3 2 1 0 TFF1 TC1S TC1CK TC1M Read/Write (Initial value: 0000 0000) TFF1 ACAP1 MCAP1 Timer F/F1 control Auto capture control Pulse width measurement mode control External trigger timer mode control PPG output control 0: Clear 0:Auto-capture disable 0:Double edge capture 1: Set 1:Auto-capture enable 1:Single edge capture R/W R/W METT1 MPPG1 0:Trigger start 0:Continuous pulse generation Timer 00: Stop and counter clear 01: Command start 10: Rising edge start (Ex-trigger/Pulse/PPG) Rising edge count (Event) Positive logic count (Window) 11: Falling edge start (Ex-trigger/Pulse/PPG) Falling edge count (Event) Negative logic count (Window) O O 1:Trigger start and stop 1:One-shot Extrigger O - Event O - Window O - Pulse O - PPG O O TC1S TC1 start control - O O O O O R/W - O O O O O NORMAL, IDLE mode DV1CK = 0 TC1CK TC1 source clock select [Hz] 00 01 10 11 fc/2 11 DV1CK = 1 fc/212 fc/28 fc/24 External clock (TC1 pin input) R/W fc/27 fc/23 TC1M TC1 operating mode select 00: Timer/external trigger timer/event counter mode 01: Window mode 10: Pulse width measurement mode 11: PPG (Programmable pulse generate) output mode R/W Note 1: fc: High-frequency clock [Hz] Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (TC1DRAH and TC1DRBH) is written. Therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only the lower byte (TC1DRAL and TC1DRBL) does not enable the setting of the timer register. Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC1CR during TC1CR Page 58 TMP88PH41UG Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other modes) Note 6: Set TC1CR Page 59 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PH41UG 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC1DRA) value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC1CR TC1CK DV1CK = 0 Resolution [s] 00 01 10 102.4 6.4 0.5 Maximum Time Setting [s] 6.7108 0.4194 26.214 m Source Clock for TimerCounter 1 (Example: fc = 20 MHz) NORMAL, IDLE Mode DV1CK = 1 Resolution [s] 204.8 12.8 0.8 Maximum Time Setting [s] 13.4216 0.8388 52.428 m Example 1 :Setting the timer mode with source clock fc/211 [Hz] and generating an interrupt 1 second later (fc = 20 MHz, CGCR LDW DI SET EI LD LD (TC1CR), 00000000B (TC1CR), 00010000B (EIRD). 2 (TC1DRA), 2625H ; Sets the timer register (1 s / 211/fc = 2625H) ; IMF= "0" ; Enables INTTC1 ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 Example 2 :Auto-capture LD : LD (TC1CR), 01010000B : WA, (TC1DRB) ; ACAP1 1 ; Wait at least one cycle of the internal source clock ; Reads the capture value Page 60 TMP88PH41UG Timer start Source clock Counter TC1DRA 0 1 2 3 4 n-1 n 0 1 2 3 4 5 6 7 ? n INTTC1 interruput request Match detect (a) Timer mode Counter clear Source clock Counter m-2 m-1 m m+1 m+2 n-1 n n+1 Capture Capture m+1 m+2 n-1 TC1DRB ? m-1 m n n+1 ACAP1 (b) Auto-capture Figure 8-2 Timer Mode Timing Chart Page 61 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PH41UG 8.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC1CR Since the TC1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width of 12/fc [s] or more is required to ensure edge detection. Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC1 pin (fc =20 MHz, CGCR LDW DI SET EI LD LD (TC1CR), 00001000B (TC1CR), 00111000B (EIRD). 2 (TC1DRA), 007DH ; 1ms / 27/fc = 7DH ; IMF= "0" ; Enables INTTC1 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC1 pin (fc =20 MHz, CGCR LDW DI SET EI LD LD (TC1CR), 00000100B (TC1CR), 01110100B (EIRD). 2 (TC1DRA), 0138H ; 4 ms / 28/fc = 0138H ; IMF= "0" ; Enables INTTC1 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 Page 62 TMP88PH41UG Count start TC1 pin input Count start At the rising edge (TC1S = 10) Source clock Up-counter 0 1 2 3 4 n-1 n 0 1 2 3 TC1DRA n Match detect Count clear INTTC1 interrupt request (a) Trigger start (METT1 = 0) At the rising edge (TC1S = 10) Count start Count clear Count start TC1 pin input Source clock Up-counter 0 1 2 3 m-1 m 0 1 2 3 n 0 TC1DRA n Match detect Count clear INTTC1 interrupt request Note: m < n (b) Trigger start and stop (METT1 = 1) Figure 8-3 External Trigger Timer Mode Timing Chart Page 63 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PH41UG 8.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC1CR Timer start TC1 pin Input Up-counter TC1DRA INTTC1 interrput request ? 0 1 2 n-1 n 0 1 2 At the rising edge (TC1S = 10) n Match detect Counter clear Figure 8-4 Event Counter Mode Timing Chart Table 8-2 Input Pulth Width to TC1 Pin Minimum Pulse Width [s] NORMAL, IDLE Mode High-going Low-going 23/fc 23/fc Page 64 TMP88PH41UG 8.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. Define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with TC1CR Count start Timer start Count stop Count start TC1 pin input Internal clock Counter TC1DRA INTTC1 interrput request ? 7 Match detect (a) Positive logic (TC1S = 10) Timer start Count start Count stop Count start 0 1 2 3 4 5 6 7 0 1 2 3 Counter clear TC1 pin input Internal clock Counter TC1DRA INTTC1 interrput request (b) Negative logic (TC1S = 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 90 1 Figure 8-5 Window Mode Timing Chart Page 65 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PH41UG 8.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC1CR Note 1: The captured value must be read from TC1DRB until the next trigger edge is detected. If not read, the captured value becomes a don't care. It is recommended to use a 16-bit access instruction to read the captured value from TC1DRB. Note 2: For the single-edge capture, the counter after capturing the value stops at "1" until detecting the next edge. Therefore, the second captured value is "1" larger than the captured value immediately after counting starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value. Page 66 TMP88PH41UG Example :Duty measurement (resolution fc/27 [Hz], CGCR CLR (INTTC1SW). 0 ; INTTC1 service switch initial setting Address set to convert INTTC1SW at each INTTC1 ; Sets the TC1 mode and source clock ; IMF= "0" (EIRD). 2 ; Enables INTTC1 ; IMF= "1" (TC1CR), 00100110B ; Starts TC1 with an external trigger at MCAP1 = 0 LD DI SET EI LD : PINTTC1: CPL JRS LD LD LD RETI SINTTC1: LD LD LD : RETI : VINTTC1: DW (TC1CR), 00000110B (INTTC1SW). 0 F, SINTTC1 A, (TC1DRBL) W,(TC1DRBH) (HPULSE), WA ; INTTC1 interrupt, inverts and tests INTTC1 service switch ; Reads TC1DRB (High-level pulse width) ; Stores high-level pulse width in RAM A, (TC1DRBL) W,(TC1DRBH) (WIDTH), WA ; Reads TC1DRB (Cycle) ; Stores cycle in RAM ; Duty calculation PINTTC1 ; INTTC1 Interrupt vector WIDTH HPULSE TC1 pin INTTC1 interrupt request INTTC1SW Page 67 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PH41UG Count start TC1 pin input Trigger Count start (TC1S = "10") Internal clock Counter TC1DRB INTTC1 interrupt request 0 1 2 3 4 n-1 n 0 1 Capture n 2 3 [Application] High-or low-level pulse width measurement (a) Single-edge capture (MCAP1 = "1") Count start TC1 pin input Count start (TC1S = "10") Internal clock Counter TC1DRB INTTC1 interrupt request [Application] (1) Cycle/frequency measurement (2) Duty measurement (b) Double-edge capture (MCAP1 = "0") 0 1 2 3 4 n+1 n n+1 n+2 n+3 Capture n m-2 m-1 m 0 1 Capture m 2 Figure 8-6 Pulse Width Measurement Mode Page 68 TMP88PH41UG 8.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC1CR Since the output level of the PPG pin can be set with TC1CR Note 1: To change TC1DRA or TC1DRB during a run of the timer, set a value sufficiently larger than the count value of the counter. Setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. Note 2: Do not change TC1CR Page 69 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PH41UG Example :Generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 20 MHz, CGCR Setting port LD LDW LDW LD (TC1CR), 10001011B (TC1DRA), 04E2H (TC1DRB), 00FAH (TC1CR), 10010111B ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 24/fc s = 04E2H) ; Sets the low-level pulse width (200 s / 24/fc = 00FAH) ; Starts the timer I/O port output latch shared with PPG output Port output enable PPG pin Data output D R Q Function output TC1CR Set Clear Toggle Q Timer F/F1 INTTC1 interrupt request TC1CR Figure 8-7 PPG Output Page 70 TMP88PH41UG Timer start Internal clock Counter 0 1 2 n n+1 m0 1 2 n n+1 m0 1 2 TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Note: m > n (a) Continuous pulse generation (TC1S = 01) Count start TC1 pin input Trigger Internal clock Counter 0 1 n n+1 m 0 TC1DRB n TC1DRA m PPG pin output INTTC1 interrupt request [Application] One-shot pulse output (b) One-shot pulse generation (TC1S = 10) Note: m > n Figure 8-8 PPG Mode Timing Chart Page 71 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PH41UG Page 72 Stop Start control Start Trigger clear CTC1S CTC1SM CTC1SE CTC1CY CTC1E 9.1 Configuration Rising edge CTC pin S A Y 9. 16-Bit Timer (CTC) B 11 12 Edge detection Falling edge fc/27 or fc/2 8 fc/25 or fc/26 fc/2 or fc/2 fc/23 or fc/24 fc/22 or fc/23 2 fc/2 or fc/2 fc or fc/2 Y Last coincidence 2 CTC1REG 3 3 Comparator Select write register CTC1DRA CTC1DRB CTC1DRC CTC1M Select read register 2 Read/Write control and clear interrupt CTC1M Interrupt 16-bit up counter H A B C D E F G Figure 9-1 CTC Block Diagram Page 73 CTC1FF0 S INTCTC1 interrupt CTC1CK CTC1S CTC1SM CTC1E Toggle Q Set Clear PPG2 pin CTC1SE CTC1CY CTC1M PPGFF0 CTC1RES CTC1CR1 CTC1REG CTC1CK CTC1FF0 EXTREGDIS 2 3 TMP88PH41UG CTC1CR2 PPGFF0 9. 16-Bit Timer (CTC) 9.2 Control TMP88PH41UG 9.2 Control Compare timer/counter 1 is controlled using Compare timer/counter 1 Control Registers (CTC1CR1 and CTC1CR2), as well as three 16-bit Timer Registers (CTC1DRA, CTC1DRB, and CTC1DRC). Compare Timer Registers (CTC1DRH: 00017h, CTC1DRL: 00016h) 15 CTC1DRA CTC1DRAH 15 CTC1DRB CTC1DRBH 15 CTC1DRC CTC1DRCH CTC1DRCL 14 13 12 11 10 9 8 7 6 5 CTC1DRBL 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 CTC1DRAL 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write only (Initial value: ******** ********) Write only Initial value: ******** ******** Write only Initial value: ******** ******** Note: CTC1DRA, CTC1DRB, and CTC1DRC are write-only registers and must not be used with any of the read-modify-write instructions such as SET, CLR, etc. Compare Timer/Counter 1 Control Registers (CTC1CR2: 00015h, CTC1CR1: 00014h) CTC1CR1 lower address CTC1CR2 upper address 7 CTC1RES 7 * 6 PPGFF0 6 EXTRGDIS 5 CTC1M 5 CTC1REG 4 CTC1CY 4 3 CTC1SE 3 2 CTC1E 2 CTC1CK 1 CTC1SM 1 0 CTC1S 0 CTC1FF0 R/W (Initial value: *0000000) R/W (Initial value: 00000000) Note 1: *: Don't care Note 2: The CTC1CR1 Page 74 TMP88PH41UG Setting-up the CTC1CR1 Register Timer CTC1S Control start 0: Stop and clear counter 1: Command start CTC1SM Select start 0: Software start 1: External trigger start 0: Enable one edge 1: Enable both edges 0: Rising edge 1: Falling edge 0: Successive 1: One shot Event x x x PPG R/W CTC1E Select external trigger edge Select external trigger start edge Select cycle CTC1SE CTC1CY CTC1M Set operation mode 0: Timer/Event counter modes 1: PPG (programmable pulse generator) output mode 0: Forward output immediately after start 1: Reverse output immediately after start 0: Normal operation 1: CTC1 reset PPGFF0 Select PPG output CTC1RES Reset all Setting-up the CTC1CR2 Register CTC1FF0 Control timer output F/F0 0: Clear 1: Set NORMAL and IDLE Modes DV1CK = 0 000 001 CTC1CK Select timer/counter clock source Unit: Hz 010 011 100 101 110 111 fc/211 fc/27 fc/25 fc/23 fc/22 fc/2 DV1CK = 1 fc/212 fc/28 fc/26 fc/24 fc/23 fc/22 R/W External clock input (CTC1 pin input) 1REG 2REG 3REG CTC1REG Set registers used by timer/ counter 00: CTC1DRA 01: CTC1DRA + CTC1DRB 10: CTC1DRA + CTC1DRB + CTC1DRC 11: Reserved 0: Enable external trigger input 1: Disable external trigger input EXTRGDIS External trigger input Note 1: fc: Clock [Hz] Note 2: Make sure the timer/counter is idle (CTC1CR1 Page 75 9. 16-Bit Timer (CTC) 9.2 Control TMP88PH41UG Note 12:The number of registers set and the values set in the timer registers must meet the conditions shown below. Number of Registers 1 Register CTC1REG 2 Register 3 Register CTC1DRA 2 Timer Register Value Conditions CTC1DRB > CTC1DRA + 1, and CTC1DRA 2 CTC1DRC > CTC1DRB + 1, CTC1DRB > CTC1DRA + 1, and CTC1DRA 2 Page 76 TMP88PH41UG 9.3 Function Compare timer/counter 1 has three modes: timer, event counter, and programmable pulse generator output modes. 9.3.1 Timer mode with software start In this mode, the timer/counter (16-bit counter) counts up synchronously with the internal clock. When the counter value and the set value of Compare Timer Register 1 (CTC1DRA) match, an INTCTC1 interrupt is generated and the counter is cleared. After the counter is cleared, it restarts and continues counting up. Table 9-1 Internal Clock Source for Compare Timer/Counter 1 (Example: fc = 20 MHz) NORMAL and IDLE Modes CTC1CK Resolution [s] 000 001 010 011 100 101 110 102.4 6.4 1.6 0.4 0.2 0.1 DV1CK = 0 Maximum Setting Time [s] 6.71 0.419 0.105 26.21 m 13.11 m 6.55 m Resolution [s] 204.8 12.8 3.2 0.8 0.4 0.2 DV1CK = 1 Maximum Setting Time [s] 13.42 0.839 0.210 52.43 m 26.21 m 13.11 m - Internal clock Counter 0 1 2 3 n-1 n 1 2 3 4 5 6 7 8 9 Timer Register A n INTCTC1 interrupt Successive Figure 9-2 Timer Mode Timing Chart Note:If the CTC input port (P47) is set for input mode, the timer/counter is reset by an input edge on port. When using the timer/counter as an ordinary timer, set CTC1CR2 Page 77 9. 16-Bit Timer (CTC) 9.2 Control TMP88PH41UG 9.3.2 Timer mode with external trigger start In this timer mode, the timer/counter starts counting as triggered by input on CTC pin (rising or falling edge selected with CTC1CR1 (I) When rising edge start is selected, with counting enabled on one edge ( CTC1SE = 0, CTC1E = 0 ) Count start Stop Trigger Count start Trigger CTC pin input Trigger Internal clock Counter Timer Register A INTCTC1 interrupt Successive Count start Count start Trigger 0 1 2 n-1 n 1 Clear 2 3 4 1 2 n CTC pin input Trigger Internal clock Counter Timer Register A INTCTC1 interrupt One Shot 0 1 2 n-1 n Stop 0 1 2 3 4 5 6 n Figure 9-3 External Trigger Mode Timing Chart Page 78 TMP88PH41UG (II) When rising start edge is selected, with counting enabled on both edges ( CTC1SE = 0, CTC1E = 1 ) Count start Count stop Trigger Count start Trigger CTC pin input Trigger Internal clock Counter Timer Register A INTCTC1 interrupt Successive Count start Count start Trigger Count clear Trigger Note) m < n 0 1 2 m 0 1 n-1 n 1 23 n CTC pin input Trigger Internal clock Counter Timer Register A INTCTC1 interrupt One Shot 0 1 2 n 0 1 2 3 4 50 1 2 3 n Figure 9-4 External Trigger Mode Timing Chart 9.3.3 Event counter mode In this mode, the timer/counter counts up at the active edge on CTC pin input (rising or falling edge selected with the CTC1CR1 When rising start edge is selected Command start CTC pin input Counter 0 1 2 n-1 n 0 1 Timer Register INTCTC1 interrupt n Figure 9-5 Event Counter Mode Timing Chart Page 79 9. 16-Bit Timer (CTC) 9.2 Control TMP88PH41UG Table 9-2 External Clock Source for Compare Timer/Counter 1 NORMAL and IDLE Modes Maximum applied frequency [Hz] Minimum pulse width Up to fc/22 22/fc and over 9.3.4 Programmable Pulse Generate (PPG) output mode The timer/counter starts counting as a command or edge on CTC pin input (rising/falling edge and one/both edges respectively selected with the CTC1CR1 Table 9-3 Internal Clock Source for Compare Timer/Counter 1 (Example: fc = 20 MHz) NORMAL and IDLE Modes CTC1CK Resolution [s] 000 001 010 011 100 101 110 102.4 6.4 1.6 0.4 0.2 0.1 DV1CK = 0 Maximum Setting Time [s] 6.71 0.419 0.105 26.21 m 13.11 m 6.55 m Resolution [s] 204.8 12.8 3.2 0.8 0.4 0.2 DV1CK = 1 Maximum Setting Time [s] 13.42 0.839 0.210 52.43 m 26.21 m 13.11 m - (I) One register used When command start, interrupt output, and counter clear are set in Timer Register A Command start CTC pin input Counter 0 1 n 1 n 1 n 1 n 1 2 3 Timer Register A n PPG2 pin output INTCTC1 interrupt Successive Figure 9-6 PPG Output Mode Timing Chart Page 80 TMP88PH41UG (II) Two registers used (CTC1REG = 01) When external trigger rising edge start, one edge enable, interrupt output, and counter clear are set in Timer Register B. Command start Stop CTC pin input Internal clock Counter 0 1 m m+1 n 1 m m+1 n 1 2 0 Timer Register A m Timer Register B n PPG2 pin output INTCTC1 interrupt Successive Command start Initial value Start CTC pin input Internal clock Counter 0 1 m m+1 n 0 1 Timer Register A m Timer Register B n PPG2 pin output INTCTC1 interrupt One shot Figure 9-7 PPG Output Two Register Mode Timing Chart Page 81 9. 16-Bit Timer (CTC) 9.2 Control TMP88PH41UG When external trigger rising edge start, both edges enable, interrupt output, and counter clear are set in Timer Register B. Command start Stop Start CTC pin input Internal clock Counter 0 1 m m+1 n 1 m 0 1 Timer Register A m Timer Register B n Initial value PPG2 pin output INTCTC1 interrupt Successive Start Start Start Start CTC pin input Internal clock Counter 0 1 m m+1 n 0 1 201 m m+1 01 m m+1 n0 Timer Register A m Timer Register B n PPG2 pin output INTCTC1 interrupt One shot Figure 9-8 PPG Output External Trigger Mode Timing Chart Page 82 TMP88PH41UG (III) Three registers used (CTC1REG = 10) When command start, interrupt output, and counter clear are set in Timer Register C. Command start CTC pin input Counter 0 1 m m+1 n n+1 s 1 m m+1 n Timer Register A m Timer Register B n Timer Register C s PPG2 pin output INTCTC1 interrupt Successive Command start Command restart CTC pin input Counter 0 1 m m+1 n n+1 s 0 1 m m+1 Timer Register A m Timer Register B n Timer Register C s PPG2 pin output INTCTC1 interrupt One shot Note: In the single-shot mode, the PPG pin output is not toggled at the last register match; it stays at the value specified with CTC1CR2 Figure 9-9 PPG Output Three Register Mode Timing Chart Page 83 9. 16-Bit Timer (CTC) 9.2 Control TMP88PH41UG Detail operation at start that varies depending on how CTC1CR2 CTC1FF0 setting (write to CTC1CR1 Register) Command start or trigger start Internal clock CTC1FF0 = 0 PPGFF0 = 0 Counter 0 1 2 3 n n+1 n+2 n+3 PPG output CTC1FF0 setting (write to CTC1CR1 Register) Command start or trigger start Internal clock CTC1FF0 = 1 PPGFF0 = 0 Counter 0 1 2 3 n n+1 n+2 n+3 PPG output CTC1FF0 setting (write to CTC1CR1 Register) Command start or trigger start Internal clock CTC1FF0 = 0 PPGFF0 = 1 Counter 0 1 2 3 n n+1 n+2 n+3 PPG output CTC1FF0 setting (write to CTC1CR1 Register) Command start or trigger start Internal clock CTC1FF0 = 1 PPGFF0 = 1 Counter 0 1 2 3 n n+1 n+2 n+3 PPG output By changing the port-shared output for PPG output before the counter starts counting after setting CTC1CR2 Page 84 TMP88PH41UG 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration Falling INTTC3 interrupt Clear Edge detector Rising TC3 pin TC3S Port (Note) fc/213, fc/2 14 fc/212, fc/2 13 fc/211 , fc/2 12 fc/210, fc/2 11 fc/2 9 , fc/210 fc/2 8 , fc/2 9 fc/2 7 , fc/2 8 H AY B C D E F G S 3 Source clock 8-bit up-counter Overflow detect TC3S CMP Match detect A B S Y TC3DRB Capture TC3DRA Capture 8-bit timer register TC3CK TC3M TC3CR TC3 contorol register Note: Function input may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 10-1 TimerCounter 3 (TC3) ACAP TC3S Page 85 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP88PH41UG 10.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TC3DRA and TC3DRB). Timer Register and Control Register TC3DRA (001CH) TC3DRB (001DH) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) Read only (Initial value: 1111 1111) TC3CR (001EH) 7 6 ACAP 5 4 TC3S 3 2 TC3CK 1 0 TC3M (Initial value: *0*0 0000) ACAP Auto capture control 0: - 1: Auto capture 0: Stop and counter clear 1: Start NORMAL, IDLE mode DV1CK=0 000 001 fc/2 13 R/W TC3S TC3 start control R/W DV1CK=1 fc/214 fc/213 fc/212 fc/211 fc/210 fc/29 fc/28 R/W fc/212 fc/211 fc/210 fc/29 fc/28 fc/27 External clock (TC3pin input) TC3CK TC3 source clock select [Hz] 010 011 100 101 110 111 TC3M TC3 operating mode select 0: Timer/event counter mode 1: Capture mode R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: Set the operating mode and source clock when TimerCounter stops (TC3CR Page 86 TMP88PH41UG 10.3 Function TimerCounter 3 has three types of operating modes: timer, event counter and capture modes. 10.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 3A (TC3DRA) value is detected, an INTTC3 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC3CR Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB. (Figure 10-2) Clock TC3DRA Up-counter Match detect C8 C6 C7 C8 00 01 TC3DRB C6 C7 C8 01 Note: In the case that TC3DRB is C8H Figure 10-2 Auto-Capture Function Table 10-1 Source Clock for TimerCounter 3 (Example: fc = 20 MHz) TC3CK DV1CK = 0 Resolution [s] 000 001 010 011 100 101 110 409.6 204.8 102.4 51.2 25.6 12.8 6.4 Maximum Time Setting [ms] 104.45 52.22 26.11 13.06 6.53 3.06 1.63 Resolution [s] 819.2 409.6 204.8 102.4 51.2 25.6 12.8 NORMAL, IDLE mode DV1CK = 1 Maximum Time Setting [ms] 208.90 104.45 52.22 26.11 13.06 6.53 3.06 Page 87 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP88PH41UG Timer start Source clock Counter 0 1 2 3 4 n0 1 2 3 4 5 6 7 TC3DRA INTTC3 interrupt ? n Match detect Counter clear (a) Timer mode Source clock Counter m m+1 m+2 n n+1 Capture Capture m+1 m+2 n TC3DRB ? m n+1 TC3CR Figure 10-3 Timer Mode Timing Chart Page 88 TMP88PH41UG 10.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC3 pin. When a match between the up-counter and TC3DRA value is detected, an INTTC3 interrupt is generated and up-counter is cleared. After being cleared, the up-counter restarts counting at each rising edge of the input pulse to the TC3 pin. Since a match is detected at the falling edge of the input pulse to TC3 pin, an INTTC3 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC3DRA. The maximum applied frequencies are shown in Table 10-2. The pulse width larger than one machine cycle is required for high-going and low-going pulses. Setting TC3CR Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB. (Figure 10-2) Example :Inputting 50 Hz pulse to TC3, and generating interrupts every 0.5 s LD LD LD (TC3CR), 00001110B (TC3DRA), 19H (TC3CR), 00011110B : Sets the clock mode : 0.5 s / 1/50 = 25 = 19H : Starts TC3. Table 10-2 Maximum Frequencies Applied to TC3 Minimum Pulse Width NORMAL, IDLE mode High-going Low-going 22/fc 22/fc Timer start TC3 pin input Counter 0 1 2 3 n 0 1 2 3 Match detect Counter clear TC3DRA n INTTC3 interrupt Figure 10-4 Event Counter Mode Timing Chart Page 89 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP88PH41UG 10.3.3 Capture Mode In the capture mode, the pulse width, frequency and duty cycle of the pulse input to the TC3 pin are measured with the internal clock. The capture mode is used to decode remote control signals, and identify AC50/60 Hz. When the falling edge of the TC3 input is detected after the timer starts, the up-counter value is captured into TC3DRB. Hereafter, whenever the rising edge is detected, the up-counter value is captured into TC3DRA and the INTTC3 interrupt request is generated. The up-counter is cleared at this time. Generally, read TC3DRB and TC3DRA during INTTC3 interrupt processing. After the up-counter is cleared, counting is continued and the next up-counter value is captured into TC3DRB. When the rising edge is detected immediately after the timer starts, the up-counter value is captured into TC3DRA only, but not into TC3DRB. The INTTC3 interrupt request is generated. When the read instruction is executed to TC3DRB at this time, the value at the completion of the last capture (FF immediately after a reset) is read. The minimum input pulse width must be larger than one cycle width of the source clock programmed in TC3CR Timer start TC3CR Source clock Counter TC3 pin input 0 1 i-1 i i+1 k-1 k 0 1 m-1 m m+1 n-1 n 0 1 2 3 FE FF 0 1 2 3 Internal waveform Capture TC3DRA TC3DRB INTTC3 interrupt request Read of TC3DRA Capture i k Capture m Capture n Capture FF (Overflow) FE Overflow Figure 10-5 Capture Mode Timing Chart Page 90 TMP88PH41UG 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TC4S fc/211, fc212 fc/27, fc28 fc/25, fc26 fc/23, fc24 fc/22, fc23 fc/2, fc22 fc, fc/2 (Note) A B Source C Clock Clear D EY Y 8-bit up-counter F G H S 3 CMP Overflow detect 0 1 Match detect Y S TC4 pin Timer F/F TC4CK Toggle Port (Note) TC4S TC4M 2 0 Y 1 Clear S PWM output mode PWM4/ PDO4/ pin TC4CR TC4DR TC4S INTTC4 interrupt PDO mode Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 11-1 TimerCounter 4 (TC4) Page 91 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP88PH41UG 11.2 TimerCounter Control The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and timer registers 4 (TC4DR). Timer Register and Control Register TC4DR (001BH) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) TC4CR (001AH) 7 6 5 TC4S 4 3 TC4CK 2 1 TC4M 0 Read/Write (Initial value: **00 0000) TC4S TC4 start control 0: Stop and counter clear 1: Start NORMAL, IDLE mode DV1CK = 0 000 001 fc/2 11 R/W DV1CK = 1 fc/212 fc/28 fc/26 fc/24 fc/23 fc/22 (fc/2)Note8 R/W fc/27 fc/25 fc/23 fc/22 fc/2 (fc)Note8 TC4CK TC4 source clock select [Hz] 010 011 100 101 110 111 External clock (TC4 pin input) TC4M TC4 operating mode select 00: Timer/event counter mode 01: Reserved 10: Programmable divider output (PDO) mode 11: Pulse width modulation (PWM) output mode R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: To set the timer registers, the following relationship must be satisfied. 1 TC4DR 255 Note 3: To start timer operation (TC4CR Timer Mode 000 001 010 TC4CK 011 100 101 110 111 O O O O - - - - Event Counter Mode - - - - - - - O PDO Mode O O O - - - - - PWM Mode - - - O O O O x Note: O : Available source clock Page 92 TMP88PH41UG 11.3 Function TimerCounter 4 has four types of operating modes: timer, event counter, programmable divider output (PDO), and pulse width modulation (PWM) output modes. 11.3.1 Timer Mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Table 11-1 Internal Source Clock for TimerCounter 4 (Example: fc = 20 MHz) TC4CK DV1CK = 0 Resolution [s] 000 001 010 011 102.4 6.4 1.6 0.4 Maximum Time Setting [ms] 26.11 1.63 0.41 0.10 Resolution [s] 204.8 12.8 3.2 0.8 NORMAL, IDLE Mode DV1CK = 1 Maximum Time Setting [ms] 52.22 3.28 0.82 0.20 11.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC4 pin. When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC4 pin. Since a match is detected at the falling edge of the input pulse to the TC4 pin, the INTTC4 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC4DR. The minimum pulse width applied to the TC4 pin are shown in Table 11-2. The pulse width larger than two machine cycles is required for high- and low-going pulses. Note:The event counter mode can used in the NORMAL and IDLE modes only. Table 11-2 External Source Clock for TimerCounter 4 Minimum Pulse Width NORMAL, IDLE mode High-going Low-going 23/fc 23/fc 11.3.3 Programmable Divider Output (PDO) Mode The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by counting with the internal clock. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PDO4 pin is switched to the opposite state and INTTC4 interrupt request is generated. The up-counter is cleared at this time and then counting is continued. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PDO4 pin is switched to the opposite state again and INTTC4 interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued. When the timer is stopped, the PDO4 pin is high. Therefore, if the timer is stopped when the PDO4 pin is low, the duty pulse may be shorter than the programmed value. Page 93 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP88PH41UG Example :Generating 1024 Hz pulse (fc = 20.0 Mhz and CGCR LD SET LD LD (TC4CR), 00000110B (P2DR), 2 (TC4DR), 4CH (TC4CR), 00100110B : Sets the PDO mode. (TC4M = 10, TC4CK = 001) : Sets the P22 output latch to 1. : 1/1024 / 27/fc / 2 (half cycle period) = 4CH : Start TC4 Internal clock Counter 0 1 2 n0 1 2 n0 1 2 n0 1 2 n0 1 TC4DR n Match detect Timer F/F PDO4 pin INTTC4 interrupt request Figure 11-2 PDO Mode Timing Chart 11.3.4 Pulse Width Modulation (PWM) Output Mode The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of resolution by an internal clock. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PWM4 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM4 pin becomes high. The INTTC4 interrupt request is generated at this time. When the timer is stopped, the PWM4 pin is high. Therefore, if the timer is stopped when the PWM4 pin is low, one PMW cycle may be shorter than the programmed value. TC4DR is serially connected to the shift register. If TC4DR is programmed during PWM output, the data set to TC4DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically. For the first time, the data written to TC4DR is shifted when the timer is started by setting TC4CR Note 1: The PWM output mode can be used only in the NORMAL and IDEL modes. Note 2: In the PWM output mode, program TC4DR immediately after the INTTC4 interrupt request is generated (typically in the INTTC4 interrupt service routine.) When the programming of TC4DR and the INTTC4 interrupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is issued. Page 94 TMP88PH41UG TC4CR Internal clock Counter 0 1 n n+1 FF 0 1 n n+1 FF 0 1 m Rewrite TC4DR ? n m Rewrite p Rewrite Data shift m Data shift Shift register ? n Data shift Match detect Timer F/F Match detect Match detect PWM4 pin INTTC4 interrupt request n n m PWM cycle Figure 11-3 PWM output Mode Timing Chart (TC4) Table 11-3 PWM Mode (Example: fc = 20 MHz) TC4CK DV1CK = 0 Resolution [ns] 000 001 010 011 100 101 110 - - - 400 200 100 - Cycle [s] - - - 102.4 51.2 25.6 - NORMAL, IDLE Mode DV1CK = 1 Resolution [ns] - - - 800 400 200 - Cycle [s] - - - 204.8 102.4 51.2 - Page 95 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP88PH41UG Page 96 TMP88PH41UG 12. Motor Control Circuit (PMD: Programmable motor driver) The TMP88PH41UG contains one channel of motor control circuits used for sinusoidal waveform output. This motor control circuit can control brushless DC motors or AC motors with or without sensors. With its primary functions like those listed below incorporated in hardware, it helps to accomplish sine wave motor control easily, with the software load significantly reduced. 1. Rotor position detect function * Can detect the rotor position, with or without sensors * Can be set to determine the rotor position when detection matched a number of times, to prevent erroneous detection * Can set a position detection inhibit period immediately after PWM-on 2. Independent timer and timer capture functions for motor control * Contains one-channel magnitude comparison timer and two-channel coincidence comparison timers that operate synchronously for position detection 3. PWM waveform generating function * Generates 12-bit PWM with 100 ns resolution * Can set a frequency of PWM interrupt occurrence * Can set the dead time at PWM-on 4. Protective function * Provides overload protective function based on protection signal input 5. Emergency stop function in case of failure * Can be made to stop in an emergency by EMG input or timer overflow interrupt * Not easily cleared by software runaway 6. Auto commutation/Auto position detection start function * Comprised of dual-buffers, can activate auto commutation synchronously with position detection or timer * Can set a position detection period using the timer function and start auto position detection at the set time 7. Electrical angle timer function * Can count 360 degrees of electrical angle with a set period in the range of 0 to 383 * Can output the counted electrical angle to the waveform arithmetic circuit 8. Waveform arithmetic circuit * Calculate the output duty cycle from the sine wave data and voltage data which are read from the RAM based on the electrical angle timer * Output the calculation result to the waveform synthesis circuit Page 97 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.1 Outline of Motor Control The following explains the method for controlling a brushless DC motor with sine wave drive. In a brushless DC motor, the rotor windings to which to apply electric current are determined from the rotor's magnetic pole position, and the current-applied windings are changed as the rotor turns. The rotor's magnetic pole position is determined using a sensor such as a hall IC or by detecting polarity change (zero-cross) points of the induced voltage that develops in the motor windings (sensorless control). For the sensorless case, the induced voltage is detected by applying electric current to two phases and not applying electric current to the remaining other phase. In this two-phase current on case, there are six current application patterns as shown in Table 12-1, which are changed synchronously with the phases of the rotor. In this two-phase current on case, the current on time in each phase is 120 degrees relative to 180 degrees of the induced voltage. Table 12-1 Current Application Patterns Current Application Pattern Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Upper Transistor u ON ON OFF OFF OFF OFF v OFF OFF ON ON OFF OFF w OFF OFF OFF OFF ON ON x OFF OFF OFF ON ON OFF Lower Transistor Current on Winding y ON OFF OFF OFF OFF ON z OFF ON ON OFF OFF OFF UV UW VW VU WU WV Note: One of the upper or lower transistors is PWM controlled. For brushless DC motors, the number of revolutions is controlled by an applied voltage, and the voltage application is controlled by PWM. At this time, the current on windings need to be changed in synchronism with the phases of the voltage induced by revolutions. Control timing in cases where the current on windings are changed by means of sensorless control is illustrated in Figure 12-4. For three-phase motors, zero-crossing occurs six times during one cycle of the induced voltage (electrical angle 360 degrees), so that the electrical angle from one zero-cross point to the next is 60 degrees. Assuming that this period comprises one mode, the rotor position can be divided into six modes by zero-cross points. The six current application patterns shown above correspond one for one to these six modes. The timing at which the current application patterns are changed (commutation) is out of phase by 30 degrees of electrical angle, with respect to the position detection by an induced voltage. Mode time is obtained by detecting a zero-cross point at some timing and finding an elapsed time from the preceding zero-cross point. Because mode time corresponds to 60 degrees of electrical angle, the following applies for the case illustrated in Figure 12-4. 1. Current on windings changeover (commutation) timing 30 degrees of electrical angle = mode time/2 2. Position detection start timing 3. Failure determination timing 45 degrees of electrical angle = mode time x 3/4 120 degrees of electrical angle = mode time x 2 Timings are calculated in this way. The position detection start timing in 2 is needed to prevent erroneous detection of the induced voltage for reasons that even after current application is turned off, the current continues flowing due to the motor reactance. Control is exercised by calculating the above timings successively for each of the zero-cross points detected six times during 360 degrees of electrical angle and activating commutation, position detection start, and other operations according to that timing. In this way, operations can be synchronized to the phases of the induced voltage of the motor. The timing needed for motor control as in this example can be set freely as desired by using the internal timers of the microcontroller's PMD unit. Also, sine wave control requires controlling the PWM duty cycle for each pulse. Control of PWM duty cycles is accomplished by counting degrees of electrical angle and calculating the sine wave data and voltage data at the counted degree of electrical angle. Page 98 TMP88PH41UG MCU Speed control Error handling, etc. PMD circuit Three-phase PWM Protective control Position detection Electrical angle timer Waveform calculation DC current U, V, W, X, Y, Z CL, EMG PDU, PDV, PDW DC motor Power drive Upper phase: u, v, w Lower phase: x, y, z Figure 12-1 Conceptual Diagram of DC Motor Control Mode Induced voltage Six-phase output 0 1 Zero crossing 2 U phase 3 4 V phase 5 W phase U phase H V phase W phase X phase Y phase Z phase Position detection Commutation Position detection start Failure determination Internal signal 60 30 45 120 L Figure 12-2 Example of Sensorless DC Motor Control Timing Chart Page 99 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.2 Configuration of the Motor Control Circuit The motor control circuit consists of various units. These include a position detection unit to detect the zero-cross points of the induced voltage or position sensor signal, a timer unit to generate events at three instances of electrical angle timing, and a three-phase PWM output unit to produce three-phase output PWM waveforms. Also included are an electrical angle timer unit to count degrees of electrical angle and a waveform arithmetic unit to calculate sinusoidal waveform output duty cycles. The input/output units are configured as shown in the diagram below. When using ports for the PMD function, set the Port input/output control register (P3CRi) to 0 for the input ports, and for the output ports, set the data output latch (P3i) to 1 and then the port input/output control register to 1. Other input/output ports can be set in the same way for use of the PMD function. CPU core Data and address buses Motor control circuit Timer circuit Electrical angle timer circuit Waveform generation circuit Waveform arithmetic circuit Position detection circuit Position signal input Error detection input U, V, W, X, Y, Z Figure 12-3 Block Diagram of the Motor Control Circuit Note 1: Always use the LDW instruction to set data in the 9, 12 and 16-bit data registers. Note 2: The EMG circuit initially is enabled. For PMD output, fix the EMG input port (P36) "H" high level or disable the EMG circuit before using for PMD output. Note 3: The EMG circuit initially is enabled. When using Port P3 as input/output IO ports, disable EMG. Note 4: When going to STOP mode, be sure to turn all of the PMD functions off before entering STOP mode. Page 100 TMP88PH41UG 12.3 Position Detection Unit The Position Detection Unit identifies the motor's rotor position from input patterns on the position signal input port. Applied to this position signal input port is the voltage status of the motor windings for the case of sensorless DC motors or a Hall element signal for the case of DC motors with sensors included. The expected patterns corresponding to specific rotor positions are set in the PMD Output Register (MDOUT) beforehand, and when the input position signal and the expected value match as the rotation, a position detection interrupt (INTPDC) is generated. Also, unmatch detection mode is used to detect the direction of motor rotation, where when the status of the position detection input port changes from the status in which it was at start of sampling, a position detection interrupt is generated. For three-phase brushless DC motors, there are six patterns of position signals, one for each mode, as summarized in Table 12-2 from the timing chart in Figure 12-2. Once a predicted position signal pattern is set in the MDOUT register, a position detection interrupt is generated the moment the position signal input port goes to mode indicated by this expected value. The position signals at each phase in the diagram are internal signals which cannot be observed from the outside. Table 12-2 Position Signal Input Patterns Position Detection Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 U Phase (PDU) H H H L L L V Phase (PDV) L L H H H L W Phase (PDW) H L L L H H Page 101 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.3.1 Configuration of the position detection unit PMD output register MDOUT - E,D,C - - - - Position signal expected value Position signal input PDNUM PDU Latch PDV PDW Clock selector 2 Sampling control Latch MDOUTsync Coincidence detection Erroneous detection prevention circuit Counter Position detection interrupt INTPDC fc/4 Sampling control circuit Reset control 4 2 Timer interrupt INTTMR2/3 PWMON Delay circuit SDREG Sampling delay set register -, 6, 5, 4, 3, 2, 1, 0 7, 6 5, 4 3, 2, 1, 0 7, 6, 5, 4 3 2 1 0 PDCRA PDCRB Position detection control register Figure 12-4 Configuration of the Position Detection Circuit * The position detection unit is controlled by the Position Detection Control Register (PDCRA, PDCRB). After the position detection function is enabled, the unit starts sampling the position detection port with Timer 2 or in software. For the case of ordinary mode, when the status of the position detection input port matches the expected value of the PMD Output Register, the unit generates a position detection interrupt and finishes sampling, waiting for start of the next sampling. * When unmatch detection mode is selected for position detection, the unit stores the sampled status of the position detection port in memory at the time it started sampling. When the port input status changes from the status in which it was at start of sampling, an interrupt is generated. * In unmatch detection mode, the port status at start of sampling can be read (PDCRC Page 102 TMP88PH41UG * A sampling delay is provided for use in modes where sampling is made while PWM is on or the lower phases are conducting current. It helps to prevent erroneous detection due to noise that occurs immediately after the transistor turns on, by starting sampling a set time after the PWM signal turned on. * When detecting position while PWM is on or the lower phases are conducting current, a method can be selected whether to recount occurrences of matched position detection after being compared for each PWM signal on (logical sum of three-phase PWM signals) (e.g., starting from 0 in each PWM cycle) or counting occurrences of matching continuously ( PDCRB 12.3.2 Position Detection Circuit Register Functions PDCRC Hold result of position detection at PWM edge (Detect position detected position) Monitor sampling status Hold position signal input status These bits hold the comparison result of position detection at falling or rising edge of PWM pulse. Bits 5 and 4 are set to 1 when position is detected at the falling or the rising edge, respectively. They show whether position is detected in the current PWM pulse, during PWM off, or in the immediately preceding PWM pulse. When read, this bit shows the sampling status. This bit holds the status of the position signal input at the time position detection started in unmatch mode. 5, 4 EMEM 3 2 to 0 SMON PDTCT PDCRB 7, 6 SPLCK Sampling period Select fc/22, fc/23, fc/24, or fc/25 for the position detection sampling period. Select one of three modes: sampling only when PWM signal is active (when PWM is on), sampling regularly, or sampling when the lower side (X, Y, Z) phases are conducting current. In ordinary mode, when the port status and the set expected value match and continuously match as many times as the sampling counts set, a position detection signal is output and an interrupt is generated. In unmatch detection mode, when the said status and value do not match and continuously unmatch as many times as the sampling counts set, a position detection signal is output and an interrupt is generated. 5, 4 SPLMD Sampling mode 3 to 0 PDCMP Sampling count PDCRA Sampling can be stopped in software by setting this bit to 1 (e.g., by writing to this register). Sampling is performed before stopping and when position detection results match, a position detection interrupt is generated, with sampling thereby stopped. Sampling can be started by setting this bit to 1 (e.g., by writing to this register). Sampling can be stopped by a trigger from Timer 3 by setting this bit to 1. Sampling is performed before stopping and when position detection results match, a position detection interrupt is generated, with sampling thereby stopped. Sampling can be started by a trigger from Timer 3 by setting this bit to 1. Select whether to use three pins (PDU/PDV/PDW) or one pin (PDU only) for position signal input. When one pin is selected, the expected values of PDV and PDW are ignored. When performing position detection with two pins or a pin other than PDU, position signal input can be masked as 0 by setting unused pin(s) for output. When performing sampling while PWM is on, occurrences of matching are recounted each time PWM signal turns on by setting this bit to 1 (when recounting occurrences of matching, the count is reset each time PWM turns off). When this bit is set to 0, occurrences of matching are counted continuously regardless PWM interval. Setting this bit to 0 selects ordinary mode where position is detected when the expected value set in the register and the port input unmatch and then match. Setting this bit to 1 selects unmatch detection mode where position is detected at the time the port status changes to another one from the status in which it was when sampling started. The position detection function is activated by setting this bit to 1. 7 SWSTP Stop sampling in software 6 SWSTT Start sampling in software 5 SPTM3 Stop sampling using Timer 3 4 STTM2 Start sampling using Timer 2 3 PDNUM Number of position signal input pins 2 RCEN Recount occurrences of matching when PWM is on 1 DTMD Position detection mode 0 PDCEN Position detection function Page 103 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG SDREG Set a time for which to stop sampling in order to prevent erroneous detection due to noise that occurs immediately after PWM output turns on (immediately after the transistor turns on). (Figure 12-5) 6 to 0 SDREG Sampling delay PWMON period PWM ON OFF Position detection match Sampling period Sampling delay Sampling pause Align the arrow to the start of counter switching. Number of position detection matches (n = 5) Match 0 1 2 3 4 5 0 Figure 12-5 Position Detection Sampling Timing with the PWMON Period Selected EMEM: Detects when a position detection match has occurred (the value is held aftr position detection). (Check on whether sampling has started on the previous pulse) PWM CASE1 CASE2 CASE3 CASE4 ON OFF EMEM value 11 01 10 00 1 Match (Sampling start) 1 1 0 0 0 0 1 11 A match with n = 5 means that it has started on the previous pulse. 01 00 10 Erroneous detection Figure 12-6 Detection Timing of the Position Detection Position Page 104 TMP88PH41UG Position Detection Circuit Registers [Addresses (PMD1)] PDCRC (01FA2H) 7 - 6 - 5 EMEM 4 3 SMON 2 1 PDTCT 0 (Initial value: **00 0000) 5, 4 EMEM Hold result of position detection at PWM edge (Detect position detected position) 00: Detected in the current pulse 01: Detected while PWM off 10: Detected in the current pulse 11: Detected in the preceding pulse 0: Sampling idle 1: Sampling in progress Holds the status of the position signal input during unmatch detection mode. Bits 2 to 0 correspond to W, V, and U phases. R 3 SMON Monitor sampling status Hold position signal input status 2 to 0 PDTCT PDCRB (01FA1H) 7 SPLCK 6 5 SPLMD 4 3 2 PDCMP 1 0 (Initial value: 0000 0000) 00: fc/22 [Hz] (200 ns at 20 MHz) 7, 6 SPLCK Select sampling input clock 01: fc/23 10: fc/24 11: fc/25 (400 ns at 20 MHz) (800 ns at 20 MHz) (1.6 s at 20 MHz) R/W 5, 4 SPLMD Sampling mode 00: Sample when PWM is on 01: Sample regularly 10: Sample when lower phases conducting current 11: Reserved 1 to 15 times (Counts 0 and 1 are assumed to be one time.) 3 to 0 PDCMP Position detection matched counts Note: When changing setting, keep the PDCEN bit reset to "0" (disable position detection function). PDCRA (01FA0H) 7 SWSTP 6 SWSTT 5 SPTM3 4 STTM2 3 PDNUM 2 RCEN 1 DTMD 0 PDCEN (Initial value: 0000 0000) 7 SWSTP Stop sampling in software 0: No operation 1: Stop sampling W 0: No operation 1: Start sampling 0: Disable 1: Enable 0: Disable 1: Enable 0: Compare three pins (PDU/PDV/PDW) 1: Compare one pin (PDU) only R/W 0: Continue counting from previously PWM on 1: Recount each time PWM turns on 0: Ordinary mode 1: Unmatch detection mode 0: Disable 1: Enable (Sampling starts) 6 SWSTT Start sampling in software 5 SPTM3 Stop sampling using Timer 3 4 STTM2 Start sampling using Timer 2 Number of position signal input pins Recount occurrences of matching when PWM is on Position detection mode Enable/Disable position detection function 3 PDNUM 2 RCEN 1 DTMD 0 PDCEN Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the PDCRA because it contains a write only bit. Page 105 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG SDREG (01FA3H) 7 - 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: *000 0000) 6 to 0 SDREG Sampling delay 23/fc x n bits (n = 0 to 6, maximum 50.8 s, resolution of 400 ns at 20 MHz) R/W Note: When changing setting, keep the PDCEN bit reset to "0" (disable position detection function). 12.3.3 Outline Processing in the Position Detection Unit Software Set mode pattern Hardware Write expected value MDOUT (E, D, C) Start position detection Sample position signal input Match with expected value? Yes Increment matching counts Specified count reached? No No INTTMR2 Timer unit Interrupt handling Increment mode counts INTPDC Yes Generate INTPDC interrupt End of position detection Page 106 TMP88PH41UG 12.4 Timer Unit Mode timer control registers MTCRA 7, 6, 5 4, 3, 2, 1 0 Overflow 4 fc/4 Clock selector Mode timer Timer reset control circuit Debug output - 3 7 MTCRB 5 - 3, 2, 1 3 Capture overwrite Capture control circuit Capture Overload protective interrupt INTCLM Position detection interrupt INTPDC MCAP F to 0 Mode capture register Timer 1 interrupt INTTMR1 (Commutation) CMP1 F to 0 Timer compare register Timer 1 magnitude comparison Timer 2 interrupt INTTMR2 (Position detection start) CMP2 F to 0 Timer 2 matching comparison CMP3 F to 0 Timer 3 matching comparison Timer 3 interrupt INTTMR3 (Overflow) Figure 12-7 Timer Circuit Configuration The timer unit has an up counter (mode timer) which is cleared by a position detection interrupt (INTPDC). Using this counter, it can generate three types of timer interrupts (INTTMR1 to 3). These timer interrupts may be used to produce a commutation trigger, position detection start trigger, etc. Also, the mode timer has a capture function which automatically captures register data in synchronism with position detection or overload protection. This capture function allows motor revolutions to be calculated by measuring position detection intervals. Page 107 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.4.1 Configuration of the Timer Unit The timer unit consists mainly of a mode timer, three timer comparator, and mode capture register, and is controlled by timer control registers and timer compare registers. * The mode timer can be reset by a signal from the position detection circuit, Timer 3, or overload protective circuit. If the mode timer overflows without being reset, it stops at FFFFH and sets an overflow flag in the control register. * The value of the mode timer during counting can be read by capturing the count in software and reading the capture register. * Timer 1 and Timers 2 and 3 generate an interrupt signal by magnitude comparison and matching comparison, respectively. Therefore, Timer 1 can generate an interrupt signal even when it could not write to the compare register in time and the counter value at the time of writing happens to exceed the register's set value. * When any one of Timers 1 to 3 interrupts occurs, the next interrupts can be enabled by writing a new value to the respective compare registers (CMP1, CMP2, CMP3). * When capturing by position detection is enabled, the capture register has the timer value captured in it each time position is detected. In this way, the capture register always holds the latest value. Page 108 TMP88PH41UG 12.4.1.1 Timer Circuit Register Functions MTCRB Debug output can be produced by setting this bit to 1. Because interrupt signals to the interrupt control circuit are used for each interrupt, hardware debugging without software delays are possible. See the debug output diagram (Figure 12-8). Output ports: P67 for PMD1. This bit shows that the timer has overflowed. When this bit is set to 1, the timer value can be captured using the overload protection signal (CL) as a trigger. When this bit is set to 1, the timer value can be captured in software (e.g., by writing to this register). When this bit is set to 1, the timer value can be captured using the position detection signal as a trigger. 7 DBOUT Debug output 5 3 TMOF CLCP Mode timer overflow Capture mode timer by overload protection Capture mode timer in software Capture mode timer by position detection 2 SWCP 1 PDCCP MTCRA 7, 6, 5 4 TMCK RBTM3 Select clock Reset mode timer from Timer 3 Reset mode timer by overload protection Reset mode timer in software Reset mode timer by position detection Select the timer clock. When this bit is set to 1, the mode timer is reset by a trigger from Timer 3. When this bit is set to 1, the mode timer is reset by the overload protection signal (CL) as a trigger. When this bit is set to 1, the mode timer is reset in software (e.g., by writing to this register) When this bit is set to 1, the mode timer is reset by the position detection signal as a trigger. The mode timer is started by setting this bit to 1. Therefore, Timers 1 to 3 must be set with CMP before setting this bit. If this bit is set to 0 after setting CMP, CMP settings become ineffective. 3 RBCL 2 SWRES 1 RBPDC 0 TMEN Enable/disable mode timer MCAP Mode capture Position detection interval can be read out. CMP1 CMP2 CMP3 Timer 1 (commutation) Timer 2 (position detection start) Timer 3 (overflow) Timers 1 to 3 are enabled while the mode timer is operating. An interrupt can be generated once by setting the corresponding bit in this register. The interrupt is disable when an interrupt is generated or the timer is reset. To use the timer again, set the register back again even if data is same. Timer 1 interrupt (commutation) Timer 2 interrupt (position detection start) Timer 3 interrupt or position detection interrupt Debug output (P67, P77) Figure 12-8 DBOUT Debug Output Diagram Page 109 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG Timer Circuit Registers [Addresses (PMD1)] MTCRB (01FA5H) 7 DBOUT 6 - 5 TMOF 4 - 3 CLCP 2 SWCP 1 PDCCP 0 - (Initial value: 0*0*0 000*) 7 DBOUT Debug output 0: Disable 1: Enable (P67 for PMD1, P77 for PMD2) 0: No overflow 1: Overflowed 0: Disable 1: Enable 0: No operation 1: Capture 0: Disable 1: Enable R/W 5 TMOF Mode timer overflow Capture mode timer by overload protection Capture mode timer in software Capture mode timer by position detection R 3 CLCP R/W 2 SWCP W 1 PDCCP R/W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRB because it contains a write-only bit. MTCRA (01FA4H) 7 6 TMCK 5 4 RBTM3 3 RBCL 2 SWRES 1 RBPDC 0 TMEN (Initial value: 0000 0000) 000: fc/23 (400 ns at 20 MHz) 010: fc/24 (800 ns at 20 MHz) 100: fc/25 (1.6 s at 20 MHz) 7, 6, 5 TMCK Select clock 110: fc/26 (3.2 s at 20 MHz) 001: fc/27 (6.4 s at 20 MHz) 011: Reserved 101: Reserved 111: Reserved 4 RBTM3 Reset mode timer from Timer 3 Reset mode timer by overload protection Reset mode timer in software Reset mode timer by position detection Enable/disable mode timer 0: Disable 1: Enable 0: Disable 1: Enable 0: No operation 1: Reset 0: Disable 1: Enable R/W 0 TMEN 0: Disable 1: Enable timer start W R/W 3 RBCL 2 SWRES 1 RBPDC Note 1: When changing MTCRA MCAP (01FA7H, 01FA6H) F DF E DE D DD C DC B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000 0000 0000) MCAP Mode capture Position detection interval R CMP1 (01FA9H, 01FA8H) F DF E DE D DD C DC B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000 0000 0000) CMP2 (01FABH, 01FAAH) F DF E DE D DD C DC B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000 0000 0000) Page 110 TMP88PH41UG CMP3 (01FADH, 01FACH) F DF E DE D DD C DC B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000 0000 0000) CMP1 CMP2 CMP3 Timer 1 Timer 2 Timer 3 Magnitude comparison compare register Matching comparison compare register Matching comparison compare register R/W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRB or MTCRA register because these registers contain write-only bits. 12.4.1.2 Outline Processing in the Timer Unit Software Interrupt handling Read MCAP Calculate timer set value MCAP 1/2 MCAP 3/4 MCAP 2 Set timer Processing unnecessary CMP1, CMP2, CMP3 Commutation INTTMR1 To PWM MCAP Hardtware INTPDC Position detection unit Start Start Mode timer count up Mode timer MCAP Clear mode timer End Greater than compare 1? No Match with compare 2? No Match with compare 3? No Yes Generate INTTMR1 interrupt Generate INTTMR2 interrupt Generate INTTMR3 interrupt End of timer 1 Processing unnecessary Position detection start INTTMR2 To the position detection Error determination unit INTTMR3 Yes End of timer 2 Interrupt handling error handling Yes End of timer 3 Page 111 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.5 Three-phase PWM Output Unit The Three-phase PWM Output Unit has the function to generate three-phase PWM waves with any desired pulse width and the commutation function capable of brushless DC motor control. In addition, it has the protective functions such as overload protection and emergency stop functions necessary to protect the power drive unit, and the dead time adding function which helps to prevent the in-phase upper/lower transistors from getting shorted by simultaneous turn-on when switched over. For the PWM output pin (U,V,W,X,Y,Z), set the port register PxDR and PxCR (x = 3) to 1. The PWM output initially is set to be active low, so that if the output needs to be used active high, set up the MDCRA Register accordingly. 12.5.1 Configuration of the three-phase PWM output unit The three-phase PWM output unit consists of a pulse width modulation circuit, commutation control circuit, protective circuit (emergency stop and overload), and a dead time control circuit. 12.5.1.1 Pulse width modulation circuit (PWM waveform generating unit) This circuit produces three-phase independent PWM waveforms with an equal PWM frequency. For PWM waveform mode, triangular wave modulation or sawtooth wave modulation can be selected by using the PMD Control Register (MDCRA) bit 1. The PWM frequency is set by using the PMD Period Register (MDPRD). The following shows the relationship between the value of this register and the PWM counter clock set by the MDCRB Register, PWMCK. 1 Sawtooth wave PWM: MDPRD Register set value = -----------------------------------------------------------------------------------PWM frequency [ Hz ] x PWMCK 1 Triangular wave PWM: MDPRD Register set value = --------------------------------------------------------------------------------------------PWM frequency [ Hz ] x 2 x P WMCK The PMD Period Register (MDPRD) is comprised of dual-buffers, so that CMPU, V, W Register is updated with PWM period. When the waveform arithmetic circuit is operating, the PWM waveform output unit receives calculation results from the waveform arithmetic circuit and by using the results as CMPU, V, W Register set value, it outputs independent three-phase PWM waveforms. When the waveform calculation function is enabled by the waveform arithmetic circuit and transfer of calculation results into the CMPU to W Registers is enabled (with EDCRA Register bit 2), the CMPU to W Registers are disabled against writing. When the waveform calculation function is enabled (with EDCRA Register bit 1) and transfer of calculation results into the CMPU, V, W Registers is disabled (with EDCRA Register bit 4), the calculation results are transferred to the buffers of CMPU, V, W Registers, but not output to the port. Read-accessing the CMPU, V, and W registers can read the calculation results of the waveform arithmetic circuit that have been input to a buffer. After changing the read calculation result data by software, writing the changed data to the CMPU, V, and W registers enables an arbitrary waveform other than a sinusoidal wave to be output. When the registers are read after writing, the values written to the registers are read out if accessed before the calculation results are transferred after calculation is finished. Page 112 TMP88PH41UG [Sawtooth wave] MDCNT Data update [MDPRD] [CMPU] Time PWMU waveform [Triangular wave] On Off MDCNT Data update [MDPRD] [CMPU] Time On PWMU waveform Off Figure 12-9 PWM Waveforms The values of the PWM Compare Registers (CMPU/V/W) and the carrier wave generated by the PWM Counter (MDCNT) are compared for the relative magnitude by the comparator to produce PWM waveforms. The PWM Counter is a 12-bit up/down counter with a 100 ns (at fc = 20 MHz) resolution. For three-phase output control, two methods of generating three-phase PWM waveforms can be set. 1. Three-phase independent mode: Values are set independently in the three-phase PMD Compare Registers to produce three-phase independent PWM waveforms. This method may be used to produce sinusoidal or any other desired drive waveforms. 2. Three-phase common mode: A value is set in only the U-phase PMD Compare Register to produce three in-phase PWM waveforms using the U phase set value. This method may be used for DC motor square wave drive. The three-phase PMD Compare Registers each have a comparison register to comprise a dual-buffer structure. The values of the PMD Compare Registers are loaded into their respective comparison registers synchronously with PWM period. Page 113 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.5.1.2 Commutation control circuit Output ports are controlled depending on the contents set in the PMD Output Register (MDOUT). The contents set in this register are divided into two, one for selecting the synchronizing signal for port output, and one for setting up port output. The synchronizing signal can be selected from Timers 1 or 2, position detection signal, or without sync. Port output can be synchronized to this synchronizing signal before being further synchronized to the PWM signal sync. The MDOUT Register's synchronizing signal select bit becomes effective immediately after writing. Other bits are dual-buffered, and are updated by the selected synchronizing signal. Example: Commutation timing for one timer period with PWM synchronization specified INTTMR PWM Commutation Output on six ports can be set to be active high or active low independently of each other by using the MDCRA Register bits 5 and 4. Furthermore, the U, V, and W phases can individually be selected between PWM output and H/L output by using the MDOUT Register bits A to 8 and 5 to 0. When PWM output is selected, PWM waveforms are output; when H/L output is selected, a waveform which is fixed high or low is output. The MDOUT Register bits E to C set the expected position signal value for the position detection circuit. PWM control register MDCRA 7 6 - - 3, 2, 1 0 3 PWM control PWM synchronizing clock Up/Down PWM counter PWM interrupt INTPWM fc/2 MDCRB 1 to 0 Clock selector Selector/ Latch Selector/ Latch MDCNT B to 0 Stop MDCNT PMD period register MDPRD B to 0 PMD compare register CMPU B to 0 PWMU Buffer U Three-phase common/ Three-phase CMPV B to 0 PWMV Buffer V CMPW B to 0 PWMW Buffer W Figure 12-10 Pulse Width Modulation Circuit Page 114 TMP88PH41UG PMD output register - -, -, - B A, 9, 8 7, 6 5, 4, 3, 2, 1, 0 MDOUT 3 PWM synchronizing clock fc/4 S Selector 2 6 Position detection interrupt INTPDC Timer 1 interrupt INTTMR1 Timer 2 interrupt INTTMR2 S Selector Gate control Set Reset Latch MDOUT sync u PWMU x v PWMV y w PWMW z Figure 12-11 Commutation Control Circuit Dead time register DTR -, -, 5, 4, 3, 2, 1, 0 fc/8 u' x' ON delay circuit ON delay circuit PMD control register MDCRA --54---U X V Y W Z v' y' ON delay circuit w' z' Figure 12-12 Dead Time Circuit Page 115 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.5.2 Register Functions of the Waveform Synthesis Circuit MDCRB PWMCK Select PWM counter clock Select PWM counter clock. MDCRA When this bit is set to 1, INTPWM is generated every half period (at triangular wave peak and valley) in the case of center PWM output and PINT = 00. In other cases, this setting has no meaning. Select whether to set the duty cycle independently for three phases using the CMPU to W Registers or in common for all three phases by setting the CMPU Register only. Select the upper-phase output port polarity. Make sure the waveform synthesis function (MDCRA Register bit 0) is idle before selecting this port polarity. Select the lower-phase output port polarity. Make sure the waveform synthesis function (MDCRA Register bit 0) is idle before selecting this port polarity. Select the frequency at which to generate a PWM interrupt from four choices available: every PWM period or once every 2, 4, or 8 PWM periods. When setting of this bit is altered while operating, an interrupt may be generated at the time the bit is altered. Select PWM mode. PWM mode 0 is an edge PWM (sawtooth wave), and PWM mode 1 is a center PWM (triangular wave). When enabling this circuit (for waveform output), be sure to set the output port polarity and other bits of this register (other than MDCRA bit 0) beforehand. 7 HLFINT Select half-period interrupt 6 DTYMD DUTY mode 5 POLH Upper-phase port polarity 4 POLL Lower-phase port polarity 3, 2 PINT PWM interrupt frequency 1 PWMMD PWM mode Enable/Disable waveform generation circuit 0 PWMEN DTR DTR Dead time Set the dead time between the upper-phase and lower-phase outputs. MDOUT F UPDWN PWM counter flag This bit indicates whether the PWM counter is counting up or down. When edge PWM (sawtooth wave) is selected, it is always set to 0. Set the data to be compared with the position detection input port. The comparison data is adopted as the expected value simultaneously when port output sync settings made with MDOUT are reflected in the ports. (This is the expected position detection input value for the output set with MDOUT next time.) Select whether or not to synchronize port output to PWM period after being synchronized to the synchronizing signal selected with SYNCS. If selected to be synchronized to PWM, output is kept waiting for the next PWM after being synchronized with SYNCS. Waveform settings are overwritten if new settings are written to the register during this time, and output is generated with those settings. E, D, C PDEXP Mode compare register B PSYNC Select PWM synchronization A 9 8 WPWM VPWM UPWM Control UVW-phase PWM outputs Set U, V, and W-phase port outputs. (See the Table 12-3) 7, 6 SYNCS Select port output sync signal Select the synchronizing signal with which to output UVW-phase settings to ports. The synchronizing signal can be selected from Timers 1 or 2, position detection, or asynchronous. Select asynchronous when the initial setting, otherwise the above setting isn't reflected immediately. 5, 4 3, 2 1, 0 WOC VOC UOC Control UVW-phase outputs Set U, V, and W-phase port outputs. (See the Table 12-3) MDCNT PWM counter This is a 12-bit read-only register used to count PWM periods. MDPRD Set PWM period This register determines PWM period, and is dual-buffered, allowing PWM period to be altered even while the PWM counter is operating. The buffers are loaded every PWM period. When 100 ns is selected for the PWM counter clock, make sure the least significant bit is set to 0. Page 116 TMP88PH41UG CMPU CMPV CMPW Set PWM pulse width This comparison register determines the pulse widths output in the respective UVW phases. This register is dual-buffered, and the pulse widths are determined by comparing the buffer and PWM counter. Waveform Synthesis Circuit Registers [Addresses (PMD1)] MDCRB (01FAFH) 7 - 6 - 5 - 4 - 3 - 2 - 1 PWMCK 0 (Initial value: **** **00) 00: fc/2 [Hz] (100 ns at 20 MHz) 1, 0 PWMCK PWM counterSelect clock 01: fc/22 10: fc/23 11: fc/24 (200 ns at 20 MHz) (400 ns at 20 MHz) (800 ns at 20 MHz) R/W Note: When changing setting, keep the PWMEN bit reset to "0" (disable wave form synthesis function). MDCRA (01FAEH) 7 HLFINT 6 DTYMD 5 POLH 4 POLL 3 PINT 2 1 PWMMD 0 PWMEN (Initial value: 0000 0000) 7 HLFINT Select half-period interrupt 0: Interrupt as specified in PINT 1: Interrupt every half period when PINT = 00 0: U phase in common 1: Three phases independent 0: Active low 1: Active high 0: Active low 1: Active high 00: Interrupt every period 01: Interrupt once every 2 periods 10: Interrupt once every 4 periods 11: Interrupt once every 8 periods 0: PWM mode0 (Edge: Sawtooth wave) 1: PWM mode1 (Center: Triangular wave) 0: Disable 1: Enable (Waveform output) 6 DTYMD DUTY mode 5 POLH Upper-phase port polarity 4 POLL Lower-phase port polarity R/W 3, 2 PINT Select PWM interrupt (trigger) 1 PWMMD PWM mode Enable/disable waveform synthesis function 0 PWMEN DTR (01FBEH) 7 - 6 - 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: **00 0000) 5 to 0 DTR Dead time 23/fc x 6 bit (maximum 25.2 s at 20 MHz) R/W Note: When changing setting, keep the MDCRA Page 117 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG MDOUT (01FB3H, 01FB2H) F UPDWN 7 SYNCS E D PDEXP C B PSYNC A WPWM 2 VOC 9 VPWM 1 UOC 8 UPWM 0 (Initial value: 00000000 00000000) 6 5 WOC 4 3 F UPDWN PWM counter flag 0: Counting up 1: Counting down bit E: W-phase expected value bit D: V-phase expected value bit C: U-phase expected value 0: Asynchronous 1: Synchronized 0: H/L level output 1: PWM waveform output 0: H/L level output 1: PWM waveform output 0: H/L level output 1: PWM waveform output 00: Asynchronous 01: Synchronized to position detection 10: Synchronized to Timer 1 11: Synchronized to Timer 2 R E, D, C PDEXP Comparison register for position detection B PSYNC Select PWM synchronization A WPWM W-phase PWM output 9 VPWM V-phase PWM output R/W 8 UPWM U-phase PWM output 7, 6 SYNCS Select port output synchronizing signal 5, 4 3, 2 1, 0 WOC VOC UOC Control W-phase output Control V-phase output Control U-phase output See the table 1-3 12.5.3 Port output as set with UOC/VOC/WOC bits and UPWM/VPWM/WPWM bits Table 12-3 Example of Pin Output Settings U-phase output polarity: Active high (POLH,POLL = 1) UPWM UOC 1: PWM output U phase 00 01 10 11 PWM U-phase output polarity: Active low (POLH,POLL = 0) UPWM UOC 1: PWM output U phase 00 01 10 11 PWM H PWM PWM 0: H/L level output U phase L L H H X phase L H L H 0: H/L level output U phase H H L L X phase H L H L X phase PWM PWM L PWM X phase PWM PWM L PWM PWM H PWM Page 118 TMP88PH41UG F MDCNT (01FB5H, 01FB4H) - E - D - C - B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) B to 0 PWM counter PWM period counter value R F MDPRD (01FB7H, 01FB6H) - E - D - C - B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) B to 0 PWM period PWM period MDPRD 010H R/W F CMPU (01FB9H, 01FB8H) - E - D - C - B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) F CMPV (01FBBH, 01FBAH) - E - D - C - B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) F CMPW (01FBDH, 01FBCH) - E - D - C - B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) CMPU B to 0 CMPV CMPW PWM compare U register PWM compare V register PWM compare W register Set U-phase duty cycle Set V-phase duty cycle Set W-phase duty cycle R/W Page 119 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.5.4 Protective Circuit This circuit consists of an EMG protective circuit and overload protective circuit. These circuits are activated by driving their respective port inputs active. EMG control register EMGCRB 7 6, 5 4 3, 2, 1, 0 2 4 EMGCRA 7, 6, 5, 4 - 2 1 0 4 Under protection 2 EMG disable code register EMGREL MDOUT A to 0 7, 6, 5, 4, 3, 2, 1, 0 8 EMG protective control Set "0" Overload protective input CL Timer 1 interrupt INTTMR1 PWM synchronizing clock PWM sync Overload protective interrupt INTCLM Stop MDCNT CL detection Reset control Overload protective control EMG EMG input INTEMG EMG interrupt u x v y w z u' x' v' y' w' z' Figure 12-13 Configuration of the Protective Circuit a. EMG protective circuit This protective circuit is used for emergency stop, when the EMG protective circuit is enabled. When the signal on EMG input port goes active (negative edge triggered), the six ports are immediately disabled high-impedance against output and an EMG interrupt (INTEMG) is generated. The EMG Control Register (EMGCRA) is used to set EMG protection. If the EMGCRA Page 120 TMP88PH41UG The number of times the overload protective input is sampled can be set by using the EMGCRA I (Current) EMG setting current Overload protection setting current Input EMG pin Input CL pin PWM output ("H" active) Overload protection (Output cut off) EMG protection (High-Z output) t (time) Figure 12-14 Example of Protection Circuit Operation Page 121 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.5.5 Functions of Protective Circuit Registers EMGREL EMG disable The EMG protective circuit is disable from the disabled state by writing "5AH" and "A5H" to this register in that order. After that, the EMGCRA Register needs to be set. EMGCRB When this bit is set to 1, the motor control circuit is returned from overload protective state in software (e.g., by writing to this register). Also, the current state can be known by reading this bit. MDOUT outputs at return from the overload protective state remain as set before the overload protective input was driven active. When this bit is set to 1, the motor control circuit is returned from overload protective state by PWM sync. If RTCL is set to 1, RTCL has priority. When this bit is set to 1, the motor control circuit is returned from overload protective state by Timer 1 sync. If RTCL is set to 1, RTCL has priority. The status of overload protection can be known by reading this bit. Select the phases to be disabled against output during overload protection. This facility allows selecting to disable no phases, all phases, PWM phases, or all upper phases/all lower phases. Can stop the PWM counter during overload protection. 7 RTCL Return from overload protective state 6 RTPWM Return by PWM sync 5 4 RTTM1 CLST Return by timer sync Overload protective state Select output disabled phases during overload protection Stop counter during overload protection Enable/Disable overload protection 3, 2 CLMD 1 CNTST 0 CLEN Enable or disable the overload protective function. EMGCRA 7 to 4 2 CLCNT EMGST Overload protection sampling time EMG protective state Return from EMG protective state Set the length of time the overload protective input port is sampled. The status of EMG protection can be known by reading this bit. The motor control circuit is returned from EMG protective state by setting this bit to "1" . When returning, set the MDOUT Register A to 0 bits to "0" . Then set the EMGCRA Register bit 1 to "1" and set MDOUT waveform output. Then set up the MDCRA Register. The EMG protective circuit is activated by setting this bit to 1. This circuit initially is enabled. (To disable this circuit, make sure key code 5AH and A5H are written to the EMGREL1 Register beforehand.) 1 RTE 0 EMGEN Enable/Disable EMG protective circuit Page 122 TMP88PH41UG Protective Circuit Registers [Addresses (PMD1)] EMGREL (01FBFH) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000) 7 to 0 EMGREL EMG disable Can disable by writing 5AH and then A5H. W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EMGREL register because this register is write only. EMGCRB (01FB1H) 7 RTCL 6 RTPWM 5 RTTM1 4 CLST 3 CLMD 2 1 CNTST 0 CLEN (Initial value: 0000 0000) 7 RTCL Return from overload protective state Enable/Disable return from overload protective state by PWM sync Enable/Disable return from overload protective state by timer 1 Overload protective state 0: No operation 1: Return from protective state 0: Disable 1: Enable W 6 RTPWM R/W 5 RTTM1 0: Disable 1: Enable 0: No operation 1: Under protection 00: No phases disabled against output 01: All phases disabled against output 10: PWM phases disabled against output 11: All upper/All lower phases disabled against output (Note) 0: Do not stop 1: Stop the counter 0: Disable 1: Enable R/W 4 CLST R 3, 2 CLMD Select output disabled phases during overload protection 1 CNTST Stop PWM counter during overload protection Enable/Disable overload protective circuit 0 CLEN Note: If during overload protection the port output state in two or more upper phases is on, all lower phases are disabled and all upper phases are enabled for output; when two or more lower phases are on, all upper phases are disabled and all lower phases are enabled for output. EMGCRA (01FB0H) 7 6 CLCNT 5 4 3 2 EMGST 1 RTE 0 EMGEN (Initial value: 0000 *001) 7 to 4 CLCNT Overload protection sampling number of times. EMG protective state 22/fc x n ( n = 1 to 15, 0 and 1 are set as 1 at 20 MHz ) 0: No operation 1: Under protection 0: No operation 1: Return from protective state (Note 1) 0: Disable 1: Enable R/W 2 EMGST R 1 RTE Return from EMG state Enable/Disable EMG protective circuit W 0 EMGEN R/W Note 1: An instruction specifying a return from the EMG state is invalid if the EMG input is "L". Note 2: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EMGCRB or EMGCRA register because these registers contain write-only bits. Page 123 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.6 Electrical Angle Timer and Waveform Arithmetic Circuit Electrical Angle Timer fc/8 Clock select and divide circuit 12-bit counter Reset Position detection Caputure (EDCAP) 2 Comparator ELDEG 8, 7, 6, 5, 4, 3, 2, 1, 0 Count stop 9-bit electrical angle register 7 - 5, 4 -, -, -, EDCRA Period register buffer 4-bit counter Decoder Period correction circuit F to C Correction value (4 bits) B to 0 EDSET Electrical angle period (12 bits) Figure 12-15 Electrical Angle Timer Circuit Waveform Arithmetic Circuit AMP B, A, 8, 7, 6, 5, 4, 3, 2, 1, 0 Voltage set register Electrical angle timer interrupt (INTEDT) Selector (12 bits) Electrical angle timer (9 bits) Electrical angle RAM 384 bytes Multiplier 12 bits 2-/3-phase modulation switch Selector ELDEG 8, 7, 6, 5, 4, 3, 2, 1, 0 WFMDR 76543210 Calculation finish 8 bits 3210 EDCRB - 6 -, - 3 2 1 0 EDCRA U-phase V-phase W-phase calculation calculation calculation result result result 12 bits 12 bits 12 bits CMPU CMPV CMPW Figure 12-16 Waveform Arithmetic Circuit Page 124 TMP88PH41UG 12.6.1 Electrical Angle Timer and Waveform Arithmetic Circuit The Electrical Angle Timer finishes counting upon reaching the value set by the Period Set Register (EDSET). The Electrical Angle Timer counts 360 degrees of electrical angle in the range of 0 to 383 (17FH) and is cleared to 0 upon reaching 383. In this way, it is possible to obtain the electrical angle of the frequency proportional to the value set by the Period Set Register. The period with which to count up can be corrected by using the Period Correction Register, allowing for fine adjustment of the frequency. The electrical angles counted by the Electrical Angle Timer are presented to the Waveform Arithmetic Circuit. An electrical angle timer interrupt signal is generated each time the Electrical Angle Timer finishes counting. The Waveform Arithmetic Circuit has a sine wave data table, which is used to extract sine wave data based on the electrical angle data received from the Electrical Angle Timer. This sine wave data is multiplied by the value of the Voltage Amplitude Register. For 2-phase modulation, the product obtained by this multiplication is presented to the waveform synthesis circuit. For 3-phase modulation, waveform data is further calculated based on the product of multiplication and the electrical angle data and the value of the PWM Period Register. The calculation is performed each time the Electrical Angle Timer finishes counting or when a value is set in the Electrical Angle Register, and the calculation results consisting of the U phase, the V phase (+120 degrees), and the W phase (+240 degrees) are sequentially presented to the PWM waveform output circuit. The sine wave data table is stored in the RAM and requires initialization. * To correct the period, set the number of times `n' to be corrected in the Period Correction Register (EDSET Register F to C bits). The period is corrected by adding 1 to electrical angle counts 16 for `n' times. For example, when a value 3 is set in the Period Correction Register, the period for 13 times out of electrical angle counts 16 is the value "mH" set in the Period Set Register, and that for 3 times is "m + 1H". (Correction is made almost at equal intervals.) * Because the electrical angle counter (ELDEG) can be accessed even while the Electrical Angle Timer is operating, the electrical angles can be corrected during operation. * The Electrical Angle Capture EDCAP captures the electrical angle value from the Electrical Angle Counter at the time the position is detected. * When the waveform calculation function is enabled, waveform calculation is performed each time the electrical angle counter (ELDEG) are accessed for write or the Electrical Angle Timer finishes counting. * The calculation is performed in 35 machine cycle of execution time, or 7 s (at 20 MHz). * When transfer of calculation result to the CMP Registers is enabled (EDCRA Note 1: The value set in the Period Set Register (EDSET Register EDT bits) must be equal to or greater than 010H. Any value smaller than this is assumed to be 010H. Note 2: The sine wave data that is read consists of the U phase, the V phase whose electrical angle is +120 degrees relative to the U phase, and the W phase whose electrical angle is +240 degrees relative to the U phase. Note 3: If a period corresponding to an electrical angle of one degree is shorter than the required calculation time, the previously calculated results are used. Page 125 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.6.1.1 Functions of the Electrical Angle Timer and Waveform Arithmetic Circuit Registers EDCRB 3 CALCST Start calculation by software Forcefully start calculation. When this bit is written while the waveform arithmetic circuit is calculating, the calculation is terminated and then newly started. By reading this bit, the operation status of the waveform arithmetic circuit can be obtained. Select whether to start calculation when the electrical angle timer finishes counting or when a value is set in the electrical angle register. When disabled, calculation is only started when CALCST is set to 1. Set the electrical angle interrupt signal request timing to either when the electrical angle timer finishes counting or upon end of calculation. 2 CALCBSY Calculation flag Enable/disable calculation start synchronized with electrical angle Electrical angle interrupt 1 EDCALEN 0 EDISEL EDCRA 7 6 5, 4 EDCNT EDRV EDCK Electrical angle count up/ down Select V-, W-phase Select clock Set whether the electrical angle timer counts up or down. Select phase direction of V-phase and W-phase in relation to U-phase. Select the clock for the electrical angle timer. This setting can be altered even while the electrical angle timer is operating. Select the modulation method with which to perform waveform calculation. Two-phase modulation DATA = ramdata (ELDEG) x AMP 3 C2PEN Switch between 2-phase and 3-phase modulations MOPRD ramdata ( ELDEG ) x AMP Three-phase modulation: DATA = ---------------------- -------------------------------------------------------------------2 2 Note: The sign during 3-phase modulation changes depending on the electrical angle. + for electrical angles 0 to 179 degrees (191) - for electrical angles 180 (192) to 360 (383) degrees Enable/disable transfer of calculation results by the waveform arithmetic circuit. When the waveform calculation function is enabled while at the same time transfer is enabled, calculation results are set as U, V, and W-phase duty cycles of the PWM generation circuit and are reflected in the ports. Enable/disable the waveform calculation function. Calculations are performed by the waveform arithmetic circuit by enabling the waveform calculation function. When the waveform calculation function is enabled, the calculated results can be read from the U, V, and W-phase compare registers (CMPU, V, W) of the PWM generation circuit. Enable/disable the electrical angle timer. When enabled, the electrical angle timer starts counting; when disabled, the electrical angle timer stops counting and is cleared to 0. 2 RWREN Auto transfer calculation results to CPM registers 1 CALCEN Enable/disable waveform calculation function 0 EDTEN Electrical angle timer EDSET F to C B to 0 EDTH EDT Correct electrical angle period Electrical angle period Correct the period by adding 1 to electrical angle counts 16 for "n" times. The timer counts the electrical angle period set value "m"'for (16 - n) times and counts (m + 1) for "n" times Set the electrical angle period. ELDEG Electrical angle Read the electrical angle. This register can also be set to initialize or correct the angle while counting. Any value greater than 17FH cannot be set. AMP Set voltage amplitude Set the voltage amplitude. The waveform arithmetic circuit multiplies the data set here by the sine wave data read out from the sine wave RAM. The amplitude has its upper limit determined by the set value of the MDPRD register when performing this multiplication. EDCAP Capture electrical angle Capture the value from the electrical angle timer when the position is detected. WFMDR Set sine wave data To initialize the entire RAM data of the sine wave table, set the addresses at which to set, sequentially from 000H to 17FH, in the ELDEG register, and write waveform data to the WFMDR register each time. Make sure the waveform arithmetic circuit is disabled when writing this data. Page 126 TMP88PH41UG Typical Settings of Sine Wave Data Two-phase modulation 100% Data amplitude 255 0 0 Three-phase modulation 100% Data amplitude 255 64 60 (40H) 128 120 (80H) 192 (C0H) 256 (100H) 320 (140H) 383 (17FH) (ELDEG) 180 240 300 360 Electrical angle 0 0 64 60 (40H) 128 120 (80H) 192 (C0H) 256 (100H) 320 (140H) 383 (17FH) (ELDEG) 180 240 300 360 Electrical angle Note: During 3-phase modulation, the sign changes at 180 degrees of electrical angle. Figure 12-17 Typical Settings of Sine Wave Data Page 127 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG List of the Electrical Angle Timer and Waveform Arithmetic Circuit Registers [Addresses (PMD1)] EDCRB (01FC1H) 7 - 6 - 5 - 4 - 3 CALCST 2 CALCBSY 1 EDCALEN 0 EDISEL (Initial value: **** 0000) 3 CALCST Start calculation by software 0: No operation 1: Start calculation 0: Waveform Arithmetic Circuit stopped 1: Waveform Arithmetic Circuit calculating 0: Start calculation insync with electrical angle 1: Do notcalculation insync with electrical angle W 2 CALCBSY Calculation flag Enable/disable calculation start synchronized with electrical angle Electrical angle interrupt R 1 EDCALEN R/W 0: Interrupt when the Electrical Angle Timer finishes counting 1: Interrupt upon end of calculation 0 EDISEL Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EDCRB register because this register is write only. EDCRA (01FC0H) 7 EDCNT 6 EDRV 5 EDCK 4 3 C2PEN 2 RWREN 1 CALCEN 0 EDTEN (Initial value: 0000 0000) 7 EDCNT Electrical angle count up/down 0: Count up 1: Count down 0: V = U + 120, W = U + 240 1: V = U - 120, W = U - 240 00: fc/23 (400 ns at 20 MHz) 6 EDRV Select V-, W-phase 5, 4 EDCK Select clock 01: fc/24 (800 ns at 20 MHz) 10: fc/25 (1.6 s at 20 MHz) 11: fc/26 (3.2 s at 20 MHz) R/W 3 C2PEN Switch between 2-/3-phase modulations Transfer calculation result to CMP registers Enable/disable waveform calculation function Electrical angleEnable/disable mode timer 0: 2-phase modulation 1: 3-phase modulation 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 2 RWREN 1 CALC 0 EDTEN Note: When changing the EDCRA Page 128 TMP88PH41UG F EDSET (01FC3H, 01FC2H) E D C B A 9 8 7 6 EDT 5 4 3 2 1 0 (Initial value: 00000000 00010000) EDTH F to C B to 0 EDTH EDT Correct period (n) Set period (m) 0 to 15 times 010H R/W One period of the Electrical Angle Timer, T, is expressed by the equation below. nT = m + ----- x 384 x set clock [ s ] where m = set period, n = period correction 16 ELDEG (01FC5H, 01FC4H) F - E - D - C - B - A - 9 - 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: *******0 00000000) 8 to 0 ELDEG Electrical angle Set the Initially and the count values of electrical angle. R/W AMP (01FC7H, 01FC6H) F - E - D - C - B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****0000 00000000) B to 0 AMP Set voltage Set the voltage to be used during waveform calculation. R/W EDCAP (01FC9H, 01FC8H) F - E - D - C - B - A - 9 - 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ******0 00000000) 8 to 0 EDCAP Captured value of electrical angle Electrical angle timer value when position is detected. R WFMDR (01FCAH) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ********) 7 to 0 WFMDR Sine wave data Write sine wave data to RAM of sine wave W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the WFMDR register because this register is write only. Page 129 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG 12.6.1.2 List of PMD Related Control Registers (1) Input/output Pins and Input/output Control Registers PMD1 Input/Output Pins (P3, P4) and Port Input/Output Control Registers (P3CR, P4CR) Name Address Bit 7 R or W R/W R/W R/W R/W Overload protection (CL1) EMG input (EMG1) U1/V1/W1/X1/Y1/Z1 outputs. Description P3DR 00003H 6 5 to 0 P4DR 00004H 2 to 0 Position signal inputs (PDU1, PDV1, PDW1). P3 port input/output control (can be set bitwise). 0: Input mode 1: Output mode P0 port input/output control (can be set bitwise). 0: Input mode 1: Output mode P3CR 01F89H 7 to 0 R/W P4CR 01F8AH 2, 1, 0 R/W Note: When using these pins as PMD function or input port, set the Output Latch (P*DR) to 1. Example of the PMD Pin Port Setting Input/Output CL1 EMG1 U1 PDU1 Input Input Output Input P3DR * * 1 - P3CR 0 0 1 - P4DR - - - * P4CR - - - 0 Page 130 TMP88PH41UG (2) Motor Control Circuit Control Registers [Address : PMD1] Position Detection Control Register (PDCR) and Sampling Delay Register (SDREG) Name Address Bit R or W Description Detect the position-detected position. 00: Within the current pulse 01: When PWM is off 10: Within the current pulse 11: Within the preceding pulse Monitor the sampling status. 0: Sampling idle 1: Sampling in progress Holds the status of the position signal input during unmatch detection mode. Bits 2, 1, and 0: W, V, and U phases Select the sampling input clock [Hz]. 5, 4 R PDCRC 01FA2H 3 R 2 to 0 R 7, 6 R/W 00: fc/22 10: fc/2 4 01: fc/23 11: fc/25 PDCRB 01FA1H 5, 4 R/W Sampling mode. 00: When PWM is on 01: Regularly 10: When lower phases are turned on Detection position match counts 1 to 15. 0: No operation 1: Stop sampling in software 0: No operation 1: Start sampling in software Stop sampling using Timer 3. 0: Disable 1: Enable Start sampling using Timer 2. 0: Disable 1: Enable Number of position signal input pins. 0: Compare three pins (PDU/PDV/PDW) 1: Compare one pin (PDU) only Count occurrences of matching when PWM is on. 0: Subsequent to matching counts when PWM previously was on 1: Eecount occurrences of matching each time PWM is on Position detection mode. 0: Ordinary mode 1: Unmatch detection mode Enable/Disable position detection function. 0: Disable 1: Enable (Sampling starts) Sampling delay. 23/fc x n bits (n = 0 to 6, maximum 50.8 s at 20 MHz). 3 to 0 7 R/W W 6 W 5 R/W 4 01FA0H 3 R/W PDCRA R/W 2 R/W 1 R/W 0 R/W SDREG 01FA3H 6 to 0 R/W Page 131 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG Mode Timer Control Register (MTCR), Mode Capture Register (MCAP), and Compare Registers (CMP1, CMP2, CMP3) Name Address Bit R or W Debug output. 0: Disable 1: Enable (P67 for PMD1) Mode timer overflow. 0: No overflow 1: Overflowed occurred Description 7 R/W 5 R MTCRB 01FA5H 3 R/W Capture mode timer by overload protection. 0: Disable 1: Enable Capture mode timer by software. 0: No operation 1: Capture Capture mode timer by position detection. 0: Disable 1: Enable Select clock for mode timer [Hz]. 000: fc/23 (400 ns at 20 MHz) 010: fc/24 (800 ns at 20 MHz) 100: fc/25 (1.6 s at 20 MHz) 2 W 1 R/W 7, 6, 5 R/W 110: fc/26 (3.2 s at 20 MHz) 001: fc/27 (6.4 s at 20 MHz) 011: Reserved 101: Reserved 111: Reserved Reset timer by Timer 3. 0: Disable 1: Enable Reset timer by overload protection. 0: Disable 1: Enable Reset timer by software. 0: No operation 1: Reset Reset timer by position detection. 0: Disable 1: Enable Enable/Disable mode timer. 0: Disable 1: Enable (timer starts) Mode capture register. 4 MTCRA 01FA4H 3 R/W R/W 2 W 1 R/W 0 R/W MCAP 01FA7H, 01FA6H F to 0 R CMP1 01FA9H, 01FA8H F to 0 R/W Compare Register 1. CMP2 01FABH, 01FAAH F to 0 R/W Compare Register 2. CMP3 01FADH, 01FACH F to 0 R/W Compare Register 3. Page 132 TMP88PH41UG PMD Control Register (MDCR), Dead Time Register (DTR), and PMD Output Register (MDOUT) Name Address 01FAFH Bit R or W Description Select clock for PWM counter. MDCRB 1, 0 R/W 00: fc/2 (100 ns at 20 MHz) 10: fc/2 (400 ns at 20 MHz) 3 01: fc/22 (200 ns at 20 MHz) 11: fc/24 (800 ns at 20 MHz) 7 R/W Select half-period interrupt 0: Interrupt every period as specified in PINT. 1: Interrupt every half-period only PINT=00. DUTY mode. 0: U phase in common 1: Three phases independent Upper-phase port polarity. 0: Active low 1: Active high Lower-phase port polarity. 0: Active low 1: Active high Select PWM interrupt (trigger). 00: Interrupt once every period 01: Interrupt once 2 periods 10: Interrupt once 4 periods 11: Interrupt once 8 periods PWM mode. 0: PWM mode0 (edge: sawtooth wave) 1: PWM mode1 (center: triangular wave) Enable/disable waveform synthesis function. 0: Disable 1: Enable (waveform output) Set dead time. 23/fc x 6bit (maximum 25.2 s at 20 MHz). 0: Count up 1: Count down Comparison register for position detection. 6: W 5: V 4: U Select PWM synchronization. 0: Asynchronous with PWM period 1: Synchronized W-phase PWM output. 0: H/L level output 1: PWM waveform output V-phase PWM output. 0: H/L level output 1: PWM waveform output U-phase PWM output. 0: H/L level output 1: PWM waveform output Select port output synchronizing signal. 00: Asynchronous 01: Synchronized to position detection 10: Synchronized to Timer 1 11: Synchronized to Timer 2 Control W-phase output Control V-phase output Control U-phase output 6 R/W 5 R/W MDCRA 01FAEH 4 R/W 3, 2 R/W 1 R/W 0 R/W DTR 01FBEH 5 to 0 R/W F R E, D, C R/W B R/W A R/W MDOUT 01FB3H, 01FB2H 9 R/W 8 R/W 7, 6 R/W 5, 4 3, 2 1, 0 R/W R/W R/W Page 133 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG PWM Counter (MDCNT), PMD Period Register (MDPRD), and PMD Compare Registers (CMPU, CMPV, CMPW) Name MDCNT Address 01FB5H, 01FB4H Bit B to 0 R or W R Description Read the PWM period counter value. PWM period MDPRD 010H. Set U-phase PWM duty cycle. MDPRD 01FB7H, 01FB6H B to 0 R/W CMPU 01FB9H, 01FB8H B to 0 R/W CMPV 01FBBH, 01FBAH B to 0 R/W Set V-phase PWM duty cycle. CMPW 01FBDH, 01FBCH B to 0 R/W Set W-phase PWM duty cycle. EMG Disable Code Register (EMGREL) and EMG Control Register (EMGCR) Name EMGREL Address 01FBFH Bit 7 to 0 R or W W Description Code input for disable EMG protection circuit. Can be disable by writing 5AH and then A5H. Return from overload protective state. 0: No operation 1: Return from protective state Condition for returning from overload protective state: Synchronized to PWM. 0: Disable 1: Enable Enable/Disable return from overload protective state by timer 1. 0: Disable 1: Enable Overload protective state. 0: No operation 1: Under protection Select output disabled phases during overload protection. 00: No phases disabled against output 01: All phases disabled against output 10: PWM phases disabled against output 11: All upper/All lower phases disabled against output Stop PWM counter (MDCNT) during overload protection. 0: Do not stop 1: Stop Enable/Disable overload protective circuit. 0: Disable 1: Enable Overload protection sampling time. 22/fc x n (n = 1 to 15, at 20 MHz) EMG protective state. 0: No operation 1: Under protection Return from EMG protective state. 0: No operation 1: Return from protective state Enable/Disable fanction of the EMG protective circuit. 0: Disable 1: Enable (This circuit initially is enabled (= 1). To disable this circuit, make sure key code 5AH and A5H are written to the EMGREL1 Register beforehand.) 7 W 6 R/W 5 R/W EMGCRB 01FB1H 4 R 3, 2 R/W 1 R/W 0 R/W 7 to 4 R/W 2 R EMGCRA 01FB0H 1 W 0 R/W Page 134 TMP88PH41UG Electrical Angle Control Register (EDCR), Electrical Angle Period Register (EDSET), Electrical Angle Set Register (ELDEG), Voltage Set Register (AMP), and Electrical Angle Capture Register (EDCAP). Name Address Bit 3 R or W W 0: No operation 1: Start calculation Description 2 EDCRB 01FC1H 1 R 0: Waveform Arithmetic Circuit stopped 1: Waveform Arithmetic Circuit calculatin 0: Start calculation insync with electrical angle 1: Do not calculation insync with electrical angle 0: Interrupt when the Electrical Angle Timer finishes counting 1: Interrupt upon end of calculation 0: Count up 1: Count down 0: V = U + 120, W = U + 240 1: V = U - 120, W = U - 240 Select clock. R/W 0 R/W 7 R/W 6 R/W 5, 4 R/W 00: fc/23 10: fc/2 5 01: fc/24 11: fc/26 EDCRA 01FC0H 3 R/W Switch between 2/3-phase modulations. 0: Two-phase modulation 1: Three-phase modulation Transfer calculation result to CMP registers. 0: Disable 1: Enable Enable/disable waveform calculation function. 0: Disable 1: Enable Electrical angle timer. 0: Disable 1: Enable Correct period (n) 0 to 15 times. Set period (1/m counter) 010H Initially set and count values of electrical angle. 2 R/W 1 R/W 0 R/W EDSET 01FC3H, 01FC2H F to C B to 0 R/W R/W R/W ELDEG 01FC5H, 01FC4H 8 to 0 AMP 01FC7H, 01FC6H B to 0 R/W Set voltage used during waveform calculation. EDCAP 01FC9H, 01FC8H 8 to 0 R Electrical angle timer value when position is detected. WFMDR 01FCAH 7 to 0 W Set sine wave data. Page 135 12. Motor Control Circuit (PMD: Programmable motor driver) TMP88PH41UG Page 136 TMP88PH41UG 13. Asynchronous Serial interface (UART) The TMP88PH41UG has a asynchronous serial interface (UART) . It can connect the peripheral circuits through TXD and RXD pin. TXD and RXD pin are also used as the general port. For TXD pin, the corresponding general port should be set output mode (Set its output control register to "1" after its output port latch to "1"). For RXD pin, should be set input mode. This UART and SIO can not use simultaneously because their input/output ports are common. 13.1 Configuration UART control register 1 UARTCRA Transmit data buffer TDBUF Receive data buffer RDBUF 3 2 Receive control circuit 2 Transmit control circuit Shift register Shift register Parity bit Stop bit Noise rejection circuit RXD INTTX INTRX TXD Transmit/receive clock Y M P X S 2 Y Counter UARTSR UART status register S fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC4 fc/96 A B C fc/2 7 fc/2 fc/28 6 A B C D E F G H 4 2 UARTCRB UART control register 2 MPX: Multiplexer Baud rate generator Figure 13-1 UART (Asynchronous Serial Interface) Page 137 13. Asynchronous Serial interface (UART) 13.2 Control TMP88PH41UG 13.2 Control UART is controlled by the UART Control Registers (UARTCRA, UARTCRB). The operating status can be monitored using the UART status register (UARTSR). UART Control Register1 UARTCRA (01F91H) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 0 (Initial value: 0000 0000) TXE Transfer operation 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 000: 001: 010: 011: 100: 101: 110: 111: Disable Enable Disable Enable 1 bit 2 bits Odd-numbered parity Even-numbered parity No parity Parity fc/13 [Hz] fc/26 fc/52 fc/104 fc/208 fc/416 Input INTTC4 fc/96 Write only RXE Receive operation STBT Transmit stop bit length EVEN Even-numbered parity PE Parity addition BRG Transmit clock select Note 1: When operations are disabled by setting UARTCRA UART Control Register2 UARTCRB (01F92H) 7 6 5 4 3 2 RXDNC 1 0 STOPBR (Initial value: **** *000) RXDNC Selection of RXD input noise rejectio time 00: 01: 10: 11: 0: 1: No noise rejection (Hysteresis input) Rejects pulses shorter than 31/fc [s] as noise Rejects pulses shorter than 63/fc [s] as noise Rejects pulses shorter than 127/fc [s] as noise 1 bit 2 bits Write only STOPBR Receive stop bit length Note: When UARTCRB Page 138 TMP88PH41UG UART Status Register UARTSR (01F91H) 7 PERR 6 FERR 5 OERR 4 RBFL 3 TEND 2 TBEP 1 0 (Initial value: 0000 11**) PERR Parity error flag 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: No parity error Parity error No framing error Framing error No overrun error Overrun error Receive data buffer empty Receive data buffer full On transmitting Transmit end Transmit data buffer full (Transmit data writing is finished) Transmit data buffer empty FERR Framing error flag OERR Overrun error flag Read only RBFL Receive data buffer full flag TEND Transmit end flag TBEP Transmit data buffer empty flag Note: When an INTTXD is generated, TBEP flag is set to "1" automatically. UART Receive Data Buffer RDBUF (01F93H) 7 6 5 4 3 2 1 0 Read only (Initial value: 0000 0000) UART Transmit Data Buffer TDBUF (01F93H) 7 6 5 4 3 2 1 0 Write only (Initial value: 0000 0000) Page 139 13. Asynchronous Serial interface (UART) 13.3 Transfer Data Format TMP88PH41UG 13.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCRA PE STBT 1 Start 2 Bit 0 3 Bit 1 Frame Length 8 Bit 6 9 Bit 7 10 Stop 1 11 12 0 0 1 1 0 1 0 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2 Figure 13-2 Transfer Data Format Without parity / 1 STOP bit With parity / 1 STOP bit Without parity / 2 STOP bit With parity / 2 STOP bit Figure 13-3 Caution on Changing Transfer Data Format Note: In order to switch the transfer data format, perform transmit operations in the above Figure 13-3 sequence except for the initial setting. Page 140 TMP88PH41UG 13.4 Transfer Rate The baud rate of UART is set of UARTCRA Source Clock BRG 16 MHz 000 001 010 011 100 101 76800 [baud] 38400 19200 9600 4800 2400 8 MHz 38400 [baud] 19200 9600 4800 2400 1200 When INTTC4 is used as the UART transfer rate (when UARTCRA 13.5 Data Sampling Method The UART receiver keeps sampling input using the clock selected by UARTCRA RXD pin Start bit RT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (a) Without noise rejection circuit Bit 0 RXD pin Start bit RT0 1 2 3 4 5 6 7 8 Bit 0 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (b) With noise rejection circuit Bit 0 Figure 13-4 Data Sampling Method Page 141 13. Asynchronous Serial interface (UART) 13.6 STOP Bit Length TMP88PH41UG 13.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCRA 13.7 Parity Set parity / no parity by UARTCRA 13.8 Transmit/Receive Operation 13.8.1 Data Transmit Operation Set UARTCRA 13.8.2 Data Receive Operation Set UARTCRA Note:When a receive operation is disabled by setting UARTCRA Page 142 TMP88PH41UG 13.9 Status Flag 13.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR RXD pin Parity Stop Shift register xxxx0** pxxxx0* 1pxxxx0 UARTSR After reading UARTSR then RDBUF clears PERR. INTRXD interrupt Figure 13-5 Generation of Parity Error 13.9.2 Framing Error When "0" is sampled as the stop bit in the receive data, framing error flag UARTSR RXD pin Final bit Stop Shift register xxx0** xxxx0* 0xxxx0 UARTSR After reading UARTSR then RDBUF clears FERR. INTRXD interrupt Figure 13-6 Generation of Framing Error 13.9.3 Overrun Error When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR Page 143 13. Asynchronous Serial interface (UART) 13.9 Status Flag TMP88PH41UG UARTSR RXD pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 UARTSR After reading UARTSR then RDBUF clears OERR. INTRXD interrupt Figure 13-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UARTSR 13.9.4 Receive Data Buffer Full Loading the received data in RDBUF sets receive data buffer full flag UARTSR RXD pin Final bit Stop Shift register xxx0** yyyy xxxx0* 1xxxx0 RDBUF xxxx UARTSR After reading UARTSR then RDBUF clears RBFL. INTRXD interrupt Figure 13-8 Generation of Receive Data Buffer Full Note:If the overrun error flag UARTSR 13.9.5 Transmit Data Buffer Empty When no data is in the transmit buffer TDBUF, that is, when data in TDBUF are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag UARTSR Page 144 TMP88PH41UG Data write TDBUF Data write xxxx yyyy zzzz Shift register TXD pin *****1 1xxxx0 *1xxxx Bit 0 ****1x Final bit *****1 Stop 1yyyy0 Start UARTSR INTTXD interrupt Figure 13-9 Generation of Transmit Data Buffer Empty 13.9.6 Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR Shift register TXD pin ***1xx ****1x *****1 1yyyy0 *1yyyy Stop Data write for TDBUF Start Bit 0 UARTSR UARTSR INTTXD interrupt Figure 13-10 Generation of Transmit End Flag and Transmit Data Buffer Empty Page 145 13. Asynchronous Serial interface (UART) 13.9 Status Flag TMP88PH41UG Page 146 TMP88PH41UG 14. Synchronous Serial Interface (SIO) The TMP88PH41UG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. Serial interface is connected to outside peripherl devices via SO, SI, SCK port. This SIO and UART can not use simultaneously because their input/output ports are common. 14.1 Configuration SIO control / status register SIOSR SIOCR1 SIOCR2 CPU Control circuit Buffer control circuit Shift register Shift clock Transmit and receive data buffer (8 bytes in DBR) 7 6 5 4 3 2 1 0 SO Serial data output 8-bit transfer 4-bit transfer SI Serial data input INTSIO interrupt request Serial clock SCK Serial clock I/O Figure 14-1 Serial Interface Page 147 14. Synchronous Serial Interface (SIO) 14.2 Control TMP88PH41UG 14.2 Control The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2 SIOCR1 (1F96H) 7 SIOS 6 SIOINH 5 4 SIOM 3 2 1 SCK 0 (Initial value: 0000 0000) 0: SIOS Indicate transfer start / stop 1: 0: SIOINH Continue / abort transfer 1: 000: 010: 100: SIOM Transfer mode select 101: 110: Stop Start Continuously transfer Abort transfer (Automatically cleared after abort) 8-bit transmit mode 4-bit transmit mode 8-bit transmit / receive mode 8-bit receive mode 4-bit receive mode Except the above: Reserved NORMAL, IDLE mode DV1CK = 0 000 001 010 fc/2 13 Write only DV1CK = 0 fc/214 fc/29 fc/28 fc/27 fc/26 fc/25 Reserved Write only fc/28 fc/27 fc/26 fc/25 fc/24 SCK Serial clock select 011 100 101 110 111 External clock (Input from SCK pin) Note 1: fc; High-frequency clock [Hz] Note 2: Set SIOCR1 SIO Control Register 2 SIOCR2 (1F97H) 7 6 5 4 WAIT 3 2 1 BUF 0 (Initial value: ***0 0000) Page 148 TMP88PH41UG Always sets "00" except 8-bit transmit / receive mode. 00: WAIT Wait control 01: 10: 11: 000: 001: 010: BUF Number of transfer words (Buffer address in use) 011: 100: 101: 110: 111: Tf = TD(Non wait) Tf = 2TD(Wait) Tf = 4TD(Wait) Tf = 8TD (Wait) 1 word transfer 2 words transfer 3 words transfer 4 words transfer 5 words transfer 6 words transfer 7 words transfer 8 words transfer 01F98H 01F98H ~ 01F99H 01F98H ~ 01F9AH 01F98H ~ 01F9BH 01F98H ~ 01F9CH 01F98H ~ 01F9DH 01F98H ~ 01F9EH 01F98H ~ 01F9FH Write only Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest address. ( The first buffer address transmitted is 01F98H ). Note 3: The value to be loaded to BUF is held after transfer is completed. Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0). Note 5: *: Don't care Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. Note 7: Tf; Frame time, TD; Data transfer time (output) SCK output TD Tf Figure 14-2 Frame time (Tf) and Data transfer time (TD) SIO Status Register SIOSR (1F97H) 7 SIOF 6 SEF 5 4 3 2 1 0 (Initial value: 00** ****) SIOF Serial transfer operating status monitor Shift operating status monitor 0: 1: 0: 1: Transfer terminated Transfer in process Shift operation terminated Shift operation in process Read only SEF Note 1: After SIOCR1 14.3 Serial clock 14.3.1 Clock source Internal clock or external clock for the source clock is selected by SIOCR1 Page 149 14. Synchronous Serial Interface (SIO) 14.3 Serial clock TMP88PH41UG 14.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. Table 14-1 Serial Clock Rate NORMAL, IDLE mode SCK 000 001 010 011 100 101 110 111 Clock fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 External Baud Rate 2.44 Kbps 78.13 Kbps 156.25 Kbps 312.50 Kbps 625.00 Kbps 125.00 Kbps External Note: 1 Kbit = 1024 bit (fc = 20 MHz) Automatically wait function SCK pin (output) SO pin (output) Written transmit data a a0 a1 a2 a3 b b0 b1 c b2 b3 c0 c1 Figure 14-3 Automatic Wait Function (at 4-bit transmit mode) 14.3.1.2 External clock An external clock connected to the SCK pin is used as the serial clock. In this case, the SCK (P43) port should be set to input mode. To ensure shifting, a pulse width of more than 24/fc is required. This pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. SCK pin (Input) tSCKL tSCKH tSCKL, tSCKH > 24/fc Figure 14-4 External clock pulse width Page 150 TMP88PH41UG 14.3.2 Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 14.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/ output). 14.3.2.2 Trailing edge Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). SCK pin SO pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register 3210 *321 **32 ***3 (a) Leading edge SCK pin SI pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register **** 0*** 10** 210* 3210 *; Don't care (b) Trailing edge Figure 14-5 Shift edge 14.4 Number of bits to transfer Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to "0" when receiving. The data is transferred in sequence starting at the least significant bit (LSB). 14.5 Number of words to transfer Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIOCR2 Page 151 14. Synchronous Serial Interface (SIO) 14.6 Transfer Mode TMP88PH41UG SCK pin SO pin a0 a1 a2 a3 INTSIO interrupt (a) 1 word transmit SCK pin SO pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (b) 3 words transmit SCK pin SI pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (c) 3 words receive Figure 14-6 Number of words to transfer (Example: 1word = 4bit) 14.6 Transfer Mode SIOCR1 14.6.1 4-bit and 8-bit transfer modes In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data (number of transfer words to be transferred) to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIOCR1 Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do not use the DBR of the remained 5 words. When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. The transmission is ended by clearing SIOCR1 Page 152 TMP88PH41UG SIOCR1 Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (Output) SO pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSIO interrupt DBR a Write Write (a) (b) b Figure 14-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock) Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (Input) SO pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSIO interrupt DBR a Write Write (a) (b) b Figure 14-8 Transfer Mode (Example: 8bit, 1word transfer, External clock) Page 153 14. Synchronous Serial Interface (SIO) 14.6 Transfer Mode TMP88PH41UG SCK pin SIOSR SO pin MSB of last word tSODH = min 3.5/fc [s] (In the NORMAL, IDLE modes) Figure 14-9 Transmiiied Data Hold Time at End of Transfer 14.6.2 4-bit and 8-bit receive modes After setting the control registers to the receive mode, set SIOCR1 Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore, during SIO do not use such DBR for other applications. When an external clock is used, the shift operation is synchronized with the external clock; therefore, the previous data are read before the next data are transferred to the data buffer register. If the previous data have not been read, the next data will not be transferred to the data buffer register and the receiving of any more data will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay between the time when the interrupt request is generated and when the data received have been read. The receiving is ended by clearing SIOCR1 |