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| 8 Bit Microcontroller TLCS-870/C Series TMP86FS49AFG TMP86FS49AFG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2007 TOSHIBA CORPORATION All Rights Reserved TMP86FS49AFG Differences among Products Differences in Functions 86CH49 ROM RAM DBR(note1) I/O High-current port Interrupt Timer/counter UART SIO I2C Key-on wake-up 10-bit AD converter (note2) Flash Security N.A. 16 Kbytes (Mask) 512 bytes 86CM49 32 Kbytes (Mask) 1 Kbyte 86PM49 32 Kbytes (OTP) 1 Kbyte 86CS49 60 Kbytes (Mask) 2 Kbytes 86FS49 86FS49A 60 Kbytes (Flash) 2 Kbytes 128 bytes (Flash control register contained) 56 pins 13 pins (sink open drain) External: 5 interrupts, Internal: 19 interrupts 16-bit: 2 channels 8-bit: 4 channels 2 channels 2 channels 1 channel 4 channels 16 channels Read protect Read/Write protect VDD without protect diode on the VDD side R without pull down resister 86FS49B 128 bytes (Flash control register not contained) VDD Structurer of TEST pin R RIN without protect diode on the VDD side R without pull down resister VDD R RIN without protect diode on the VDD side R without pull down resister R without pull down resister Emulation chip QFP64P-14140.80A QFP64-P-1414-0.80A LQFP64-P-1010-0.50D SDIP64-P-750-1.78 TMP86C949XB QFP64-P-1414-0.80A LQFP64-P-1010-0.50D Package - Note 1: The products with Flash memory (86FS49, 86FS49A, 86FS49B) contain the Flash control register (FLSCR) at 0FFFH in the DBR area. The products with mask ROM or OTP and the emulation chip do not have the FLSCR register. In these devices, therefore, a program that accesses the FLSCR register cannot function properly (executes differently as in the case of a Flash product). Note 2: In this data sheet,the following pin names and register names have been changed from the data sheet of the old edition. Although the names have been changed, their functions remain the same. TMP86FS49AFG OLD name P60(AIN00) P61(AIN01) P62(AIN02) P63(AIN03) P64(AIN04) P65(AIN05) P66(AIN06) P67(AIN07) P70(AIN10) P71(AIN11) P72(AIN12) P73(AIN13) P74(AIN14) P75(AIN15) P76(AIN16) P77(AIN17) 0000:AIN00 0001:AIN01 0010:AIN02 0011:AIN03 0100:AIN04 0101:AIN05 0110:AIN06 0111:AIN07 1000:AIN10 1001:AIN11 1010:AIN12 1011:AIN13 1100:AIN14 1101:AIN15 1110:AIN16 1111:AIN17 NEW name P60(AIN0) P61(AIN1) P62(AIN2) P63(AIN3) P64(AIN4) P65(AIN5) P66(AIN6) P67(AIN7) P70(AIN8) P71(AIN9) P72(AIN10) P73(AIN11) P74(AIN12) P75(AIN13) P76(AIN14) P77(AIN15) 0000:AIN0 0001:AIN1 0010:AIN2 0011:AIN3 0100:AIN4 0101:AIN5 0110:AIN6 0111:AIN7 1000:AIN8 1001:AIN9 1010:AIN10 1011:AIN11 1100:AIN12 1101:AIN13 1110:AIN14 1111:AIN15 AD Converter analog input pin name ADCCR1 register TMP86FS49AFG Differences in Electrical Characteristics 86CH49 86CM49 86PM49 [V] 5.5 4.5 3.6 [V] 5.5 4.5 3.6 (a) 3.0 2.7 2.0 1.8 0.030 0.034 1 4.2 8 16 [MHz] 0.030 0.034 1 4.2 8 (b) (Note 1) 16 [MHz] (a) [V] 5.5 (a) 4.5 3.6 3.0 2.7 1.8 0.030 0.034 1 4.2 8 16 [MHz] (Note 2) (b) 4.5 3.6 3.0 2.7 1.8 0.030 0.034 1 4.2 8 16 [MHz] (b) (Note 3) 1.8 0.030 0.034 1 4.2 8 16 [MHz] (a) 4.5 3.6 3.0 2.7 (a) [V] 5.5 [V] 5.5 86CS49 86FS49 86FS49A 86FS49B Read / Fetch 3.0 2.7 1.8 Operating condition (MCU mode) (a) 1.8V to 5.5V (-40 to 85C) (a) 2.0V to 5.5V (-40 to 85C) (b) 1.8V to 2.0V (-20 to 85C) (a) 4.5V to 5.5V (-40 to 85C) (b) 3.0V to 3.6V (-40 to 85C) (a) 3.0V to 5.5V (-40 to 85C) (b) 2.7V to 3.0V (-20 to 85C) [V] 5.5 4.5 (a) (a) 2.7V to 5.5V (-40 to 85C) Erase / Program 3.6 - - 3.0 2.7 1.8 0.030 0.034 1 4.2 8 16 [MHz] - - (a) 4.5V to 5.5V (-10 to 40C) [V] 5.5 4.5 (a) (Serial PROM mode) Operating condition 3.6 - - 3.0 2.7 1.8 0.030 0.034 2 4.2 8 16 [MHz] Operating Current - (a) 4.5V to 5.5V (-10 to 40C) Operating current varies with each product. For details, refer to the datasheet (electrical characteristics) of each product. (Note 4) Note 1: With the 86CS49, the operating temperature (Topr) is -20 C to 85 C when the supply voltage VDD is less than 2.0 V. Note 2: With the 86FS49, the supply voltage VDD is specified as two separate ranges. While the MCU is operating, do not change the supply voltage from range (a) to range (b) or from range (b) to range (a). Note 3: With the 86FS49A, the operating temperature (Topr) is -20 C to 85 C when the supply voltage VDD is less than 3.0 V. Note 4: With the 86FS49A/B, when a program is executing in the Flash memory or when data is being read from the Flash memory, the Flash memory operates in an intermittent manner causing peak currents in the Flash memory momentarily, as shown in Figure. In this case, the supply current IDD (in NORMAL1, NORMAL2 and SLOW1 modes) is defined as the sum of the average peak current and MCU current. 1 machine cycle (4/fc or 4/fs) Program counter (PC) I DDP-P [mA] n n+1 n+2 n+3 Momentary Flash current Max. current Sum of average momentary Typ. current Flash current and MCU current MCU current Intermittent Operation of Flash Memory TMP86FS49AFG Revision History Date 2006/2/22 2006/3/23 2006/7/6 2006/7/21 2006/10/18 2007/2/2 2007/2/2 2007/6/26 Revision 1 2 3 4 5 6 7 8 First Release Contents Revised Contents Revised Periodical updating.No change in contents. Contents Revised Periodical updating.No change in contents. Periodical updating.No change in contents. Contents Revised Table of Contents Differences among Products TMP86FS49AFG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Address Map............................................................................................................................... 9 Program Memory (Flash) .......................................................................................................................... 9 Data Memory (RAM) ................................................................................................................................. 9 Clock Generator...................................................................................................................................... 10 Timing Generator .................................................................................................................................... 12 Operation Mode Control Circuit .............................................................................................................. 13 Single-clock mode Dual-clock mode STOP mode Configuration of timing generator Machine cycle 2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2.1 2.2.2.2 2.2.3.1 2.2.3.2 2.2.3.3 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4 Operating Mode Control ......................................................................................................................... 18 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Reset Input ............................................................................................................................... Address trap reset .................................................................................................................................. Watchdog timer reset.............................................................................................................................. System clock reset.................................................................................................................................. 31 32 32 32 2.3.1 2.3.2 2.3.3 2.3.4 3. Interrupt Control Circuit 3.1 3.2 Interrupt latches (IL23 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt master enable flag (IMF) .......................................................................................................... 36 Individual interrupt enable flags (EF23 to EF4) ...................................................................................... 37 Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 3.3.2 Interrupt acceptance processing is packaged as follows........................................................................ 39 Saving/restoring general-purpose registers ............................................................................................ 40 Using PUSH and POP instructions 3.3.2.1 3.2.1 3.2.2 i 3.4 3.3.3 3.4.1 3.4.2 3.3.2.2 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Address error detection .......................................................................................................................... 42 Debugging .............................................................................................................................................. 42 Interrupt return ........................................................................................................................................ 41 Using data transfer instructions 3.5 3.6 3.7 4. Special Function Register (SFR) 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Port P0 (P07 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P37 to P30) (Large Current Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P54 to P50) (Large Current Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 52 54 55 56 58 59 62 6. Watchdog Timer (WDT) 6.1 6.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 66 67 68 68 69 6.3 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 70 70 70 71 6.3.1 6.3.2 6.3.3 6.3.4 7. Time Base Timer (TBT) 7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Configuration .......................................................................................................................................... 73 Control .................................................................................................................................................... 73 Function .................................................................................................................................................. 74 Configuration .......................................................................................................................................... 75 Control .................................................................................................................................................... 75 7.1.1 7.1.2 7.1.3 7.2.1 7.2.2 7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ii 8. 16-Bit TimerCounter 1 (TC1) 8.1 8.2 8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Timer mode............................................................................................................................................. External Trigger Timer Mode .................................................................................................................. Event Counter Mode ............................................................................................................................... Window Mode ......................................................................................................................................... Pulse Width Measurement Mode............................................................................................................ Programmable Pulse Generate (PPG) Output Mode ............................................................................. 80 82 84 85 86 89 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 9. 16-Bit Timer/Counter2 (TC2) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Timer mode............................................................................................................................................. 95 Event counter mode................................................................................................................................ 97 Window mode ......................................................................................................................................... 97 9.3.1 9.3.2 9.3.3 10. 8-Bit TimerCounter (TC3, TC4) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8-Bit Timer Mode (TC3 and 4) ............................................................................................................ 8-Bit Event Counter Mode (TC3, 4) .................................................................................................... 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)................................................................. 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4).............................................................. 16-Bit Timer Mode (TC3 and 4) .......................................................................................................... 16-Bit Event Counter Mode (TC3 and 4) ............................................................................................ 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)...................................................... 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ........................................... Warm-Up Counter Mode..................................................................................................................... Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 105 106 106 109 111 112 112 115 117 10.3.9.1 10.3.9.2 11. 8-Bit TimerCounter (TC5, TC6) 11.1 11.2 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8-Bit Timer Mode (TC5 and 6) ............................................................................................................ 8-Bit Event Counter Mode (TC5, 6) .................................................................................................... 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)................................................................. 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6).............................................................. 16-Bit Timer Mode (TC5 and 6) .......................................................................................................... 16-Bit Event Counter Mode (TC5 and 6) ............................................................................................ 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)...................................................... 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) ........................................... Warm-Up Counter Mode..................................................................................................................... Low-Frequency Warm-up Counter Mode 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.3.9 125 126 126 129 131 132 132 135 137 11.3.9.1 iii 11.3.9.2 (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 12. Asynchronous Serial interface (UART1 ) 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 144 Data Receive Operation ..................................................................................................................... 144 145 145 145 146 146 147 139 140 142 143 143 144 144 144 12.8.1 12.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 12.9.1 12.9.2 12.9.3 12.9.4 12.9.5 12.9.6 13. Asynchronous Serial interface (UART2 ) 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 154 Data Receive Operation ..................................................................................................................... 154 155 155 155 156 156 157 149 150 152 153 153 154 154 154 13.8.1 13.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 13.9.1 13.9.2 13.9.3 13.9.4 13.9.5 13.9.6 14. Synchronous Serial Interface (SIO1) 14.1 14.2 14.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Serial clock ......................................................................................................................................... 162 Transfer bit direction ........................................................................................................................... 164 Transmit mode Clock source Shift edge 14.3.1.1 14.3.1.2 14.3.2.1 14.3.1 14.3.2 iv 14.3.3 14.3.2.2 14.3.2.3 14.3.3.1 14.3.3.2 14.3.3.3 Transfer modes................................................................................................................................... 165 Transmit mode Receive mode Transmit/receive mode Receive mode Transmit/receive mode 15. Synchronous Serial Interface (SIO2) 15.1 15.2 15.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Serial clock ......................................................................................................................................... 180 Transfer bit direction ........................................................................................................................... 182 Transmit mode Receive mode Transmit/receive mode Transmit mode Receive mode Transmit/receive mode Clock source Shift edge 15.3.1.1 15.3.1.2 15.3.2.1 15.3.2.2 15.3.2.3 15.3.3.1 15.3.3.2 15.3.3.3 15.3.1 15.3.2 15.3.3 Transfer modes................................................................................................................................... 183 16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.1 16.2 16.3 16.4 16.5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Data Format in the I2C Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgement mode specification................................................................................................ 199 Number of transfer bits ....................................................................................................................... 200 Serial clock ......................................................................................................................................... 200 Clock source Clock synchronization Acknowledgment mode (ACK = "1") Non-acknowledgment mode (ACK = "0") 16.5.1.1 16.5.1.2 195 195 195 196 197 16.5.1 16.5.2 16.5.3 16.6 16.5.4 16.5.5 16.5.6 16.5.7 16.5.8 16.5.9 16.5.10 16.5.11 16.5.12 16.5.13 16.6.1 16.6.2 16.6.3 16.6.4 16.6.5 16.5.3.1 16.5.3.2 Data Transfer of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Device initialization ............................................................................................................................. 205 Start condition and slave address generation..................................................................................... 205 1-word data transfer............................................................................................................................ 205 Stop condition generation ................................................................................................................... 208 Restart ................................................................................................................................................ 209 When the MST is "1" (Master mode) When the MST is "0" (Slave mode) Slave address and address recognition mode specification ............................................................... Master/slave selection ........................................................................................................................ Transmitter/receiver selection............................................................................................................. Start/stop condition generation ........................................................................................................... Interrupt service request and cancel................................................................................................... Setting of I2C bus mode ..................................................................................................................... Arbitration lost detection monitor ...................................................................................................... Slave address match detection monitor............................................................................................ GENERAL CALL detection monitor .................................................................................................. Last received bit monitor................................................................................................................... 201 201 201 202 202 203 203 204 204 204 16.6.3.1 16.6.3.2 17. 10-bit AD Converter (ADC) 17.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 v 17.2 17.3 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Software Start Mode ........................................................................................................................... 215 Repeat Mode ...................................................................................................................................... 215 Register Setting ................................................................................................................................ 216 17.4 17.5 17.6 17.3.1 17.3.2 17.3.3 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 218 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Restrictions for AD Conversion interrupt (INTADC) usage ................................................................. Analog input pin voltage range ........................................................................................................... Analog input shared pins .................................................................................................................... Noise Countermeasure ....................................................................................................................... 219 219 219 219 17.6.1 17.6.2 17.6.3 17.6.4 18. Key-on Wakeup (KWU) 18.1 18.2 18.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19. Flash Memory 19.1 19.2 Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Byte Program ...................................................................................................................................... Sector Erase (4-kbyte Erase) ............................................................................................................. Chip Erase (All Erase) ........................................................................................................................ Product ID Entry ................................................................................................................................. Product ID Exit .................................................................................................................................... Read Protect ....................................................................................................................................... 225 225 226 226 226 226 Flash Memory Command Sequence Execution Control (FLSCR 19.3 19.4 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 Toggle Bit (D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Access to the Flash Memory Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Flash Memory Control in the Serial PROM Mode............................................................................... 228 Flash Memory Control in the MCU mode............................................................................................ 230 How to write to the flash memory by executing a user write control program in the RAM area (in the MCU mode) How to write to the flash memory by executing the control program in the RAM area (in the RAM loader mode within the serial PROM mode) 19.4.1 19.4.2 19.4.1.1 19.4.2.1 20. Serial PROM Mode 20.1 20.2 20.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Serial PROM Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Serial PROM Mode Control Pins ........................................................................................................ Pin Function........................................................................................................................................ Example Connection for On-Board Writing......................................................................................... Activating the Serial PROM Mode ...................................................................................................... 234 234 235 236 20.4 20.5 20.6 20.3.1 20.3.2 20.3.3 20.3.4 Interface Specifications for UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Operation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Flash Memory Erasing Mode (Operating command: F0H) ................................................................. 241 Flash Memory Writing Mode (Operation command: 30H) .................................................................. 243 RAM Loader Mode (Operation Command: 60H) ................................................................................ 246 20.6.1 20.6.2 20.6.3 vi 20.7 20.8 20.6.4 20.6.5 20.6.6 20.6.7 Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Checksum (SUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Calculation Method ............................................................................................................................. 254 Calculation data .................................................................................................................................. 255 Flash Memory SUM Output Mode (Operation Command: 90H) ......................................................... Product ID Code Output Mode (Operation Command: C0H).............................................................. Flash Memory Status Output Mode (Operation Command: C3H) ...................................................... Flash Memory Read Protection Setting Mode (Operation Command: FAH) ...................................... 248 249 251 252 20.9 Intel Hex Format (Binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.10 Passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.10.1 20.10.2 20.10.3 Password String................................................................................................................................ 257 Handling of Password Error .............................................................................................................. 257 Password Management during Program Development .................................................................... 257 20.8.1 20.8.2 20.11 20.12 20.13 20.14 20.15 Product ID Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Status Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Erasure Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 258 260 261 262 21. Input/Output Circuit 21.1 21.2 Control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 22. Electrical Characteristics 22.1 22.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 MCU mode (Flash Programming or erasing) ..................................................................................... 268 MCU mode (Except Flash Programming or erasing) ......................................................................... 268 Serial PROM mode ............................................................................................................................. 269 22.3 22.4 22.5 22.6 22.7 22.8 22.2.1 22.2.2 22.2.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write/Retention Characteristics .......................................................................................................... 272 270 271 272 272 22.6.1 Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 23. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). vii viii TMP86FS49AFG CMOS 8-Bit Microcontroller TMP86FS49AFG The TMP86FS49AFG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 61440 bytes of Flash Memory. It is pin-compatible with the TMP86CH49/CM49/CS49FG (Mask ROM version). The TMP86FS49AFG can realize operations equivalent to those of the TMP86CH49/CM49/CS49FG by programming the on-chip Flash Memory. Product No. TMP86FS49AFG ROM (FLASH) 61440 bytes RAM 2048 bytes Package QFP64-P-1414-0.80A MASK ROM MCU TMP86CH49/CM49/ CS49FG Emulation Chip TMP86C949XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 24interrupt sources (External : 5 Internal : 19) 3. Input / Output ports (56 pins) Large current output: 13pins (Typ. 20mA), LED direct drive 4. Watchdog Timer 5. Prescaler - Time base timer - Divider output function 6. 16-bit timer counter: 1 ch - Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 7. 16-bit timer counter: 1 ch - Timer, Event counter, Window modes This product uses the Super Flash technology under the licence of Silicon Storage Technology, Inc. Super Flash is registered trademark of Silicon Storage Technology, Inc. 060116EBP * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86FS49AFG 8. 8-bit timer counter : 4 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 9. 8-bit UART : 2 ch 10. High-Speed SIO: 2ch 11. Serial Bus Interface(I2C Bus): 1ch 12. 10-bit successive approximation type AD converter - Analog input: 16 ch 13. Key-on wakeup : 4 ch 14. Clock operation Single clock mode Dual clock mode 15. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz Release by Page 2 TMP86FS49AFG 1.2 Pin Assignment P14 (TC4/PDO4/PWM4/PPG4) P13 (TC3/PDO3/PWM3) P12 (PPG) P11 (DVO) P10 (TC1) P47 P46 (SCK2) P45 (SO2) P44 (SI2) P43 P42 (TXD2) P41 (RXD2) P40 P77 (AIN15) P76 (AIN14) P75 (AIN13) (INT3/TC2) P15 (PDO5/PWM5/TC5) P16 (PDO6/PWM6/PPG6/TC6) P17 (SCL) P50 (SDA) P51 P52 P53 P54 P30 P31 P32 P33 P34 P35 P36 P37 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET Figure 1-1 Pin Assignment Page 3 (STOP/INT5) P20 (INT0) P00 (BOOT/RXD1) P01 (TXD1) P02 (INT1) P03 (SI1) P04 (SO1) P05 (SCK1) P06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P74(AIN12) P73(AIN11) P72(AIN10) P71(AIN9) P70(AIN8) P67(AIN7/STOP3) P66(AIN6/STOP2) P65(AIN5/STOP1) P64(AIN4/STOP0) P63(AIN3) P62(AIN2) P61(AIN1) P60(AIN0) AVDD VAREF P07(INT2) 1.3 Block Diagram TMP86FS49AFG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86FS49AFG 1.4 Pin Names and Functions The TMP86FS49AFG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/3) Pin Name P07 INT2 P06 SCK1 Pin Number 17 Input/Output IO I IO IO IO O IO I IO I IO O IO I I IO I IO I O IO I O IO I I IO I O IO I O IO O IO O IO I IO O PORT07 External interrupt 2 input Functions 16 PORT06 Serial clock input/output 1 PORT05 Serial data output 1 PORT04 Serial data input 1 PORT03 External interrupt 1 input PORT02 UART data output 1 PORT01 UART data input 1 Serial PROM mode control input PORT00 External interrupt 0 input PORT17 TC6 input PDO6/PWM6/PPG6 output PORT16 TC5 input PDO5/PWM5 output PORT15 TC2 input External interrupt 3 input PORT14 TC4 input PDO4/PWM4/PPG4 output PORT13 TC3 input PDO3/PWM3 output PORT12 PPG output PORT11 Divider Output PORT10 TC1 input PORT22 Resonator connecting pins(32.768kHz) for inputting external clock PORT21 Resonator connecting pins(32.768kHz) for inputting external clock P05 SO1 P04 SI1 P03 INT1 P02 TXD1 P01 RXD1 BOOT P00 INT0 15 14 13 12 11 10 P17 TC6 PDO6/PWM6/PPG6 51 P16 TC5 PDO5/PWM5 50 P15 TC2 INT3 P14 TC4 PDO4/PWM4/PPG4 49 48 P13 TC3 PDO3/PWM3 47 P12 PPG 46 P11 DVO 45 P10 TC1 P22 XTOUT 44 7 P21 XTIN 6 IO I Page 5 1.4 Pin Names and Functions TMP86FS49AFG Table 1-1 Pin Names and Functions(2/3) Pin Name P20 INT5 STOP Pin Number Input/Output IO I I IO IO IO IO IO IO IO IO IO IO IO IO O IO I IO IO O IO I IO IO IO IO IO IO IO IO IO I I IO I I IO I I IO I I Functions PORT20 External interrupt 5 input STOP mode release signal input PORT37 PORT36 PORT35 PORT34 PORT33 PORT32 PORT31 PORT30 PORT47 PORT46 Serial clock input/output 2 PORT45 Serial data output 2 PORT44 Serial data input 2 PORT43 PORT42 UART data output 2 PORT41 UART data input 2 PORT40 PORT54 PORT53 PORT52 PORT51 I2C bus data PORT50 I2C bus clock PORT67 Analog Input7 STOP3 input PORT66 Analog Input6 STOP2 input PORT65 Analog Input5 STOP1 input PORT64 Analog Input4 STOP0 input 9 P37 P36 P35 P34 P33 P32 P31 P30 P47 P46 SCK2 64 63 62 61 60 59 58 57 43 42 P45 SO2 P44 SI2 P43 P42 TXD2 P41 RXD2 P40 P54 P53 P52 P51 SDA P50 SCL P67 AIN7 STOP3 P66 AIN6 STOP2 P65 AIN5 STOP1 P64 AIN4 STOP0 41 40 39 38 37 36 56 55 54 53 52 27 26 25 24 Page 6 TMP86FS49AFG Table 1-1 Pin Names and Functions(3/3) Pin Name P63 AIN3 P62 AIN2 P61 AIN1 P60 AIN0 P77 AIN15 P76 AIN14 P75 AIN13 P74 AIN12 P73 AIN11 P72 AIN10 P71 AIN9 P70 AIN8 XIN XOUT RESET Pin Number 23 Input/Output IO I IO I IO I IO I IO I IO I IO I IO I IO I IO I IO I IO I I O I I I I I I PORT63 Analog Input3 PORT62 Analog Input2 PORT61 Analog Input1 PORT60 Analog Input0 PORT77 Analog Input15 PORT76 Analog Input14 PORT75 Analog Input13 PORT74 Analog Input12 PORT73 Analog Input11 PORT72 Analog Input10 PORT71 Analog Input9 PORT70 Analog Input8 Functions 22 21 20 35 34 33 32 31 30 29 28 2 3 8 4 18 19 5 1 Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal Test pin for out-going test. Normally, be fixed to low. Analog Base Voltage Input Pin for A/D Conversion Analog Power Supply +5V 0(GND) TEST VAREF AVDD VDD VSS Page 7 1.4 Pin Names and Functions TMP86FS49AFG Page 8 TMP86FS49AFG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86FS49AFG memory is composed Flash, RAM, DBR(Data buffer register) and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86FS49AFG memory address map. 0000H SFR 003FH 0040H 64 bytes SFR: RAM 083FH 0F80H 2048 bytes RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack DBR: DBR 0FFFH 1000H 128 bytes Flash: Data buffer register includes: Peripheral control registers Peripheral status registers Program memory Flash FFB0H FFBFH FFC0H FFDFH FFE0H FFFFH 61440 bytes Vector table for interrupts (16 bytes) Vector table for vector call instructions (32 bytes) Vector table for interrupts (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (Flash) The TMP86FS49AFG has a 61440 bytes (Address 1000H to FFFFH) of program memory (Flash ). 2.1.3 Data Memory (RAM) The TMP86FS49AFG has 2048 bytes (Address 0040H to 083FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. Page 9 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to "00H". (TMP86FS49AFG) LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC, 07FFH (HL), A HL BC F, SRAMCLR ; Start address setup ; Initial value (00H) setup 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register Clock generator XIN fc TBTCR 0036H High-frequency clock oscillator XOUT XTIN Timing generator fs Standby controller 0038H SYSCR1 0039H SYSCR2 Low-frequency clock oscillator XTOUT System clocks Clock generator control System control registers Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 10 TMP86FS49AFG High-frequency clock XIN XOUT XIN XOUT (Open) XTIN Low-frequency clock XTOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 11 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 fc or fs Main system clock generator SYSCK DV7CK Machine cycle counters High-frequency clock fc Low-frequency clock fs 12 fc/4 S A 123456 B Y Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S B0 B1 A0 Y0 A1 Y1 Multiplexer Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 12 TMP86FS49AFG Timing Generator Control Register TBTCR (0036H) 7 (DVOEN) 6 (DVOCK) 5 4 DV7CK 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86FS49AFG is placed in this mode after reset. Page 13 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 Page 14 TMP86FS49AFG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 15 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG IDLE0 mode Reset release RESET IDLE1 mode (a) Single-clock mode Note 2 SYSCR2 IDLE2 mode Interrupt NORMAL2 mode SYSCR2 SLEEP1 mode (b) Dual-clock mode SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode High Frequency Low Frequency CPU Core TBT Other Peripherals Reset Operate 4/fc [s] Machine Cycle Time RESET NORMAL1 Single clock IDLE1 IDLE0 STOP NORMAL2 IDLE2 SLOW2 Dual clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Oscillation Stop Oscillation Reset Operate Stop Halt Reset Operate Halt Operate with high frequency Halt - 4/fc [s] Oscillation Halt Operate with low frequency Halt Operate with low frequency Operate Operate 4/fs [s] Halt Halt Halt - Page 16 TMP86FS49AFG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP RELM RETM OUTEN STOP mode start Release method for STOP mode Operating mode after STOP mode Port output during STOP mode 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) 0: Edge-sensitive release 1: Level-sensitive release 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output kept Return to NORMAL mode Return to SLOW mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W R/W R/W R/W WUT Warm-up time at releasing STOP mode 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 214/fc R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHALT 1 0 (Initial value: 1000 *0**) XEN XTEN High-frequency oscillator control Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) TG control (IDLE0 and SLEEP0 modes) 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W R/W SYSCK IDLE TGHALT Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator, *; Don't care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Page 17 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG 2.2.4 Operating Mode Control STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP3 to STOP0) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 2.2.4.1 Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP3 to STOP0). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOP3 to STOP0 pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP3 to STOP0 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP3 to STOP0 input is high. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS DI SET (SYSCR1). 7 (SYSCR1), 01010000B (P2PRD). 0 F, SSTOPH ; IMF 0 ; Starts STOP mode ; Sets up the level-sensitive release mode ; Wait until the STOP pin input goes low level Page 18 TMP86FS49AFG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1). 7 (P2PRD). 0 F, SINT5 (SYSCR1), 01010000B ; To reject noise, STOP mode does not start if port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 ; Starts STOP mode STOP pin XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. VIH Warm up NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP3 to STOP0 pin input for releasing STOP mode in edge-sensitive release mode. Example :Starting STOP mode from NORMAL mode DI LD (SYSCR1), 10010000B ; IMF 0 ; Starts after specified to the edge-sensitive release mode STOP pin XOUT pin NORMAL operation STOP mode started by the program. STOP operation VIH Warm up NORMAL operation STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode Page 19 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024 Return to SLOW Mode 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 20 Turn off Oscillator circuit Turn on Main system clock a+3 SET (SYSCR1). 7 n+1 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+2 n+3 n+4 Halt Program counter a+2 Instruction execution Divider n 0 Figure 2-9 STOP Mode Start/Release a+4 Instruction address a + 2 Page 21 0 1 (b) STOP mode release Warm up STOP pin input Oscillator circuit Turn off Turn on Main system clock a+5 Instruction address a + 3 Program counter a+3 a+6 Instruction address a + 4 Instruction execution Halt Divider 0 Count up 2 3 TMP86FS49AFG 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input No No Interrupt request Reset Yes "0" IMF Normal release mode "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 22 TMP86FS49AFG * Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 23 Main system clock 2.2 System Clock Controller 2. Operational Description Interrupt request Program counter a+2 SET (SYSCR2). 4 Operate a+3 Halt Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Main system clock Interrupt request Program counter a+3 Instruction address a + 2 Operate Normal release mode a+4 Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24 a+3 Acceptance of interrupt Operate Operate Interrupt release mode Instruction execution Halt Watchdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt Watchdog timer Halt TMP86FS49AFG (b) IDLE1/2 and SLEEP1/2 modes release TMP86FS49AFG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input No No TBT source clock falling edge Yes TBTCR Yes Reset No No (Normal release mode) Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 25 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG * Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR (1) Normal release mode (IMF*EF7*TBTCR (2) Interrupt release mode (IMF*EF7*TBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR Page 26 Main system clock Interrupt request a+2 a+3 Program counter Instruction execution SET (SYSCR2). 2 Halt Watchdog timer Operate (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Main system clock TBT clock a+3 a+4 Program counter Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27 Instruction address a + 2 Operate Normal release mode a+3 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt Acceptance of interrupt Operate Interrupt release mode (b) IDLE and SLEEP0 modes release TMP86FS49AFG Watchdog timer Halt 2. Operational Description 2.2 System Clock Controller TMP86FS49AFG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET LD LD LDW DI SET EI SET : PINTTC6: CLR SET (TC6CR). 3 (SYSCR2). 5 ; Stops TC6, 5 ; SYSCR2 Page 28 TMP86FS49AFG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET LD LD LD DI SET EI SET : PINTTC6: CLR CLR (TC6CR). 3 (SYSCR2). 5 ; Stops TC6, 5 ; SYSCR2 Page 29 2.2 System Clock Controller 2. Operational Description Highfrequency clock Lowfrequency clock Main system clock Turn off SYSCK XEN CLR (SYSCR2). 7 SLOW2 mode (a) Switching to the SLOW mode Instruction execution SET (SYSCR2). 5 NORMAL2 mode SLOW1 mode Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30 CLR (SYSCR2). 5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2). 7 TMP86FS49AFG SLOW1 mode NORMAL2 mode TMP86FS49AFG 2.3 Reset Circuit The TMP86FS49AFG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 MHz) when power is turned on. Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) (PC) (SP) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latches of I/O ports Not initialized Not initialized 0 0 Control registers 0 RAM Refer to each of control register Not initialized Refer to I/O port circuitry Watchdog timer Enable Prescaler and divider of timing generator 0 On-chip Hardware Initial Value 2.3.1 External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 31 2. Operational Description 2.3 Reset Circuit TMP86FS49AFG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution Internal reset JP a Address trap is occurred Reset release Instruction at address r maximum 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR, DBR or on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 System clock reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 Page 32 TMP86FS49AFG Page 33 2. Operational Description 2.3 Reset Circuit TMP86FS49AFG Page 34 TMP86FS49AFG 3. Interrupt Control Circuit The TMP86FS49AFG has a total of 24 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE FFEC FFEA FFE8 FFE6 FFE4 FFE2 FFE0 FFBE FFBC FFBA FFB8 FFB6 FFB4 FFB2 FFB0 Interrupt Factors Internal/External Internal Internal Internal Internal External Internal External Internal External Internal Internal Internal External Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal External (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INT0 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF4 = 1, INT0EN = 1 IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1 IMF* EF9 = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1 IMF* EF13 = 1 IMF* EF14 = 1 IMF* EF15 = 1 IMF* EF16 = 1 IMF* EF17 = 1 IMF* EF18 = 1 IMF* EF19 = 1 IMF* EF20 = 1 IMF* EF21 = 1 IMF* EF22 = 1 IMF* EF23 = 1 Priority 1 2 2 2 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 INTTC1 INT1 INTTBT INT2 INTTC4 INTTC3 INTSBI INT3 INTSIO1 INTSIO2 INTADC INTRXD1 INTTXD1 INTTC6 INTTC5 INTRXD2 INTTXD2 INTTC2 INT5 Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1 3.1 Interrupt latches (IL23 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. Page 35 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86FS49AFG The interrupt latches are located on address 002EH, 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 002CH, 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". Page 36 TMP86FS49AFG 3.2.2 Individual interrupt enable flags (EF23 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF23 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 37 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86FS49AFG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) (Initial value: 00000000) ILE (002EH) 7 IL23 6 IL22 5 IL21 4 IL20 3 IL19 2 IL18 1 IL17 0 IL16 ILE (002EH) IL23 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000***0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 EF14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) (Initial value: 00000000) EIRE (002CH) 7 EF23 6 EF22 5 EF21 4 EF20 3 EF19 2 EF18 1 EF17 0 EF16 EIRE (002CH) EF23 to EF4 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 38 TMP86FS49AFG 3.3 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFF0H FFF1H 03H D2H Vector D203H D204H 0FH 06H Figure 3-2 Vector table address,Entry address Page 39 3. Interrupt Control Circuit 3.3 Interrupt Sequence TMP86FS49AFG A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. 3.3.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP b-5 A b-4 SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction b-3 b-2 b-1 SP b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.3.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Page 40 TMP86FS49AFG Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Page 41 3. Interrupt Control Circuit 3.4 Software Interrupt (INTSW) TMP86FS49AFG Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.4.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM, DBR or SFR areas. 3.4.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.5 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.6 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). Page 42 TMP86FS49AFG 3.7 External Interrupts The TMP86FS49AFG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT3. The INT0/P00 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P00 pin function selection are performed by the external interrupt control register (EINTCR). Source Pin Enable Conditions Release Edge Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 IMF EF4 INT0EN=1 Falling edge INT1 INT1 IMF EF6 = 1 Falling edge or Rising edge INT2 INT2 IMF EF8 = 1 Falling edge or Rising edge INT3 INT3 IMF EF12 = 1 Falling edge or Rising edge INT5 INT5 IMF EF23 = 1 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 43 3. Interrupt Control Circuit 3.7 External Interrupts TMP86FS49AFG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 00** 000*) INT1NC INT0EN INT3 ES INT2 ES INT1 ES Noise reject time select P00/INT0 pin configuration INT3 edge select INT2 edge select INT1 edge select 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P00 input/output port 1: INT0 pin (Port P00 should be set to an input mode) 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge R/W R/W R/W R/W R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Page 44 TMP86FS49AFG 4. Special Function Register (SFR) The TMP86FS49AFG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86FS49AFG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H SIO1SR SIO1RDB TC2CR TC2DRL TC2DRH ADCDR2 ADCDR1 SIO1CR SIO1TDB P0PRD P2PRD P3PRD P4PRD P5PRD TC1DRAL TC1DRAH TC1DRBL TC1DRBH TTREG3 TTREG4 TTREG5 TTREG6 PWREG3 PWREG4 PWREG5 PWREG6 ADCCR1 ADCCR2 Read P0DR P1DR P2DR P3DR P4DR P5DR P6DR P7DR P0OUTCR P1CR P4OUTCR Write Page 45 4. Special Function Register (SFR) 4.1 SFR TMP86FS49AFG Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read TC1CR TC3CR TC4CR TC5CR TC6CR SIO2RDB EIRE Reserved ILE Reserved Reserved SIO2CR SIO2SR Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH Reserved PSW Write SIO2TDB - WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 46 TMP86FS49AFG 4.2 DBR Address 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H 0F8AH 0F8BH 0F8CH 0F8DH 0F8EH 0F8FH 0F90H 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH UART1SR RD1BUF UART2SR RD2BUF P6CR1 P6CR2 P7CR1 P7CR2 STOPCR SBISRB Reserved UART1CR1 UART1CR2 TD1BUF UART2CR1 UART2CR2 TD2BUF SBISRA SBIDBR I2CAR SBICRB Read Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SBICRA Write Address 0FA0H :: 0FBFH Read Reserved :: Reserved Write Address 0FC0H :: 0FDFH Read Reserved :: Reserved Write Page 47 4. Special Function Register (SFR) 4.2 DBR TMP86FS49AFG Address 0FE0H 0FE1H 0FE2H 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H 0FF1H 0FF2H 0FF3H 0FF4H 0FF5H 0FF6H 0FF7H 0FF8H 0FF9H 0FFAH 0FFBH 0FFCH 0FFDH 0FFEH 0FFFH Read Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FLSCR Write Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 48 TMP86FS49AFG 5. I/O Ports The TMP86FS49AFG has 8 parallel input/output ports (56 pins) as follows. Primary Function Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 8-bit I/O port 8-bit I/O port 3-bit I/O port 8-bit I/O port 8-bit I/O port 5-bit I/O port 8-bit I/O port 8-bit I/O port Serial interface input/output and UART input/output. Serial bus interface input/output. Analog input and key-on wakeup input. Analog input. Secondary Functions External interrupt, Serial PROM mode cotrol input, serial interface input/output, UART input/output. External interrupt, timer counter input/output, divider output. Low-frequency resonator connections, external interrupt input, STOP mode release signal input. Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. Figure 5-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle S0 S1 S2 S3 Fetch cycle S0 S1 S2 S3 Read cycle S0 S1 S2 S3 Instruction execution cycle Example: LD A, (x) Input strobe Data input (a) Input timing Fetch cycle S0 S1 S2 S3 Fetch cycle S0 S1 S2 S3 Write cycle S0 S1 S2 S3 Instruction execution cycle Example: LD (x), A Output strobe Old (b) Output timing New Data output Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 5-1 Input/Output Timing (Example) Page 49 5. I/O Ports 5.1 Port P0 (P07 to P00) TMP86FS49AFG 5.1 Port P0 (P07 to P00) Port P0 is an 8-bit input/output port. Port P0 is also used as an external interrupt input, Serial PROM mode control input, a serial interface input/output and an UART input/output. When used as an input port, an external interrupt input, a serial interface input/output and an UART input/output, the corresponding output latch (P0DR) should be set to "1". During reset, the P0DR is initialized to "1", and the P0OUTCR is initialized to "0". It can be selected whether output circuit of P0 port is a C-MOS output or a sink open drain individually, by setting P0OUTCR. When a corresponding bit of P0OUTCR is "0". the output circuit is selected to a sink open drain and when a corresponding bit of P0OUTCR is "1", the output circuit is selected to a C-MOS output. When used as an input port, an external interrupt input, a serial interface input and an UART input, the corresponding output control (P0OUTCR) should be set to "0" after P0DR is set to "1". P0 port output latch (P0DR) and P0 port terminal input (P0PRD) are located on their respective address. When read the output latch data, the P0DR should be read. When read the terminal input data, the P0PRD register should be read. Table 5-1 Register Programming for Multi-function Ports (P07 to P00) Programmed Value Function P0DR Port input, external input, serial interface input or UART input, Serial PROM mode cotrol input Port "0" output Port "1" output, serial interface output or UART output "1" "0" "1" P0OUTCR "0" Programming for each applications STOP OUTEN P0OUTCRi P0OUTCRi input Data input (P0PRD) Output latch read (P0DR) Data output (P0DR) Control output Control input Note: i = 7 to 0 D Q D Q P0i Output latch Figure 5-2 Port 0 and P0OUTCR Page 50 TMP86FS49AFG P0DR (0000H) R/W 7 P07 INT2 6 P06 SCK1 5 P05 SO1 4 P04 SI1 3 P03 INT1 2 P02 TXD1 1 P01 RXD1 BOOT 0 P00 INT0 (Initial value: 1111 1111) P0OUTCR (0008H) (Initial value: 0000 0000) P0OUTCR Port P0 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: C-MOS output R/W P0PRD (000BH) Read only P07 P06 P05 P04 P03 P02 P01 P00 Page 51 5. I/O Ports 5.2 Port P1 (P17 to P10) TMP86FS49AFG 5.2 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P1 is also used as a timer/counter input/output, an external interrupt input and a divider output. Input/output mode is specified by the P1 control register (P1CR). During reset, the P1CR is initialized to "0" and port P1 becomes an input mode. And the P1DR is initialized to "0". When used as an input port, a timer/counter input and an external interrupt input, the corresponding bit of P1CR should be set to "0". When used as an output port, the corresponding bit of P1CR should be set to "1". When used as a timer/counter output and a divider output, P1DR is set to "1" beforehand and the corresponding bit of P1CR should be set to "1". When P1CR is "1", the content of the corresponding output latch is read by reading P1DR. Table 5-2 Register Programming for Multi-function Ports Programmed Value Function P1DR Port input, timer/counter input or external interrupt input Port "0" output Port "1" output, a timer output or a divider output * "0" "1" P1CR "0" "1" "1" Note: Asterisk (*) indicates "1" or "0" either of which can be selected. STOP OUTEN P1CRi P1CRi input D Q Data input (P1DR) Data output (P1DR) Control output Control input Note: i = 7 to 0 D Q P1i Output latch Figure 5-3 Port 1 and P1CR Note: The port set to an input mode reads the terminal input data. Therefore, when the input and output modes are used together, the content of the output latch which is specified as input mode might be changed by executing a bit Manipulation instruction. Page 52 TMP86FS49AFG 7 P1DR (0001H) R/W P17 TC6 PWM6 PDO6 PPG6 6 P16 TC5 PWM5 PDO5 5 P15 TC2 INT3 4 P14 TC4 PWM4 PDO4 PPG4 3 P13 TC3 PWM3 PDO3 2 P12 PPG 1 P11 DVO 0 P10 TC1 (Initial value: 0000 0000) P1CR (0009H) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P1CR I/O control for port P1 (Specified for each bit) 0: Input mode 1: Output mode R/W Page 53 5. I/O Ports 5.3 Port P2 (P22 to P20) TMP86FS49AFG 5.3 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set to "1". During reset, the P2DR is initialized to "1". A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dualclock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports. It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address. When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD register should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable. Data input (P20PRD) Data input (P20) Data output (P20) Contorl input Data input (P21PRD) Output latch read (P21) Data output (P21) Data input (P22PRD) Output latch read (P22) Data output (P22) D Q D Q D Q P20 (INT5, STOP) Output latch Osc. enable P21 (XTIN) Output latch P22 (XTOUT) Output latch STOP OUTEN XTEN fs Figure 5-4 Port 2 P2DR (0002H) R/W 7 6 5 4 3 2 P22 XTOUT 1 P21 XTIN 0 P20 INT5 STOP (Initial value: **** *111) P2PRD (000CH) Read only P22 P21 P20 Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes high-Z mode. Page 54 TMP86FS49AFG 5.4 Port P3 (P37 to P30) (Large Current Port) Port P3 is an 8-bit input/output port. When used as an input port, the corresponding output latch (P3DR) should be set to "1". During reset, the P3DR is initialized to "1". P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address. When read the output latch data, the P3DR should be read. When read the terminal input data, the P3PRD register should be read. STOP OUTEN Data input (P3PRD) Output latch read (P3DR) Data output (P3DR) D Q P3i Note: i = 7 to 0 Figure 5-5 Port 3 P3DR (0003H) R/W 7 P37 6 P36 5 P35 4 P34 3 P33 2 P32 1 P31 0 P30 (Initial value: 1111 1111) P3PRD (000DH) Read only P37 P36 P35 P34 P33 P32 P31 P30 Page 55 5. I/O Ports 5.5 Port P4 (P47 to P40) TMP86FS49AFG 5.5 Port P4 (P47 to P40) Port P4 is an 8-bit input/output port. Port P4 is also used as a serial interface input/output and an UART input/output. When used as an input port, a serial interface input/output and an UART input/output, the corresponding output latch (P4DR) should be set to "1". During reset, the P4DR is initialized to "1", and the P4OUTCR is initialized to "0". It can be selected whether output circuit of P4 port is a C-MOS output or a sink open drain individually, by setting P4OUTCR. When a corresponding bit of P4OUTCR is "0". the output circuit is selected to a sink open drain and when a corresponding bit of P4OUTCR is "1", the output circuit is selected to a C-MOS output. When used as an input port, a serial interface input and an UART input, the corresponding output control (P4OUTCR) should be set to "0" after P4DR is set to "1". P4 port output latch (P4DR) and P4 port terminal input (P4PRD) are located on their respective address. When read the output latch data, the P4DR should be read. When read the terminal input data, the P4PRD register should be read. Table 5-3 Register Programming for Multi-function Ports (P47 to P40) Programmed Value Function P4DR Port input UART input or serial interface input Port "0" output Port "1" output UART output or serial interface output "1" "0" "1" P4OUTCR "0" Programming for each applications STOP OUTEN P4OUTCRi P4OUTCRi input Data input (P4PRD) Output latch read (P4DR) Data output (P4DR) Control output Control input Note: i = 7 to 0 D Q D Q P4i Output latch Figure 5-6 Port 4 Page 56 TMP86FS49AFG P4DR (0004H) R/W 7 P47 6 P46 SCK2 5 P45 SO2 4 P44 SI2 3 P43 2 P42 TXD2 1 P41 RXD2 0 P40 (Initial value: 1111 1111) P4OUTCR (000AH) (Initial value: 0000 0000) P4OUTCR Port P4 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: C-MOS output R/W P4PRD (000EH) Read only P47 P46 P45 P44 P43 P42 P41 P40 Page 57 5. I/O Ports 5.6 Port P5 (P54 to P50) (Large Current Port) TMP86FS49AFG 5.6 Port P5 (P54 to P50) (Large Current Port) Port P5 is an 5-bit input/output port. Port P5 is also used as an I2C Bus input/output. When used as an input port and I2C Bus input/output, the corresponding output latch (P5DR) should be set to "1". During reset, the P5DR is initialized to "1". P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address. When read the output latch data, the P5DR should be read. When read the terminal input data, the P5PRD register should be read. If a read instruction is executed for port P5, read data of bit 7 to 5 are unstable. STOP OUTEN Data input (P5PRD) Output latch read (P5DR) Data output (P5DR) Control output Control input Note: i = 4 to 0 D Q P5i Output latch Figure 5-7 Port 5 P5DR (0005H) R/W 7 6 5 4 P54 3 P53 2 P52 1 P51 SDA 0 P50 SCL (Initial value: ***1 1111) P5PRD (000FH) Read only P54 P53 P52 P51 P50 Page 58 TMP86FS49AFG 5.7 Port P6 (P67 to P60) Port P6 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P6 is also used as an analog input and key-on wakeup input. Input/output mode is specified by the P6 control register (P6CR1) and P6 input control register (P6CR2). During reset, the P6CR1 is initialized to "0" the P6CR2 is initialized to "1" and port P6 becomes an input mode. And the P6DR is initialized to "0". When used as an output port, the corresponding bit of P6CR1 should be set to "1". When used as an input port , the corresponding bit of P6CR1 should be set to "0" and then, the corresponding bit of P6CR2 should be set to "1". When used as a key-on wakeup input , the corresponding bit of P6CR1 should be set to "0" and then, the corresponding bit of STOPkEN should be set to "1". When used as an analog input, the corresponding bit of P6CR1 should be set to "0" and then, the corresponding bit of P6CR2 should be set to "0". When P6CR1 is "1", the content of the corresponding output latch is read by reading P6DR. Table 5-4 Register Programming for Multi-function Ports Programmed Value Function P6DR Port input Key-on wakeup input Analog input Port "0" output Port "1" output * * * "0" "1" P6CR1 "0" "0" "0" "1" "1" P6CR2 "1" * "0" * * STOPkEN * "1" * * * Note: Asterisk (*) indicates "1" or "0" either of which can be selected. Table 5-5 Values Read from P6DR and Register Programming Conditions Values Read from P6DR P6CR1 "0" "0" "1" "1" P6CR2 "0" "1" "0" Output latch contents "0" Terminal input data Page 59 5. I/O Ports 5.7 Port P6 (P67 to P60) TMP86FS49AFG P6CR2i P6CR2i input P6CR1i P6CR1i input Control input Data input (P6DRi) D Q D Q Data output (P6DRi) STOP OUTTEN Analog input AINDS SAIN D Q P6i a) P63 to P60 Key-on wakeup STOPkEN P6CR2j P6CR2j input P6CR1j P6CR1j input Data input (P6DRj) D Q D Q Data output (P6DRj) STOP OUTTEN Analog input AINDS SAIN D Q P6j b) P67 to P64 Note 1: i = 3 to 0, j = 7 to 4, k = 3 to 0 Note 2: STOP is bit7 in SYSCR1. Note 3: SAIN is AD input select signal. Note 4: STOPkEN is input select signal in a key-on wakeup. Figure 5-8 Port 6, P6CR1 and P6CR2 Page 60 TMP86FS49AFG P6DR (0006H) R/W 7 P67 AIN7 STOP3 6 P66 AIN6 STOP2 5 P65 AIN5 STOP1 4 P64 AIN4 STOP0 3 P63 AIN3 2 P62 AIN2 1 P61 AIN1 0 P60 AIN0 (Initial value: 0000 0000) P6CR1 (0F9BH) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P6CR1 I/O control for port P6 (Specified for each bit) 0: Input mode 1: Output mode R/W P6CR2 (0F9CH) 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) P6CR2 P6 port input control (Specified for each bit) 0: Analog input 1: Port input R/W Note 1: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. Note 2: When used as an analog inport, be sure to clear the corresponding bit of P6CR2 to disable the port input. Note 3: Do not set the output mode (P6CR1 = "1") for the pin used as an analog input pin. Note 4: Pins not used for analog input can be used as I/O ports. During AD conversion, output instructions should not be executed to keep a precision. In addition, a variable signal should not be input to a port adjacent to the analog input during AD conversion. Page 61 5. I/O Ports 5.8 Port P7 (P77 to P70) TMP86FS49AFG 5.8 Port P7 (P77 to P70) Port P7 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. Port P7 is also used as an analog input. Input/output mode is specified by the P7 control register (P7CR1) and P7 input control register (P7CR2). During reset, the P7CR1 is initialized to "0" the P7CR2 is initialized to "1" and port P7 becomes an input mode. And the P7DR is initialized to "0". When used as an output port, the corresponding bit of P7CR1 should be set to "1". When used as an input port, the corresponding bit of P7CR1 should be set to "0" and then, the corresponding bit of P7CR2 should be set to "1". When used as an analog input, the corresponding bit of P7CR1 should be set to "0" and then, the corresponding bit of P7CR2 should be set to "0". When P7CR1 is "1", the content of the corresponding output latch is read by reading P7DR. Table 5-6 Register Programming for Multi-function Ports Programmed Value Function P7DR Port input external interrupt input or key-on wakeup input Analog input Port "0" output Port "1" output * * "0" "1" P7CR1 "0" "0" "1" "1" P7CR2 "1" "0" * * Note: Asterisk (*) indicates "1" or "0" either of which can be selected. Table 5-7 Values Read from P7DR and Register Programming Conditions Values Read from P7DR P7CR1 "0" "0" "1" "1" P7CR2 "0" "1" "0" Output latch contents "0" Terminal input data Page 62 TMP86FS49AFG P7CR2i P7CR2i input P7CR1i P7CR1i input Control input Data input (P7DRi) D Q D Q Data output (P7DRi) STOP OUTTEN Analog input AINDS SAIN Note 1: i = 7 to 0 Note 2: STOP is bit7 in SYSCR1. Note 3: SAIN is AD input select signal. D Q P7i Figure 5-9 Port 7, P7CR1 and P7CR2 P7DR (0007H) R/W 7 P77 AIN15 6 P76 AIN14 5 P75 AIN13 4 P74 AIN12 3 P73 AIN11 2 P72 AIN10 1 P71 AIN9 0 P70 AIN8 (Initial value: 0000 0000) P7CR1 (0F9DH) 7 6 5 4 3 2 1 0 (Initial value: 0000 0000) P7CR1 I/O control for port P7 (Specified for each bit) 0: Input mode 1: Output mode R/W P7CR2 (0F9EH) 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) P7CR2 P7 port input control (Specified for each bit) 0: Analog input 1: Port input, external interrupt input or key-on wakeup input R/W Note 1: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. Note 2: When used as an analog inport, be sure to clear the corresponding bit of P7CR2 to disable the port input. Note 3: Do not set the output mode (P7CR1 = "1") for the pin used as an analog input pin. Note 4: Pins not used for analog input can be used as I/O ports. During AD conversion, output instructions should not be executed to keep a precision. In addition, a variable signal should not be input to a port adjacent to the analog input during AD conversion. Page 63 5. I/O Ports 5.8 Port P7 (P77 to P70) TMP86FS49AFG Page 64 TMP86FS49AFG 6. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 Watchdog Timer Configuration Reset release fc/2 or fs/2 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 23 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 6-1 Watchdog Timer Configuration Page 65 6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86FS49AFG 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 66 TMP86FS49AFG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 217/fs 215/fs 213/fs 211/fs SLOW1/2 mode 217/fs 215fs 213fs 211/fs Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "6.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 6.2.2 Watchdog Timer Enable Setting WDTCR1 Page 67 6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86FS49AFG 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary counter : WDTEN 0, WDTCR2 Disable code Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m NORMAL1/2 mode DV7CK = 1 4 1 250 m 62.5 m SLOW mode 4 1 250 m 62.5 m 6.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 083FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 68 TMP86FS49AFG 6.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs Write 4EH to WDTCR2 Figure 6-2 Watchdog Timer Interrupt Page 69 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86FS49AFG 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area Select operation at address trap 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is required) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 6.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 6.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 6.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 70 TMP86FS49AFG 6.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 71 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86FS49AFG Page 72 TMP86FS49AFG 7. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration MPX fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 7-1 Time Base Timer configuration 7.1.2 Control Time Base Timer is controlled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 fc/223 fc/221 fc/216 fc/2 14 DV7CK = 1 fs/215 fs/213 fs/28 fs/2 6 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - - - - - - R/W TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/213 fc/2 12 fs/25 fs/2 4 fc/211 fc/2 9 fs/23 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 73 7. Time Base Timer (TBT) 7.1 Time Base Timer TMP86FS49AFG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRL) . 7 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 7-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 7.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generator which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 7-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 7-2 Time Base Timer Interrupt Page 74 TMP86FS49AFG 7.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 7.2.1 Configuration Output latch Data output D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 7-3 Divider Output 7.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 fs/25 fs/24 fs/23 fs/22 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 75 7. Time Base Timer (TBT) 7.2 Divider Output (DVO) TMP86FS49AFG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k Page 76 MCAP1 S A TC1S Y INTTC1 interript 8.1 Configuration B 2 Decoder Command start Start MPPG1 TC1S clear Pulse width measurement mode External trigger External trigger start PPG output mode Set Q Rising Falling Clear Edge detector METT1 TC1 Clear Y 8. 16-Bit TimerCounter 1 (TC1) Port (Note) D Figure 8-1 TimerCounter 1 (TC1) 16-bit up-counter S Page 77 Source clock Match CMP Pulse width measurement mode fc/211, fs/23 A B fc/27 B Y A fc/23 C S Toggle Q 2 Window mode Clear Selector S Q Set Set Clear Port (Note) PPG output mode Internal reset Toggle Enable pin Capture TC1DRB TC1DRA 16-bit timer register A, B ACAP1 TC1CK TC1CR Write to TC1CR TFF1 TC1 control register TMP86FS49AFG Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". 8. 16-Bit TimerCounter 1 (TC1) 8.2 TimerCounter Control TMP86FS49AFG 8.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register 15 TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC1DRAH (0011H) (Initial value: 1111 1111 1111 1111) TC1DRBH (0013H) (Initial value: 1111 1111 1111 1111) TC1DRAL (0010H) Read/Write TC1DRBL (0012H) Read/Write (Write enabled only in the PPG output mode) TimerCounter 1 Control Register 7 TC1CR (0026H) 6 ACAP1 MCAP1 METT1 MPPG1 5 4 3 2 1 0 Read/Write (Initial value: 0000 0000) TFF1 TC1S TC1CK TC1M TFF1 ACAP1 MCAP1 METT1 MPPG1 Timer F/F1 control Auto capture control Pulse width measurement mode control External trigger timer mode control PPG output control 0: Clear 0:Auto-capture disable 0:Double edge capture 0:Trigger start 0:Continuous pulse generation Timer 00: Stop and counter clear 01: Command start 10: Rising edge start (Ex-trigger/Pulse/PPG) Rising edge count (Event) Positive logic count (Window) 11: Falling edge start (Ex-trigger/Pulse/PPG) Falling edge count (Event) Negative logic count (Window) O O 1: Set 1:Auto-capture enable 1:Single edge capture R/W R/W 1:Trigger start and stop 1:One-shot Extrigger O - Event O - Window O - Pulse O - PPG O O TC1S TC1 start control - O O O O O R/W - O O O O O NORMAL1/2, IDLE1/2 mode DV7CK = 0 TC1CK TC1 source clock select [Hz] 00 01 10 11 TC1 operating mode select fc/211 fc/27 fc/23 DV7CK = 1 fs/23 fc/27 fc/23 External clock (TC1 pin input) Divider SLOW, SLEEP mode fs/23 - - R/W DV9 DV5 DV1 TC1M 00: Timer/external trigger timer/event counter mode 01: Window mode 10: Pulse width measurement mode 11: PPG (Programmable pulse generate) output mode R/W Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (TC1DRAH and TC1DRBH) is written. Therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing only the lower byte (TC1DRAL and TC1DRBL) does not enable the setting of the timer register. Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC1CR during TC1S=00. Set the timer F/ F1 control until the first timer start after setting the PPG mode. Page 78 TMP86FS49AFG Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other modes) Note 6: Set TFF1 to "0" in the mode except PPG output mode. Note 7: Set TC1DRB after setting TC1M to the PPG output mode. Note 8: When the STOP mode is entered, the start control (TC1S) is cleared to "00" automatically, and the timer stops. After the STOP mode is exited, set the TC1S to use the timer counter again. Note 9: Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Note 10:Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR Page 79 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS49AFG 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC1DRA) value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC1CR NORMAL1/2, IDLE1/2 mode TC1CK DV7CK = 0 Resolution [s] 00 01 10 128 8.0 0.5 Maximum Time Setting [s] 8.39 0.524 32.77 m Resolution [s] 244.14 8.0 0.5 DV7CK = 1 Maximum Time Setting [s] 16.0 0.524 32.77 m Resolution [s] 244.14 - - Maximum Time Setting [s] 16.0 - - SLOW, SLEEP mode Example 1 :Setting the timer mode with source clock fc/211 [Hz] and generating an interrupt 1 second later (fc = 16 MHz, TBTCR LDW DI SET EI LD LD (TC1CR), 00000000B (TC1CR), 00010000B (EIRL). 5 (TC1DRA), 1E84H ; Sets the timer register (1 s / 211/fc = 1E84H) ; IMF= "0" ; Enables INTTC1 ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 Example 2 :Auto-capture LD : LD (TC1CR), 01010000B : WA, (TC1DRB) ; Reads the capture value ; ACAP1 1 Note: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR Page 80 TMP86FS49AFG Timer start Source clock Counter TC1DRA 0 1 2 3 4 n-1 n 0 1 2 3 4 5 6 7 ? n INTTC1 interruput request Match detect (a) Timer mode Counter clear Source clock Counter m-2 m-1 m m+1 m+2 n-1 n n+1 Capture Capture m+1 m+2 n-1 TC1DRB ? m-1 m n n+1 ACAP1 (b) Auto-capture Figure 8-2 Timer Mode Timing Chart Page 81 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS49AFG 8.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC1CR Since the TC1 pin input has the noise rejection, pulses of 4/fc [s] or less are rejected as noise. A pulse width of 12/fc [s] or more is required to ensure edge detection. The rejection circuit is turned off in the SLOW1/2 or SLEEP1/2 mode, but a pulse width of one machine cycle or more is required. Example 1 :Generating an interrupt 1 ms after the rising edge of the input pulse to the TC1 pin (fc =16 MHz) LDW DI SET EI LD LD (TC1CR), 00000100B (TC1CR), 00100100B (EIRL). 5 (TC1DRA), 007DH ; 1ms / 27/fc = 7DH ; IMF= "0" ; Enables INTTC1 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 0 Example 2 :Generating an interrupt when the low-level pulse with 4 ms or more width is input to the TC1 pin (fc =16 MHz) LDW DI SET EI LD LD (TC1CR), 00000100B (TC1CR), 01110100B (EIRL). 5 (TC1DRA), 01F4H ; 4 ms / 27/fc = 1F4H ; IMF= "0" ; Enables INTTC1 interrupt ; IMF= "1" ; Selects the source clock and mode ; Starts TC1 external trigger, METT1 = 1 Page 82 TMP86FS49AFG Count start TC1 pin input Count start At the rising edge (TC1S = 10) Source clock Up-counter 0 1 2 3 4 n-1 n 0 1 2 3 TC1DRA n Match detect Count clear INTTC1 interrupt request (a) Trigger start (METT1 = 0) At the rising edge (TC1S = 10) Count start Count clear Count start TC1 pin input Source clock Up-counter 0 1 2 3 m-1 m 0 1 2 3 n 0 TC1DRA n Match detect Count clear INTTC1 interrupt request Note: m < n (b) Trigger start and stop (METT1 = 1) Figure 8-3 External Trigger Timer Mode Timing Chart Page 83 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS49AFG 8.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC1CR Timer start TC1 pin Input Up-counter TC1DRA INTTC1 interrput request ? 0 1 2 n-1 n 0 1 2 At the rising edge (TC1S = 10) n Match detect Counter clear Figure 8-4 Event Counter Mode Timing Chart Table 8-2 Input Pulse Width to TC1 Pin Minimum Pulse Width [s] NORMAL1/2, IDLE1/2 Mode High-going Low-going 23/fc 23/fc SLOW1/2, SLEEP1/2 Mode 23/fs 23/fs Page 84 TMP86FS49AFG 8.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared. Define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with TC1CR Count start Timer start Count stop Count start TC1 pin input Internal clock Counter TC1DRA INTTC1 interrput request ? 7 Match detect (a) Positive logic (TC1S = 10) Timer start Count start Count stop Count start 0 1 2 3 4 5 6 7 0 1 2 3 Counter clear TC1 pin input Internal clock Counter TC1DRA INTTC1 interrput request (b) Negative logic (TC1S = 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 90 1 Figure 8-5 Window Mode Timing Chart Page 85 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS49AFG 8.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC1CR Note 1: The captured value must be read from TC1DRB until the next trigger edge is detected. If not read, the captured value becomes a don't care. It is recommended to use a 16-bit access instruction to read the captured value from TC1DRB. Note 2: For the single-edge capture, the counter after capturing the value stops at "1" until detecting the next edge. Therefore, the second captured value is "1" larger than the captured value immediately after counting starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value. Page 86 TMP86FS49AFG Example :Duty measurement (resolution fc/27 [Hz]) CLR LD DI SET EI LD : PINTTC1: CPL JRS LD LD LD RETI SINTTC1: LD LD LD : RETI : VINTTC1: DW PINTTC1 ; INTTC1 Interrupt vector ; Duty calculation A, (TC1DRBL) W,(TC1DRBH) (WIDTH), WA ; Stores cycle in RAM ; Reads TC1DRB (Cycle) (INTTC1SW). 0 F, SINTTC1 A, (TC1DRBL) W,(TC1DRBH) (HPULSE), WA ; Stores high-level pulse width in RAM ; Reads TC1DRB (High-level pulse width) ; INTTC1 interrupt, inverts and tests INTTC1 service switch (TC1CR), 00100110B (EIRL). 5 (INTTC1SW). 0 (TC1CR), 00000110B ; INTTC1 service switch initial setting Address set to convert INTTC1SW at each INTTC1 ; Sets the TC1 mode and source clock ; IMF= "0" ; Enables INTTC1 ; IMF= "1" ; Starts TC1 with an external trigger at MCAP1 = 0 WIDTH HPULSE TC1 pin INTTC1 interrupt request INTTC1SW Page 87 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS49AFG Count start TC1 pin input Trigger Count start (TC1S = "10") Internal clock Counter TC1DRB INTTC1 interrupt request 0 1 2 3 4 n-1 n 0 1 Capture n 2 3 [Application] High-or low-level pulse width measurement (a) Single-edge capture (MCAP1 = "1") Count start Count start (TC1S = "10") TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request 0 1 2 3 4 n+1 n n+1 n+2 n+3 Capture n m-2 m-1 m 0 1 Capture m 2 [Application] (1) Cycle/frequency measurement (2) Duty measurement (b) Double-edge capture (MCAP1 = "0") Figure 8-6 Pulse Width Measurement Mode Page 88 TMP86FS49AFG 8.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC1CR Since the output level of the PPG pin can be set with TC1CR Note 1: To change TC1DRA or TC1DRB during a run of the timer, set a value sufficiently larger than the count value of the counter. Setting a value smaller than the count value of the counter during a run of the timer may generate a pulse different from that specified. Note 2: Do not change TC1CR Page 89 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS49AFG Example :Generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 MHz) Setting port LD LDW LDW LD (TC1CR), 10000111B (TC1DRA), 007DH (TC1DRB), 0019H (TC1CR), 10010111B ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc ms = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc = 16 MHz) Setting port LD LDW LDW LD : LD LD LD LD (TC1CR), 10000111B (TC1DRA), 007DH (TC1DRB), 0019H (TC1CR), 10010111B : (TC1CR), 10000111B (TC1CR), 10000100B (TC1CR), 00000111B (TC1CR), 00010111B ; Stops the timer ; Sets the timer mode ; Sets the PPG mode, TFF1 = 0 ; Starts the timer ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms / 27/fc s = 007DH) ; Sets the low-level pulse width (200 s / 27/fc = 0019H) ; Starts the timer I/O port output latch shared with PPG output Port output enable PPG pin Data output D R Q Function output TC1CR Set Clear Toggle Q Timer F/F1 INTTC1 interrupt request TC1CR Figure 8-7 PPG Output Page 90 TMP86FS49AFG Timer start Internal clock Counter 0 1 2 n n+1 m0 1 2 n n+1 m0 1 2 TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Note: m > n (a) Continuous pulse generation (TC1S = 01) Count start TC1 pin input Trigger Internal clock Counter 0 1 n n+1 m 0 TC1DRB n TC1DRA m PPG pin output INTTC1 interrupt request [Application] One-shot pulse output (b) One-shot pulse generation (TC1S = 10) Note: m > n Figure 8-8 PPG Mode Timing Chart Page 91 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FS49AFG Page 92 TMP86FS49AFG 9. 16-Bit Timer/Counter2 (TC2) 9.1 Configuration TC2S H Window TC2 pin Port (Note) fc/2 fs/2 fc/213, fs/25 fc/28 fc/23 23, 15 fc fs A B C D E F S B Timer/ event counter Clear Y A S Source clock 16-bit up counter TC2M CMP Match INTTC2 interrupt 3 TC2CK TC2S TC2CR TC2DR 16-bit timer register 2 TC2 control register Note: When control input/output is used, I/O port setting should be set correctly. For details, refer to the section "I/O ports". Figure 9-1 Timer/Counter2 (TC2) Page 93 9. 16-Bit Timer/Counter2 (TC2) 9.2 Control TMP86FS49AFG 9.2 Control The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TC2DR (0025H, 0024H) TC2DRH (0025H) (Initial value: 1111 1111 1111 1111) TC2DRL (0024H) R/W TC2CR (0023H) 7 6 5 TC2S 4 3 TC2CK 2 1 0 TC2M (Initial value: **00 00*0) TC2S TC2 start control 0:Stop and counter clear 1:Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 000 001 fc/223 fc/213 fc/28 fc/2 - fs 3 R/W SLOW1/2 mode fs/215 fs/25 - - fc (Note7) - SLEEP1/2 mode fs/215 fs/25 - - - - R/W DV7CK = 1 fs/215 fs/25 fc/28 fc/2 - fs 3 Divider DV21 DV11 DV6 DV1 - - TC2CK TC2 source clock select Unit : [Hz] 010 011 100 101 110 111 Reserved External clock (TC2 pin input) R/W TC2M TC2 operating mode select 0:Timer/event counter mode 1:Window mode Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: When writing to the Timer Register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper side (TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no effect. Note 3: The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written to the upper side (TC2DRH) after writing data to the lower side (TC2DRL). Note 4: Set the mode and source clock when the TC2 stops (TC2S = 0). Note 5: Values to be loaded to the timer register must satisfy the following condition. TC2DR > 1 (TC2DR15 to TC2DR11 > 1 at warm up) Note 6: If a read instruction is executed for TC2CR, read data of bit 7, 6 and 1 are unstable. Note 7: The high-frequency clock (fc) canbe selected only when the time mode at SLOW2 mode is selected. Note 8: On entering STOP mode, the TC2 start control (TC2S) is cleared to "0" automatically. So, the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC2S again. Page 94 TMP86FS49AFG 9.3 Function The timer/counter 2 has three operating modes: timer, event counter and window modes. And if fc or fs is selected as the source clock in timer mode, when switching the timer mode from SLOW1 to NORMAL2, the timer/counter2 can generate warm-up time until the oscillator is stable. 9.3.1 Timer mode In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the contents of up counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. When fc is selected for source clock at SLOW2 mode, lower 11-bits of TC2DR are ignored and generated a interrupt by matching upper 5-bits only. Though, in this situation, it is necessary to set TC2DRH only. Table 9-1 Source Clock (Internal clock) for Timer/Counter2 (at fc = 16 MHz, DV7CK=0) TC2C K NORMAL1/2, IDLE1/2 mode SLOW1/2 mode DV7CK = 0 DV7CK = 1 Maximum Time Setting 18.2 [h] 1.07 [min] - - - - Maximum Time Setting 18.2 [h] 1.07 [min] - - - - SLEEP1/2 mode Resolution Maximum Time Setting Resolution Maximum Time Setting Resolution Resolution 000 001 010 011 100 101 524.29 [ms] 512.0 [ms] 16.0 [ms] 0.5 [ms] - 30.52 [ms] 9.54 [h] 33.55 [s] 1.05 [s] 32.77 [ms] - 2 [s] 1 [s] 0.98 [ms] 16.0 [ms] 0.5 [ms] - 30.52 [ms] 18.2 [h] 1.07 [min] 1.05 [s] 32.77 [ms] - 2 [s] 1 [s] 0.98 [ms] - - 62.5 [ns] - 1 [s] 0.98 [ms] - - - - Note:When fc is selected as the source clock in timer mode, it is used at warm-up for switching from SLOW1 mode to NORMAL2 mode. Example :Sets the timer mode with source clock fc/23 [Hz] and generates an interrupt every 25 ms (at fc = 16 MHz ) LDW DI SET EI LD LD (TC2CR), 00001000B (TC2CR), 00101000B (EIRE). 6 (TC2DR), 061AH ; Sets TC2DR (25 ms 28/fc = 061AH) ; IMF= "0" ; Enables INTTC2 interrupt ; IMF= "1" ; Source clock / mode select ; Starts Timer Page 95 9. 16-Bit Timer/Counter2 (TC2) 9.3 Function TMP86FS49AFG Timer start Source clock Up-counter 0 1 2 3 4 Match detect n0 1 2 3 Counter clear TC2DR INTTC2 interrupt Figure 9-2 Timer Mode Timing Chart Page 96 TMP86FS49AFG 9.3.2 Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are compared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. Counting up is resumed every the rising edge of the TC2 pin input after the up counter is cleared. Match detect is executed on the falling edge of the TC2 pin. Therefore, an INTTC2 interrupt is generated at the falling edge after the match of TC2DR and up counter. The minimum input pulse width of TC2 pin is shown in Table 9-2. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Example :Sets the event counter mode and generates an INTTC2 interrupt 640 counts later. LDW DI SET EI LD LD (TC2CR), 00011100B (TC2CR), 00111100B (EIRE). 6 (TC2DR), 640 ; Sets TC2DR ; IMF= "0" ;Enables INTTC2 interrupt ; IMF= "1" ; TC2 source vclock / mode select ; Starts TC2 Table 9-2 Timer/Counter 2 External Input Clock Pulse Width Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 mode "H" width "L" width 23/fc 23/fc SLOW1/2, SLEEP1/2 mode 23/fs 23/fs Timer start TC2 pin input Counter 0 1 2 3 n 0 1 2 3 Match detect Counter clear TC2DR n INTTC2 interrupt Figure 9-3 Event Counter Mode Timing Chart 9.3.3 Window mode In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input (Window pulse) is "H" level. The contents of TC2DR are compared with the contents of up counter. If a match found, an INTTC2 interrupt is generated, and the up-counter is cleared. The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock by the TC2CR Note:It is not available window mode in the SLOW/SLEEP mode. Therefore, at the window mode in NORMAL mode, the timer should be halted by setting TC2CR Page 97 9. 16-Bit Timer/Counter2 (TC2) 9.3 Function TMP86FS49AFG Example :Generates an interrupt, inputting "H" level pulse width of 120 ms or more. (at fc = 16 MHz, TBTCR LDW DI SET EI LD LD (TC2CR), 00000101B (TC2CR), 00100101B (EIRE). 6 (TC2DR), 00EAH ; Sets TC2DR (120 ms 213/fc = 00EAH) ; IMF= "0" ; Enables INTTC2 interrupt ; IMF= "1" ; TC2sorce clock / mode select ; Starts TC2 Timer start TC2 pin input Internal clock Counter TC2DR Match detect INTTC2 interrupt 1 2 n 0 1 2 3 Counter clear Figure 9-4 Window Mode Timing Chart Page 98 TMP86FS49AFG 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC4 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TC4 pin TC4M TC4S TFF4 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC4S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F4 PDO4/PWM4/ PPG4 pin TC4CK TC4CR TTREG4 PWREG4 PWM, PPG mode DecodeEN TFF4 PDO, PWM, PPG mode 16-bit mode TC3S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TC3 pin TC3M TC3S TFF3 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC3 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F3 PDO3/PWM3/ pin TC3CK TC3CR TTREG3 PWREG3 PWM mode DecodeEN TFF3 PDO, PWM mode 16-bit mode Figure 10-1 8-Bit TimerCounter 3, 4 Page 99 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration TMP86FS49AFG 10.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (0014H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG3 (0018H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG3) setting while the timer is running. Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 3 Control Register TC3CR (0027H) 7 TFF3 6 5 TC3CK 4 3 TC3S 2 1 TC3M 0 (Initial value: 0000 0000) TFF3 Time F/F3 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC3CK Operating clock selection [Hz] 010 011 100 101 110 111 TC3S TC3 start control 0: 1: 000: 001: TC3M TC3M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC4M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running. Note 3: To stop the timer operation (TC3S= 1 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer operation (TC3S= 0 1), TC3M, TC3CK and TFF3 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR Page 100 TMP86FS49AFG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 103. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 101 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration TMP86FS49AFG The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (0015H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG4 (0019H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running. Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 4 Control Register TC4CR (0028H) 7 TFF4 6 5 TC4CK 4 3 TC4S 2 1 TC4M 0 (Initial value: 0000 0000) TFF4 Timer F/F4 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC4 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC4CK Operating clock selection [Hz] 010 011 100 101 110 111 TC4S TC4 start control 0: 1: 000: 001: 010: TC4M TC4M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running. Note 3: To stop the timer operation (TC4S= 1 0), do not change the TC4M, TC4CK and TFF4 settings. To start the timer operation (TC4S= 0 1), TC4M, TC4CK and TFF4 can be programmed. Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC3 overflow signal regardless of the TC4CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR Page 102 TMP86FS49AFG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR Table 10-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note 2: : Available source clock Table 10-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note2: : Available source clock Page 103 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration TMP86FS49AFG Table 10-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG4, 3) 65535 256 (TTREG4, 3) 65535 2 (PWREG4, 3) 65534 1 (PWREG4, 3) < (TTREG4, 3) 65535 16-bit PPG and (PWREG4, 3) + 1 < (TTREG4, 3) Register Value Note: n = 3 to 4 Page 104 TMP86FS49AFG 10.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 10.3.1 8-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 10-4 Source Clock for TimerCounter 3, 4 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Maximum Time Setting fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter4, fc = 16.0 MHz) LD DI SET EI LD LD (TC4CR), 00010000B (TC4CR), 00011000B : Sets the operating clock to fc/27, and 8-bit timer mode. : Starts TC4. (EIRH). 1 : Enables INTTC4 interrupt. (TTREG4), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 105 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration TMP86FS49AFG TC4CR Internal Source Clock Counter TTREG4 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 10-2 8-Bit Timer Mode Timing Chart (TC4) 10.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC4CR Counter TTREG4 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 10-3 8-Bit Event Counter Mode Timing Chart (TC4) 10.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 106 TMP86FS49AFG Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD LD LD (TTREG4), 3DH (TC4CR), 00010001B (TC4CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC4. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 107 10.1 Configuration 10. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Figure 10-4 8-Bit PDO Mode Timing Chart (TC4) Match detect Match detect Match detect Page 108 Counter 0 1 2 TTREG4 ? n Match detect Timer F/F4 Set F/F PDO4 pin INTTC4 interrupt request Held at the level when the timer is stopped TMP86FS49AFG TMP86FS49AFG 10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 10-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 109 10.1 Configuration 10. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock n Write to PWREG4 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG4 PWREG4 ? Shift Shift m Match detect n m p Shift p Match detect Match detect Figure 10-5 8-Bit PWM Mode Timing Chart (TC4) Page 110 n One cycle period m Shift Shift registar ? n Match detect Timer F/F4 PWM4 pin n p INTTC4 interrupt request TMP86FS49AFG TMP86FS49AFG 10.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the timer mode, fix TCjCR Table 10-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Maximum Time Setting fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC3CR), 13H :Sets the operating clock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRH). 1 : Enables INTTC4 interrupt. (TTREG3), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC4CR), 04H (TC4CR), 0CH TC4CR Internal source clock Counter TTREG3 (Lower byte) TTREG4 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 10-6 16-Bit Timer Mode Timing Chart (TC3 and TC4) Page 111 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration TMP86FS49AFG 10.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR 4 Note 1: In the event counter mode, fix TCjCR 10.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 112 TMP86FS49AFG CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the PWM4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4 pin during the warm-up period time after exiting the STOP mode. Table 10-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2s 8.2 ms 4.1 ms fs = 32.768 kHz 16 s - - - 2s - - Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG3), 07D0H (TC3CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC4CR), 056H (TC4CR), 05EH Page 113 10.1 Configuration 10. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock an Write to PWREG3 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG3 FFFF 0 1 cp PWREG3 (Lower byte) ? Write to PWREG4 n m p Write to PWREG4 Figure 10-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 114 b Shift Shift bm Match detect an One cycle period bm PWREG4 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F4 PWM4 pin an cp INTTC4 interrupt request TMP86FS49AFG TMP86FS49AFG 10.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/ 2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG3), 07D0H (TTREG3), 8002H (TC3CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC4CR), 057H (TC4CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 115 10.1 Configuration 10. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG3 (Lower byte) ? n Figure 10-8 16-Bit PPG Mode Timing Chart (TC3 and TC4) Page 116 Match detect Match detect Match detect mn mn PWREG4 (Upper byte) ? m Match detect Match detect TTREG3 (Lower byte) ? r TTREG4 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F4 PPG4 pin INTTC4 interrupt request TMP86FS49AFG TMP86FS49AFG 10.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCounter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 10.3.9.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Minimum Time Setting (TTREG4, 3 = 0100H) 7.81 ms Maximum Time Setting (TTREG4, 3 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC4: CLR SET (TC4CR).3 : (TC4CR).3 (SYSCR2).5 : Stops TC4 and 3. : SYSCR2 CLR RETI : VINTTC4: DW (SYSCR2).7 : PINTTC4 : INTTC4 vector table Page 117 10. 8-Bit TimerCounter (TC3, TC4) 10.1 Configuration TMP86FS49AFG 10.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Minimum time Setting (TTREG4, 3 = 0100H) 16 s Maximum time Setting (TTREG4, 3 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC3CR), 63H (TC4CR), 05H (TTREG3), 0F800H : SYSCR2 DI SET EI SET : PINTTC4: CLR CLR CLR (SYSCR2).6 RETI : VINTTC4: DW : PINTTC4 : INTTC4 vector table Page 118 TMP86FS49AFG 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC6 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TC6 pin TC6M TC6S TFF6 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC6S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F6 PDO6/PWM6/ PPG6 pin TC6CK TC6CR TTREG6 PWREG6 PWM, PPG mode DecodeEN TFF6 PDO, PWM, PPG mode 16-bit mode TC5S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TC5 pin TC5M TC5S TFF5 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC5 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F5 PDO5/PWM5/ pin TC5CK TC5CR TTREG5 PWREG5 PWM mode DecodeEN TFF5 PDO, PWM mode 16-bit mode Figure 11-1 8-Bit TimerCounter 5, 6 Page 119 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration TMP86FS49AFG 11.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers (TTREG5, PWREG5). TimerCounter 5 Timer Register TTREG5 (0016H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG5 (001AH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG5) setting while the timer is running. Note 2: Do not change the timer register (PWREG5) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 5 Control Register TC5CR (0029H) 7 TFF5 6 5 TC5CK 4 3 TC5S 2 1 TC5M 0 (Initial value: 0000 0000) TFF5 Time F/F5 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC5 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC5CK Operating clock selection [Hz] 010 011 100 101 110 111 TC5S TC5 start control 0: 1: 000: 001: TC5M TC5M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC6M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC5M, TC5CK and TFF5 settings while the timer is running. Note 3: To stop the timer operation (TC5S= 1 0), do not change the TC5M, TC5CK and TFF5 settings. To start the timer operation (TC5S= 0 1), TC5M, TC5CK and TFF5 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC6CR Page 120 TMP86FS49AFG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 113. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 121 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration TMP86FS49AFG The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers (TTREG6 and PWREG6). TimerCounter 6 Timer Register TTREG6 (0017H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG6 (001BH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG6) setting while the timer is running. Note 2: Do not change the timer register (PWREG6) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 6 Control Register TC6CR (002AH) 7 TFF6 6 5 TC6CK 4 3 TC6S 2 1 TC6M 0 (Initial value: 0000 0000) TFF6 Timer F/F6 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC6 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC6CK Operating clock selection [Hz] 010 011 100 101 110 111 TC6S TC6 start control 0: 1: 000: 001: 010: TC6M TC6M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC6M, TC6CK and TFF6 settings while the timer is running. Note 3: To stop the timer operation (TC6S= 1 0), do not change the TC6M, TC6CK and TFF6 settings. To start the timer operation (TC6S= 0 1), TC6M, TC6CK and TFF6 can be programmed. Note 4: When TC6M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC5 overflow signal regardless of the TC6CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC6M, where TC5CR Page 122 TMP86FS49AFG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR Table 11-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC5 pin input - - - - - TC6 pin input - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC5CK). Note 2: : Available source clock Table 11-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC5 pin input - - - - - TC6 pin input - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC5CK). Note2: : Available source clock Page 123 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration TMP86FS49AFG Table 11-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG6, 5) 65535 256 (TTREG6, 5) 65535 2 (PWREG6, 5) 65534 1 (PWREG6, 5) < (TTREG6, 5) 65535 16-bit PPG and (PWREG6, 5) + 1 < (TTREG6, 5) Register Value Note: n = 5 to 6 Page 124 TMP86FS49AFG 11.3 Function The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 11.3.1 8-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 11-4 Source Clock for TimerCounter 5, 6 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Maximum Time Setting fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter6, fc = 16.0 MHz) LD DI SET EI LD LD (TC6CR), 00010000B (TC6CR), 00011000B : Sets the operating clock to fc/27, and 8-bit timer mode. : Starts TC6. (EIRE). 2 : Enables INTTC6 interrupt. (TTREG6), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 125 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration TMP86FS49AFG TC6CR Internal Source Clock Counter TTREG6 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 11-2 8-Bit Timer Mode Timing Chart (TC6) 11.3.2 8-Bit Event Counter Mode (TC5, 6) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC6CR Counter TTREG6 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 11-3 8-Bit Event Counter Mode Timing Chart (TC6) 11.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 126 TMP86FS49AFG Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz) Setting port LD LD LD (TTREG6), 3DH (TC6CR), 00010001B (TC6CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC6. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 127 11.1 Configuration 11. 8-Bit TimerCounter (TC5, TC6) TC6CR TC6CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Figure 11-4 8-Bit PDO Mode Timing Chart (TC6) Match detect Match detect Match detect Page 128 Counter 0 1 2 TTREG6 ? n Match detect Timer F/F6 Set F/F PDO6 pin INTTC6 interrupt request Held at the level when the timer is stopped TMP86FS49AFG TMP86FS49AFG 11.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 11-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 129 11.1 Configuration 11. 8-Bit TimerCounter (TC5, TC6) TC6CR TC6CR Internal source clock n Write to PWREG6 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG6 PWREG6 ? Shift Shift m Match detect n m p Shift p Match detect Match detect Figure 11-5 8-Bit PWM Mode Timing Chart (TC6) Page 130 n One cycle period m Shift Shift registar ? n Match detect Timer F/F6 PWM6 pin n p INTTC6 interrupt request TMP86FS49AFG TMP86FS49AFG 11.3.5 16-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR Note 1: In the timer mode, fix TCjCR Table 11-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Maximum Time Setting fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC5CR), 13H :Sets the operating clock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRE). 2 : Enables INTTC6 interrupt. (TTREG5), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC6CR), 04H (TC6CR), 0CH TC6CR Internal source clock Counter TTREG5 (Lower byte) TTREG6 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 11-6 16-Bit Timer Mode Timing Chart (TC5 and TC6) Page 131 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration TMP86FS49AFG 11.3.6 16-Bit Event Counter Mode (TC5 and 6) In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5 and 6 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR 4 Note 1: In the event counter mode, fix TCjCR 11.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC6 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F6 by TC6CR Note 1: In the PWM mode, program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt request is generated (normally in the INTTC6 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC6 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM6 pin holds the output status when the timer is stopped. To change the output status, program TC6CR Page 132 TMP86FS49AFG CLR (TC6CR).3: Stops the timer. CLR (TC6CR).7 : Sets the PWM6 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM6 pin during the warm-up period time after exiting the STOP mode. Table 11-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2s 8.2 ms 4.1 ms fs = 32.768 kHz 16 s - - - 2s - - Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG5), 07D0H (TC5CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF6 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC6CR), 056H (TC6CR), 05EH Page 133 11.1 Configuration 11. 8-Bit TimerCounter (TC5, TC6) TC6CR TC6CR Internal source clock an Write to PWREG5 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG5 FFFF 0 1 cp PWREG5 (Lower byte) ? Write to PWREG6 n m p Write to PWREG6 Figure 11-7 16-Bit PWM Mode Timing Chart (TC5 and TC6) Page 134 b Shift Shift bm Match detect an One cycle period bm PWREG6 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F6 PWM6 pin an cp INTTC6 interrupt request TMP86FS49AFG TMP86FS49AFG 11.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F6 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected, and the counter is cleared. The INTTC6 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 to in the SLOW1/ 2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F6 by TC6CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG5), 07D0H (TTREG5), 8002H (TC5CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF6 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC6CR), 057H (TC6CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG6 pin holds the output status when the timer is stopped. To change the output status, program TC6CR Page 135 11.1 Configuration 11. 8-Bit TimerCounter (TC5, TC6) TC6CR TC6CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG5 (Lower byte) ? n Figure 11-8 16-Bit PPG Mode Timing Chart (TC5 and TC6) Page 136 Match detect Match detect Match detect mn mn PWREG6 (Upper byte) ? m Match detect Match detect TTREG5 (Lower byte) ? r TTREG6 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F6 PPG6 pin INTTC6 interrupt request TMP86FS49AFG TMP86FS49AFG 11.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a 16-bit TimerCounter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 11.3.9.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Minimum Time Setting (TTREG6, 5 = 0100H) 7.81 ms Maximum Time Setting (TTREG6, 5 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC6 and 5, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC6: CLR SET (TC6CR).3 : (TC6CR).3 (SYSCR2).5 : Stops TC6 and 5. : SYSCR2 CLR RETI : VINTTC6: DW (SYSCR2).7 : PINTTC6 : INTTC6 vector table Page 137 11. 8-Bit TimerCounter (TC5, TC6) 11.1 Configuration TMP86FS49AFG 11.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Minimum time Setting (TTREG6, 5 = 0100H) 16 s Maximum time Setting (TTREG6, 5 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC6 and 5, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC5CR), 63H (TC6CR), 05H (TTREG5), 0F800H : SYSCR2 DI SET EI SET : PINTTC6: CLR CLR CLR (SYSCR2).6 RETI : VINTTC6: DW : PINTTC6 : INTTC6 vector table Page 138 TMP86FS49AFG 12. Asynchronous Serial interface (UART1 ) 12.1 Configuration UART control register 1 UART1CR1 Transmit data buffer TD1BUF Receive data buffer RD1BUF 3 2 Receive control circuit 2 Transmit control circuit Shift register Shift register Parity bit Stop bit Noise rejection circuit RXD1 INTTXD1 INTRXD1 TXD1 Transmit/receive clock Y M P X S 2 Y Counter UART1SR S fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC3 A B C fc/2 fc/27 8 fc/2 6 fc/96 A B C D E F G H 4 2 UART1CR2 UART status register Baud rate generator UART control register 2 MPX: Multiplexer Figure 12-1 UART1 (Asynchronous Serial Interface) Page 139 12. Asynchronous Serial interface (UART1 ) 12.2 Control TMP86FS49AFG 12.2 Control UART1 is controlled by the UART1 Control Registers (UART1CR1, UART1CR2). The operating status can be monitored using the UART status register (UART1SR). UART1 Control Register1 UART1CR1 (0F95H) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 0 (Initial value: 0000 0000) TXE RXE STBT EVEN PE Transfer operation Receive operation Transmit stop bit length Even-numbered parity Parity addition 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 000: 001: 010: 011: 100: 101: 110: 111: Disable Enable Disable Enable 1 bit 2 bits Odd-numbered parity Even-numbered parity No parity Parity fc/13 [Hz] fc/26 fc/52 fc/104 fc/208 fc/416 TC3 ( Input INTTC3) fc/96 Write only BRG Transmit clock select Note 1: When operations are disabled by setting TXE and RXE bit to "0", the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. Note 2: The transmit clock and the parity are common to transmit and receive. Note 3: UART1CR1 UART1 Control Register2 UART1CR2 (0F96H) 7 6 5 4 3 2 RXDNC 1 0 STOPBR (Initial value: **** *000) RXDNC Selection of RXD input noise rejection time 00: 01: 10: 11: 0: 1: No noise rejection (Hysteresis input) Rejects pulses shorter than 31/fc [s] as noise Rejects pulses shorter than 63/fc [s] as noise Rejects pulses shorter than 127/fc [s] as noise 1 bit 2 bits Write only STOPBR Receive stop bit length Note: When UART1CR2 Page 140 TMP86FS49AFG UART1 Status Register UART1SR (0F95H) 7 PERR 6 FERR 5 OERR 4 RBFL 3 TEND 2 TBEP 1 0 (Initial value: 0000 11**) PERR FERR OERR RBFL TEND TBEP Parity error flag Framing error flag Overrun error flag Receive data buffer full flag Transmit end flag Transmit data buffer empty flag 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: No parity error Parity error No framing error Framing error No overrun error Overrun error Receive data buffer empty Receive data buffer full On transmitting Transmit end Transmit data buffer full (Transmit data writing is finished) Transmit data buffer empty Read only Note: When an INTTXD is generated, TBEP flag is set to "1" automatically. UART1 Receive Data Buffer RD1BUF (0F97H) 7 6 5 4 3 2 1 0 Read only (Initial value: 0000 0000) UART1 Transmit Data Buffer TD1BUF (0F97H) 7 6 5 4 3 2 1 0 Write only (Initial value: 0000 0000) Page 141 12. Asynchronous Serial interface (UART1 ) 12.3 Transfer Data Format TMP86FS49AFG 12.3 Transfer Data Format In UART1, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART1CR1 PE STBT 1 Start 2 Bit 0 3 Bit 1 Frame Length 8 Bit 6 9 Bit 7 10 Stop 1 11 12 0 0 1 1 0 1 0 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2 Figure 12-2 Transfer Data Format Without parity / 1 STOP bit With parity / 1 STOP bit Without parity / 2 STOP bit With parity / 2 STOP bit Figure 12-3 Caution on Changing Transfer Data Format Note: In order to switch the transfer data format, perform transmit operations in the above Figure 12-3 sequence except for the initial setting. Page 142 TMP86FS49AFG 12.4 Transfer Rate The baud rate of UART1 is set of UART1CR1 |