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| DI2CS I2C Bus Interface - Slave ver 3.02 OVERVIEW I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CS core provides an interface between a microprocessor /microcontroller and an I2C bus. It can works as a slave transmitter or slave receiver depending on working mode determined by a master device. The DI2CS core incorporates all features required by the latest I2C specification including clock synchronization, arbitration and High-speed transmission mode. The DI2CS supports all the transmission speed modes. Fully synthesizable Static synchronous design with positive edge clocking and synchronous reset No internal tri-states Scan test ready APPLICATIONS Embedded microprocessor boards Consumer and professional audio/video Home and automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems KEY FEATURES Conforms to v.2.1 of the I2C specification Slave operation Slave transmitter Slave receiver DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support http://www.DigitalCoreDesign.com http://www.dcd.pl Supports 3 transmission speed modes Standard (up to 100 kb/s) Fast (up to 400 kb/s) High Speed (up to 3,4 Mb/s) Allows operation from a wide range of input clock frequencies Simple interface allows easy connection to microprocessor/microcontroller devices Interrupt generation User-defined data setup time All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. IP Core implementation support 3 months maintenance SYMBOL datai(7:0) datao(7:0) address(1:0) cs rd we irq Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. clk rst address(1:0) cs we rd scli sdai datai(7:0) datao(7:0) sclo sdao irq scli sdai rst clk sclo sdao PINS DESCRIPTION PIN TYPE input input input input input input input input input output output output output DESCRIPTION Global clock Global reset Processor address lines Chip select Processor write strobe Processor read strobe I2C bus clock line (input) I2C bus data line (input) Processor data bus (input) Processor data bus (output) I2C bus clock line (output) I2C bus data line (output) Processor interrupt line Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM Figure below shows the DI2CS IP Core block diagram. datai(7:0) datao(7:0) address(1:0) cs we rd irq IMPLEMENTATION Figure below show the typical DI2CS implementations in system with Standard/Fast and High-speed devices. sdai Receive Data Shift Register Send Data Own address detection Control Register Status Register Input Filter Output Register VDD sdao CPU Interface RP SDA SCL RP Control Logic sdai RS RS RS RS sda Synchronization Logic rst clk Input Filter Output Register scli sclo sdao open drain Clock Stretching DI2CS Master device CPU Interface - Performs the interface functions between DI2CS internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system. Control Logic - Manages execution of all commands sent via interface. Synchronizes internal data flow. Shift Register - Controls SDA line, performs data and address shifts during the data transmission and reception. Control Register - Contains five control bits used for performing all types of I2C Bus transmissions. Status Register - Contains seven status bits that indicates state of the I2C Bus and the DI2CS core. Input Filter - Performs spike filtering. Synchronization Logic - Performs DI2CS core synchronization. Clock Stretching - Performs I2C SCL clock stretching when DI2CS core is not ready for next transmission. scli sclo open drain scl PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA(R) devices after Place & Route (all key features have been included): Speed Logic Cells Fmax grade MERCURY -5 170 250 MHz STRATIX -5 170 260 MHz CYCLONE -6 170 220 MHz APEX II -7 170 270 MHz APEX20KC -7 170 150 MHz APEX20KE -1 170 120 MHz APEX20K -1 170 90 MHz ACEX1K -1 170 107 MHz FLEX10KE -1 170 107 MHz MAX 7000AE -5 83 96 MHz MAX 3000A -5 83 104 MHz Core performance in ALTERA(R) devices Device All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. The main features of each Digital Core Design I2C compliant cores have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. High-speed mode 10-bit addressing Master operation I2C specification version 7-bit addressing Clock synchronization Slave operation Standard mode Passive device interface CPU interface DI2CM DI2CS DI2CSB 3.0 2.1 2.1 - - Arbitration Design - - - I2C cores summary table CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND nfo@dcd.pl e-mail: iinfo@dcd.pl tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Spike filtering User defined timing Fast mode Interrupt generation |
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