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October 2007
HYS72T512420EFA-[25F/3S]-C
240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products
Internet Data Sheet
Rev.1.20
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HYS72T512420EFA-[25F/3S]-C Fully-Buffered DDR2 SDRAM Modules
Revision History: Rev.1.20, 2007-10-19 Page 5 Page 20 Page 20 Page 65 Page 5 Page 20 Changed Table 4 "Components on Modules" on Page 5 Changed Table 5.1 "ICC/IDD Conditions" on Page 20 Changed Table 14 "ICC/IDD Specification for PC2-6400F" on Page 20 Changed Table 21 "ICC/IDD Specification for PC2-5300F" on Page 65 Changed Table 2 "Ordering Information for RoHS Compliant Products" on Page 5. Updated Table 5.1 "ICC/IDD Conditions" on Page 20
Previous Revision: Rev. 1.10, 2007-08-22
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev411 / 3.31 QAG / 2007-01-22 03202007-06NE-DYYI
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1
1.1
Overview
Features
* Detects errors on the channel and reports them to the host memory controller. * Automatic DDR2 DRAM Bus Calibration. * Automatic Channel Calibration. * Full Host Control of the DDR2 DRAMs. * Over-Temperature Detection and Alert. * Hot Add-on and Hot Remove Capability. * MBIST and IBIST Test Functions. * Transparent Mode for DRAM Test Support. * Low profile: 133.35mm x 30.35 mm * 240 Pin gold plated card connector with 1.00mm contact centers (JEDEC standard pending). * Based on JEDEC standard reference card designs (Jedec standard pending). * SPD (Serial Presence Detect) with 256 Byte serial E2PROM.Performance: * RoHS Compliant Products1)
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
* 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications. * two rank 512M x 72 module organization, and 256M x 4, 128M x 4 chip organization * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * 4GB Modules built with chipsize packages PG-TFBGA-60 * Re-drive and re-sync of all address, command, clock and data signals using AMB (Advanced Memory Buffer). * High-Speed Differential Point-to-Point Link Interface at 1.5 V (Jedec standard pending). * Host Interface and AMB component industry standard compliant. * Supports SMBus protocol interface for access to the AMB configuration registers.
TABLE 1
Performance Table
QAG Speed Code DRAM Speed Grade Module Speed Grade CAS-RCD-RP latencies Max. Clock Frequency CL3 CL5 CL4 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -25F DDR2-800D PC2-6400D 5-5-5 -3S DDR2-667D PC2-5300D 5-5-5 200 333 266 15 15 45 60 MHz MHz MHz ns ns ns ns Unit
fCK3 fCK5 fCK4 tRCD tRP tRAS tRC
200 400 266 12.5 12.5 45 57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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1.2
Description
controller and / or the adjacent DIMMs on a system board using an Industry Standard High-Speed Differential Point-toPoint Link Interface at 1.5 V. The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The Advanced Memory Buffer interface is responsible for handling channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the memory channel. Fully Buffered DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. The maximum memory capacity is 288 DDR2 SDRAM devices per channel or 8 DIMMs.
This document describes the electrical and mechanical features of a 240-pin,PC2-5300F, ECC type, Fully Buffered Double-Data-Rate Two Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered DIMMs use commodity DRAMs isolated from the memory channel behind a buffer on the DIMM. They are intended for use as main memory when installed in systems such as servers and workstations. PC2-5300F, refers to the DIMM naming convention indicating the DDR2 SDRAMs running at 333, MHz clock speed and offering 5300, MB/s peak bandwidth. FB-DIMM features a novel architecture including the Advanced Memory Buffer. This single chip component, located in the center of each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the DDR2 SDRAMs including data in- and output. The AMB communicates with the host
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TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1) PC2-6400 HYS72T512420EFA-25F-C PC2-5300 HYS72T512420EFA-3S-C 4GB 2Rx4 PC2-5300F-555-11-ZZ 2 Ranks, ECC 1Gbit (x4)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-6400F-555-11-H0" where 6400F means Fully-Buffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555-11" means Column Address Strobe (CAS) latency =5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card "H".
Compliance Code2) 4GB 2Rx4 PC2-6400F-555-11-ZZ
Description 2 Ranks, ECC
SDRAM Technology 1Gbit (x4)
TABLE 3
Address Format
DIMM Density 4GB Module Organization 512M x 72 Memory Ranks 2 ECC/ Non-ECC ECC # of SDRAMs # of row/bank/column bits 36 14/3/11 Raw Card Z
TABLE 4
Components on Modules
Product Type1)2) HYS72T512420EFA DRAM Components1) HYB18T1G400CF DRAM Density 1Gbit DRAM Organisation 256M x 4
1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
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2
Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
TABLE 5
Pin Configuration of FB-DIMM
Pin# Nam e SCK SCK RES ET PN0 PN1 PN2 PN3 PN4 PN5 PN6 PN7 PN8 PN9 Pin Type I I I Buffer Type HSDL_15 HSDL_15 LV-CMOS Function
Clock Signals 228 229 17 Northbound 22 25 28 31 34 37 51 54 57 60 63 66 48 40 23 26 29 32 35 38 52 55 58 61 64 O O O O O O O O O O HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 Primary Northbound Data, positive lines System Clock Input, positive line System Clock Input, negative line AMB reset signal
Control Signals
PN10 O PN11 O PN12 O PN13 O PN0 PN1 PN2 PN3 PN4 PN5 PN6 PN7 PN8 PN9 O O O O O O O O O O
PN10 O
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Pin# 67 49 41 142 145 148 151 154 157 171 174 177 180 183 186 168 160 143 146 149 152 155 158 172 175 178 181 184 187 169 161 Southbound 70 73 76 79 82 93 96 99
Nam e
Pin Type
Buffer Type HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15
Function
PN11 O PN12 O PN13 O SN0 SN1 SN2 SN3 SN4 SN5 SN6 SN7 SN8 SN9 I I I I I I I I I I
Secondary Northbound Data, positive lines
SN10 I SN11 I SN12 I SN13 I SN0 SN1 SN2 SN3 SN4 SN5 SN6 SN7 SN8 SN9 I I I I I I I I I I
SN10 I SN11 I SN12 I SN13 I PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 I I I I I I I I
Primary Southbound Data, positive lines
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Pin# 102 90 71 74 77 80 83 94 97 100 103 91 190 193 196 199 202 213 216 219 222 210 191 194 197 200 203 214 217 220 223 211 EEPROM 120 119 239 240 118 Power Supplies
Nam e PS8 PS9 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 SS0 SS1 SS2 SS3 SS4 SS5 SS6 SS7 SS8 SS9 SS0 SS1 SS2 SS3 SS4 SS5 SS6 SS7 SS8 SS9 SCL SDA SA0 SA1 SA2
Pin Type I I I I I I I I I I I I O O O O O O O O O O O O O O O O O O O O I I/O I I I
Buffer Type HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 HSDL_15 CMOS OD CMOS CMOS CMOS
Function
Primary Southbound Data, negative lines
Secondary Southbound data, positive lines
Secondary Southbound data, negative lines
Serial Bus Clock Serial Bus Data Serial Address Select Bus 2:0
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Pin# 238
Nam e
Pin Type
Buffer Type - -
Function EEPROM Power Supply AMB Core Power / Channel Interface Power
VDDSP PWR
D
9,10,12,13,1 VCC 29,130,132, 133 15,117,135, 237 VTT
PWR
PWR PWR
- -
Address/Command/Clock Termination Power Power Supply
1,2,3,5,6,7,1 VDD 08,109,111, 112,113,115 ,116,121,12 2,123,125,1 26, 127,231,232 ,233,235,23 6 4,8,11,14,18 VSS ,21,24,27,30 ,33,36, 39,42,43,46, 47,50,53,56, 59,62, 65,68,69,72, 75,78,81,84, 85,88, 89,92,95,98, 101,104,107 ,110, 114,124,128 ,131,134,13 8,141, 144,147,150 ,153,156,15 9,162, 163,166,167 ,170,173,17 6,179, 182,185,188 ,189,192,19 5,198, 201,204,205 ,208,209,21 2,215, 218,221,224 ,227,230,23 4 Other Pins
GND
-
Ground Plane
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Pin#
Nam e
Pin Type NC
Buffer Type -
Function Not connected Pins not connected on Infineon FB-DIMM's. Pin positions are reserved for future architecture flexibility.
19,20,44,45, RFU 86,87,105,1 06,139, 140,164,165 ,206,207,22 5,226 136 16 VID0 VID1
- -
- -
Voltage ID Note: These Pins must be unconnected for DDR2-based Fully Buffered DIMMs VID[0] is VDD value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is VCC value: OPEN = 1.5 V, GND = 1.2 V VREF Note: Pin must be unconnected for normal operation
137
Test
AI
-
TABLE 6
Abbreviations for Buffer Type
Abbreviation HSDL_15 LV-CMOS CMOS OD Description High-Speed Differential Point-to-Point Link Interface at 1.5 V Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NU NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable Not Connected
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FIGURE 1
Pin Configuration for FB-DIMM (240 pin)
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3
3.1
Basic Functionality
Advanced Memory Buffer Overview
This chapter describes the basic functionality.
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification.
3.2
Advanced Memory Buffer Functionality
* Detects errors on the channel and reports them to the host memory controller. * Support the FB-DIMM configuration register set as defined in the register chapters. * Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM. * Provides a read buffer FIFO and a write buffer FIFO. * Supports an SMBus protocol interface for access to the AMB configuration registers. * Provides logic to support MEMBIST and IBIST Design for Test functions. * Provides a register interface for the thermal sensor and status indicator. * Functions as a repeater to extend the maximum length of FB-DIMM Links.
The Advanced Memory Buffer will perform the following FBDIMM channel functions: * Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB DIMM position. * Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames. * If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames.
Transparent Mode for DRAM Test Support In this mode, the Advanced Memory Buffer will provide lower speed tester access to DRAM pins through the FB-DIMM I/O pins. This allows the tester to send an arbitrary test pattern to the DRAMs. Transparent mode only supports a maximum DRAM frequency equivalent to DDR2 400. Transparent mode functionality: * Reconfigures FB-DIMM inputs from differential high speed link receivers to two single ended lower speed receivers (~200 MHz) * These inputs directly control DDR2 Command/Address and input data that is replicated to all DRAMs * Uses low speed direct drive FB-DIMM outputs to bypass high speed Parallel/Serial circuitry and provide test results back to tester
DDR2 SDRAM Interface * Supports DDR2 at speeds of 667, 800 MT/s * Supports 256Mb, 512Mb and 1Gb devices in x4 and x8 configurations * 72-bit DDR2 SDRAM memory array
3.3
Interfaces
controller or an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM.
Figure 2 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FB-DIMM links, one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the Advanced Memory Buffer to a host memory
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FIGURE 2
Block Diagram Advanced Memory Buffer Interface
Interface Topology The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives the data to the next DIMM until the host is reached.
FIGURE 3
Block Diagram of Channel Southbound and Northbound Paths
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3.4
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces
read return data or status information that is generated internally. Data and commands sent to the DRAMs travel southbound on 10 primary differential signal line pairs. Data received from the DRAMs and status information travel northbound on 14 primary differential pairs. Data and commands sent to the adjacent DIMM upstream are repeated and travel further southbound on 10 secondary differential pairs. Data and status information received from the adjacent DIMM upstream travel further northbound on 14 secondary differential pairs.
The Advanced Memory Buffer supports one FB-DIMM Channel consisting of two bidirectional link interfaces using highspeed differential point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards this same data to the next FB-DIMM. The northbound input link is 14 lanes wide and carries read return data or status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards this information back towards the host and multiplexes in any
3.4.1
DDR2 Channel
Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The Advanced Memory Buffer provides four copies of the command clock phase references (CLK[3:0]) and write data/check-bit strobes (DQSs) for each DRAM nibble.
The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data, and eight check-bit signals. There are two copies of address and command signals to support DIMM routing and electrical requirements. Four transfer bursts are driven on the data and check-bit lines at 800 MHz.
3.4.2
SMBus Slave Interface
to set link strength, frequency and other parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the unique ID.
The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration registers independent of the FB-DIMM link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100 kHz. SMBus access to the Advanced Memory Buffer may be a requirement to boot and
3.4.3
Channel Latency
channel. Because the channel is based on the point-to-point interconnection of buffer components between DIMMs, memory requests are required to travel through N-1 buffers before reaching the Nth buffer. The result is that a 4 DIMM channel configuration will have greater idle read latency compared to a 1 DIMM channel configuration. The Variable Read Latency capability can be used to reduce latency for DIMMs closer to the host. The idle latencies listed in this section are representative of what might be achieved in typical AMB designs. Actual implementations with latencies less than the values listed will have higher application performance and vice versa.
FB-DIMM channel latency is measured from the time a read request is driven on the FB-DIMM channel pins to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by the memory controller. When not using the Variable Read Latency capability, the latency for a specific DIMM on a channel is always equal to the latency for any other DIMM on that channel. However, the latency for each DIMM in a specific configuration with some number of DIMMs installed may not be equal to the latency for each FB-DIMM in a configuration with some different number of DIMMs installed. As more DIMMs are added to the channel, additional latency is required to read from each DIMM on the
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3.4.4
Peak Theoretical Channel Throughput
from a single channel, or a burst of 4 from two lock-step channels provides a total of 72 bytes of data (64 bytes plus 8 bytes ECC). When the frame rate matches the DRAM command clock, the Southbound command and data connection will exhibit one half the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Southbound command and data connection is 2.133 GB/sec. The total peak theoretical throughput for a single FBDIMM channel is defined as the sum of the peak theoretical throughput of the Northbound data connection and the Southbound command and data connection. When the frame rate matches the DRAM command clock, this is equal to 1.5 times the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical throughput of a single DDR2-533 channel would be 4.267 GB/sec., while the peak theoretical throughput of the entire FB-DIMM PC4200F channel would be 6.4GB/sec.
An FB-DIMM channel transfers read completion data on the Northbound data connection. 144 bits of data are transferred for every Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 from a single channel or a DRAM burst of four from two lock stepped channels provides a total of 72 bytes of data (64 bytes plus 8 bytes ECC). The FB-DIMM frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FB-DIMM channel clock to the DRAM command clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput as a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data connection is 4.267 GB/sec. Write data is transferred on the Southbound command and data connection, via Command+Wdata frames. 72 bits of data are transferred for every Command+Wdata frame. Two Command+Wdata frames match the 18-byte data transfer of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst of 8 transfers
3.5
Hot-add
DIMM(s) and perform a Hot-Add Reset to bring them into the channel timing domain. It should be noted that the power to the DIMM socket must be removed before a "hot-add" DIMM is inserted or removed. Applying or removing the power to a DIMM socket is a system platform function.
The FB-DIMM channel does not provide a mechanism to automatically detect and report the addition of a new DIMM south of the currently active last DIMM. It is assumed the system will be notified through some means of the addition of one or more new DIMMs so that specific commands can be sent to the host controller to initialize the newly added
3.6
Hot-remove
system can coordinate the procedure to remove power in preparation for physical removal of the DIMM if needed. It should be noted that the power to the DIMM socket must be removed before a "hot-add" DIMM is inserted or removed. Applying or removing the power to a DIMM socket is a system platform function.
In order to accomplish removal of DIMMs the host must perform a Fast Reset sequence targeted at the last DIMM that will be retained on the channel. The Fast Reset re-establish the appropriate last DIMM so that the Southbound Tx outputs of the last active DIMM and the Southbound and Northbound outputs of the DIMMs beyond the last active DIMM are disabled. Once the appropriate outputs are disabled the
3.7
Hot-replace
Hot replace of DIMM is accomplished through combining the Hot-Remove and Hot-Add process.
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4
4.1
Electrical Characteristics
Operating Conditions
This chapter describes the electrical characteristics.
This chapter describes the operating conditions.
TABLE 8
Absolute Maximum Ratings
Parameter Symbol Rating Min. Voltage on any SMbus interface signal pin relative to VSS Voltage on VDD pin relative to VSS Voltage on VCC pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Voltage on VTT pin relative to VSS Storage Temperature Max. +4.00 +2.4 +1.75 +2.3 +2.3 +1.75 +2.3 +100 V V V V V V V C
1) 2)
Unit
Notes
VIN, VOUT VDD VCC VDDQ VDDL VIN, VOUT VTT TSTG
-0.5 -0.5 -0,3 -0.5 -0.5 -0.3 -0.5 -55
-
2)3) 2)3) 2)
-
2)3)
1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV. 3) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
Operating Temperature Range
Parameter Symbol Values Min Junction Temperature DRAM Component Case Temperature Range AMB Component Case Temperature Range Max 115 95 111 C C C
1)2) 3)4) 1)2)
Unit Note
TJ TCASE
0 0 0
1) Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2) Within the DRAM Component Case temperature range all DRAM specifications will be supported.
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3) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C case temperature before initiating self-refresh operation. 4) Above 85 C DRAM case temperature the Auto-Refresh command has to be reduced to tREFI = 3.9 s.
TABLE 10
Supply Voltage Levels and DC Operating Conditions
Parameter Symbol Limit Values Min. AMB Supply Voltage DC AMB Supply Voltage DC + AC DRAM Supply Voltage Termination Voltage EEPROM Supply Voltage DC Input Logic High(SPD) DC Input Logic Low(SPD) DC Input Logic High(RESET) DC Input Logic Low(RESET) Leakage Current (RESET) Leakage Current (Link)
1) 2) 3) 4) 5)
Unit Nom. 1.5 1.5 1.8 0.50 xVDD 3.3 -- -- -- -- -- -- Max. 1.575 1.590 1.9 0.52 xVDD 3.6 VDDSPD 0.8 -- +0.5 +90 +5 V V V V V V V V V
Notes
VCC VDD VTT VDDSPD VIH(DC) VIL(DC) VIH(DC) VIL(DC) IL IL
1.455 1.425 1.7 0.48 xVDD 3.0 2.1 -- 1.0 -- -90 -5
1) 2)
- - -
3) 3) 4) 3) 4) 5)
At 0KHz - 30KHz AT 30KHz - 1 MHz Applies for SMB and SPD Bus Signals Applies for AMB CMOS Signal RESET For all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications
TABLE 11
FB-DIMM Latency Range
Parameter DDR2-800D Min. tC2D_DIMM tRESAMPLE_DIMM_SB tRESAMPLE_DIMM_NB tRESYNC_DIMM_SB tRESYNC_DIMM_NB Tbd Tbd Tbd Tbd Tbd Nom. 19.35 1.68 1.48 2.66 2.54 Max. Tbd Tbd Tbd Tbd Tbd DDR2-667D Min. 17.5 1.4 1.3 2.5 2.4 Typ. 21 1.69 1.73 2.8 2.8 Max. 21.5 2.4 2.3 3.7 3.6 ns ns ns ns ns
1)2) 2)3) 2)4) 2)5) 2)6)
Unit
Note
1) For DDR-800D and DDR-800E no Jedec Standart values are avalible for Min. and Max parameter. 2) Measured delay at FBDIMM gold finger between the center of the1st UI of command frame on the primary southbound lane 81 (connector pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0 (connector pins 22 & 23) - [CL (DRAM CAS latency) value] * [frame clock period - AL (DRAM additional latency) value * frame clock period]. 3) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the primary southbound lane 8 (connector pins 102 & 103) and the center of the 1st UI of the same frame on the secondary southbound lane 8 (connector pins 222 & 223). 4) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins 142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23). 5) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins 142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23).
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6) Measured delay at FBDIMM gold finger between the center of the1st UI of command frame on the primary southbound lane 81 (connector pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0 (connector pins 22 & 23) - [CL (DRAM CAS latency) value] * [frame clock period - AL (DRAM additional latency) value * frame clock period].
TABLE 12
Environmental Parameters
Parameter Operating Temperature Operating Humidity (relative) Storage Temperature Storage Humidity (without condensation) Barometric pressure (operating) Barometric pressure (storage) Symbol TOPR HOPR TSTG HSTG PBAR PBAR Rating See Note 10 to 90 -50 to +100 5 to 95 3050 14240 % C % m m Units Notes
1) 2) 2) 2) 2) 2)
1) The designer must meet the case temperature specifications for individual module components. 2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device funcional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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5
Current Spec. and Conditions
TABLE 13
IDD Measurement Conditions
The following table provides an overview of the measurement conditions.
Parameter Idle Current, single or last DIMM L0 state, idle (0 BW) Primary channel enabled, Secondary channel disabled CKE high. Command and address lines stable. DRAM clock active Idle Current, first DIMM L0 state, idle (0 BW) Primary and Secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active Active Power L0 state 50% DRAM BW, 67% read, 33% write. Primary and Secondary channels enabled. DRAM clock active, CKE high. Training Primary and Secondary channels enabled. 100% toggle on all channels lanes. DRAMs idle (0 BW). CKE high. Command and address lines stable. DRAM clock active. IBIST Over all IBIST modesDRAM Idle (0 BW)Primary channel EnabledSecondary channel EnabledCKE high. Command and Address lines stableDRAM clock active MemBIST Over all MemBIST modes >50% DRAM BW (as dictated by the AMB)Primary channel EnabledSecondary channel EnabledCKE high. Command and Address lines stableDRAM clock active
Symbol ICC_Idle_0 IDD_Idle_0
ICC_Idle_1 IDD_Idle_1
ICC_Active_1 IDD_Active_1
ICC_Training IDD_Training
ICC_IBIST IDD_IBIST ICC_MEMBIST IDD_MEMBIST
Electrical Idle ICC_EI DRAM Idle (0 BW)Primary channel DisabledSecondary channel DisabledCKE low. Command and Address IDD_EI lines FloatedDRAM clock active, ODT and CKE driven low Notes 1. 2. 3. 4. 5. 6. 7. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes. Burst Length = 4. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM). Modeled with 27 termination for command, address, and clocks, and 47 termination for control. Termination is referenced to VTT = VDD / 2.
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5.1
ICC/IDD Conditions
TABLE 14
ICC/IDD Specification for PC2-6400F
In the following table you can find the Measurement Conditions and Power Supply Currents.
Product Type Speed Grade Symbol
HYS72T512420EFA-25F-C PC2-6400F Typ. 1.84 2.77 2.47 4.43 4.41 7.3 3 4.49 2.31 4.16 5.37 8.7 3.16 4.72 4.03 7.27 7.28 12.07 3.67 5.46 2.16 3.9 5.9 9.43 3.4 5.07 2.16 3.9 5.63 9.04 2.39 3.6
Unit
Note
ICC_Idle_0 PCC_Idle_0 IDD_Idle_0 PDD_Idle_0 ITOT_Idle_0 PTOT_Idle_0 ICC_Idle_1 PCC_Idle_1 IDD_Idle_1 PDD_Idle_1 ITOT_Idle_1 PTOT_Idle_1 ICC_Active_1 PCC_Active_1 IDD_Active_1 PDD_Active_1 ITOT_Active_1 PTOT_Active_1 ICC_IBIST PCC_IBIST IDD_IBIST PDD_IBIST ITOT_IBIST PTOT_IBIST ICC_Training PCC_Training IDD_Trainig PDD_Training ITOT_Trainig PTOT_Training ICC_EI PCC_EI
A W A W A W A W A W A W A W A W A W A W A W A W A W A W A W A W
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Product Type Speed Grade Symbol
HYS72T512420EFA-25F-C PC2-6400F Typ. 0.29 0.52 2.78 4.2 3.24 4.84 4.86 8.77 8.13 13.64
Unit
Note
IDD_EI PDD_EI ITOT_EI PTOT_EI ICC_MEMBIST PCC_MEMBIST IDD_MEMBIST PDD_MEMBIST ITOT_MEMBIST PTOT_MEMBIST
A W A W A W A W A W
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TABLE 15
ICC/IDD Specification for PC2-5300F
Product Type Speed Grade Symbol HYS72T512420EFA-3S-C PC2-5300F Typ. 1.65 2.5 2.35 4.15 4.08 6.72 2.66 3.97 2.12 3.73 4.83 7.75 2.81 4.19 3.72 6.52 6.61 10.78 3.21 4.77 2 3.53 5.27 8.35 2.99 4.45 2 3.53 5.05 8.03 2.08 3.13 0.29 0.5 2.47 A W A W A W A W A W A W A W A W A W A W A W A W A W A W A W A W A W A Unit Note
ICC_Idle_0 PCC_Idle_0 IDD_Idle_0 PDD_Idle_0 ITOT_Idle_0 PTOT_Idle_0 ICC_Idle_1 PCC_Idle_1 IDD_Idle_1 PDD_Idle_1 ITOT_Idle_1 PTOT_Idle_1 ICC_Active_1 PCC_Active_1 IDD_Active_1 PDD_Active_1 ITOT_Active_1 PTOT_Active_1 ICC_IBIST PCC_IBIST IDD_IBIST PDD_IBIST ITOT_IBIST PTOT_IBIST ICC_Training PCC_Training IDD_Trainig PDD_Training ITOT_Trainig PTOT_Training ICC_EI PCC_EI IDD_EI PDD_EI ITOT_EI
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Product Type Speed Grade Symbol
HYS72T512420EFA-3S-C PC2-5300F Typ. 3.72 2.85 4.26 4.32 7.59 7.2 11.87
Unit
Note
PTOT_EI ICC_MEMBIST PCC_MEMBIST IDD_MEMBIST PDD_MEMBIST ITOT_MEMBIST PTOT_MEMBIST
W A W A W A W
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6
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 16 "PC2-6400-666" on Page 24 * Table 17 "PC2-5300-555" on Page 28
TABLE 16
PC2-6400-666
Product Type Organization HYS72T512420EFA-25F-C 4 GByte x72 2 Ranks (x4) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Description SPD Size CRC / Total / Used SPD Revision Key Byte / DRAM Device Type Voltage Level of this Assembly SDRAM Addressing Module Physical Attributes Module Type Module Organization Fine Timebase (FTB) Dividend and Divisor Medium Timebase (MTB) Dividend Medium Timebase (MTB) Divisor PC2-6400F-555 Rev. 1.1 HEX 92 11 09 12 49 23 07 10 00 01 04 0A 20 43 32 52 3C 92 60 32 1E
tCK.MIN (min. SDRAM Cycle Time) tCK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
tCAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
tWR.MIN (Write Recovery Time)
Write Latency Times Supported Additive Latency Times Supported
tRCD.MIN (min. RAS# to CAS# Delay) tRRD.MIN (min. Row Active to Row Active Delay)
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Product Type Organization
HYS72T512420EFA-25F-C 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 - 78 79 80 81 82 83 84 85 86 87 88 89 Description
PC2-6400F-555 Rev. 1.1 HEX 32 00 B4 D2 FE 01 1E 1E 03 07 01 C2 57 60 5C 29 2B 2E 4E 25 39 00 21 00 02 00 20 54 50 44 26 3F 50
tRP.MIN (min. Row Precharge Time) tRAS and tRC Extension tRAS.MIN (min. Active to Precharge Time) tRC.MIN (min. Active to Active / Refresh Time) tRFC.MIN LSB (min. Refresh Recovery Time Delay) tRFC.MIN MSB (min. Refresh Recovery Time Delay) tWTR.MIN (min. Internal Write to Read Cmd Delay) tRTP.MIN (min. Internal Read to Precharge Cmd Delay)
Burst Lengths Supported Terminations Supported Drive Strength Supported
tREFI (avg. SDRAM Refresh Period) TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) DRAM T2Q (DT2Q) DRAM T2P (DT2P) DRAM T3N (DT3N) DRAM T4R (DT4R) / T4R4W Sign (DT4R4W) DRAM T5B (DT5B) DRAM T7 (DT7) DRAM Not used FBDIMM ODT Values Not used Channel Protocols Supported LSB Channel Protocols Supported MSB Back-to-Back Access Turnaround Time AMB Read Access Delay for DDR2-800 AMB Read Access Delay for DDR2-667 AMB Read Access Delay for DDR2-533 Psi(T-A) AMB TIdle_0 (DT Idle_0) AMB TIdle_1 (DT Idle_1) AMB
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Product Type Organization
HYS72T512420EFA-25F-C 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 90 91 92 93 94 - 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 125 126 127 Description TIdle_2 (DT Idle_2) AMB TActive_1 (DT Active_1) AMB TActive_2 (DT Active_2) AMB TL0s (DT L0s) AMB Not used AMB Junction Temperature Maximum (Tjmax) Category Byte Not used AMB Personality Bytes: Pre-initialization (1) AMB Personality Bytes: Pre-initialization (2) AMB Personality Bytes: Pre-initialization (3) AMB Personality Bytes: Pre-initialization (4) AMB Personality Bytes: Pre-initialization (5) AMB Personality Bytes: Pre-initialization (6) AMB Personality Bytes: Post-initialization (1) AMB Personality Bytes: Post-initialization (2) AMB Personality Bytes: Post-initialization (3) AMB Personality Bytes: Post-initialization (4) AMB Personality Bytes: Post-initialization (5) AMB Personality Bytes: Post-initialization (6) AMB Personality Bytes: Post-initialization (7) AMB Personality Bytes: Post-initialization (8) AMB Manufacturers JEDEC ID Code LSB AMB Manufacturers JEDEC ID Code MSB DIMM Manufacturers JEDEC ID Code LSB DIMM Manufacturers JEDEC ID Code MSB Module Manufacturing Location Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Cyclical Redundancy Code LSB Cyclical Redundancy Code MSB
PC2-6400F-555 Rev. 1.1 HEX 54 57 53 00 00 11 CA 00 D5 60 08 02 00 00 4C 00 00 00 00 00 00 00 85 51 85 51 xx xx xx xx 0E 0E
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Product Type Organization
HYS72T512420EFA-25F-C 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 175 176 255 Description Module Product Type, Char #1 Module Product Type, Char #2 Module Product Type, Char #3 Module Product Type, Char #4 Module Product Type, Char #5 Module Product Type, Char #6 Module Product Type, Char #7 Module Product Type, Char #8 Module Product Type, Char #9 Module Product Type, Char #10 Module Product Type, Char #11 Module Product Type, Char #12 Module Product Type, Char #13 Module Product Type, Char #14 Module Product Type, Char #15 Module Product Type, Char #16 Module Product Type, Char #17 Module Product Type, Char #18 Module Revision Code Test Program Revision Code DRAM Manufacturers JEDEC ID Code LSB DRAM Manufacturers JEDEC ID Code MSB informal AMB content revision tag (MSB) informal AMB content revision tag (LSB) Not used Blank for customer use
PC2-6400F-555 Rev. 1.1 HEX 37 32 54 35 31 32 34 32 30 45 46 41 32 35 46 43 20 20 2x xx 85 51 43 10 00 FF
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TABLE 17
PC2-5300-555
Product Type Organization HYS72T512420EFA-3S-C 4 GByte x72 2 Ranks (x4) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description SPD Size CRC / Total / Used SPD Revision Key Byte / DRAM Device Type Voltage Level of this Assembly SDRAM Addressing Module Physical Attributes Module Type Module Organization Fine Timebase (FTB) Dividend and Divisor Medium Timebase (MTB) Dividend Medium Timebase (MTB) Divisor PC2-5300F-555 Rev. 1.1 HEX 92 11 09 12 49 23 07 10 00 01 04 0C 20 33 3C 42 3C 72 50 3C 1E 3C 00 B4 F0 FE 01 1E 1E 03
tCK.MIN (min. SDRAM Cycle Time) tCK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
tCAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
tWR.MIN (Write Recovery Time)
Write Latency Times Supported Additive Latency Times Supported
tRCD.MIN (min. RAS# to CAS# Delay) tRRD.MIN (min. Row Active to Row Active Delay) tRP.MIN (min. Row Precharge Time) tRAS and tRC Extension tRAS.MIN (min. Active to Precharge Time) tRC.MIN (min. Active to Active / Refresh Time) tRFC.MIN LSB (min. Refresh Recovery Time Delay) tRFC.MIN MSB (min. Refresh Recovery Time Delay) tWTR.MIN (min. Internal Write to Read Cmd Delay) tRTP.MIN (min. Internal Read to Precharge Cmd Delay)
Burst Lengths Supported
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Product Type Organization
HYS72T512420EFA-3S-C 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 - 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 - 97 98 99 100 101 Description Terminations Supported Drive Strength Supported
PC2-5300F-555 Rev. 1.1 HEX 07 01 C2 56 60 3C 24 2B 28 42 24 2C 00 22 00 02 00 10 54 50 44 26 3F 50 54 57 53 00 00 11 CA 00 D5
tREFI (avg. SDRAM Refresh Period) TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) DRAM T2Q (DT2Q) DRAM T2P (DT2P) DRAM T3N (DT3N) DRAM T4R (DT4R) / T4R4W Sign (DT4R4W) DRAM T5B (DT5B) DRAM T7 (DT7) DRAM Not used FBDIMM ODT Values Not used Channel Protocols Supported LSB Channel Protocols Supported MSB Back-to-Back Access Turnaround Time AMB Read Access Delay for DDR2-800 AMB Read Access Delay for DDR2-667 AMB Read Access Delay for DDR2-533 Psi(T-A) AMB TIdle_0 (DT Idle_0) AMB TIdle_1 (DT Idle_1) AMB TIdle_2 (DT Idle_2) AMB TActive_1 (DT Active_1) AMB TActive_2 (DT Active_2) AMB TL0s (DT L0s) AMB Not used AMB Junction Temperature Maximum (Tjmax) Category Byte Not used AMB Personality Bytes: Pre-initialization (1)
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Product Type Organization
HYS72T512420EFA-3S-C 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 125 126 127 128 129 130 131 132 133 134 135 136 Description AMB Personality Bytes: Pre-initialization (2) AMB Personality Bytes: Pre-initialization (3) AMB Personality Bytes: Pre-initialization (4) AMB Personality Bytes: Pre-initialization (5) AMB Personality Bytes: Pre-initialization (6) AMB Personality Bytes: Post-initialization (1) AMB Personality Bytes: Post-initialization (2) AMB Personality Bytes: Post-initialization (3) AMB Personality Bytes: Post-initialization (4) AMB Personality Bytes: Post-initialization (5) AMB Personality Bytes: Post-initialization (6) AMB Personality Bytes: Post-initialization (7) AMB Personality Bytes: Post-initialization (8) AMB Manufacturers JEDEC ID Code LSB AMB Manufacturers JEDEC ID Code MSB DIMM Manufacturers JEDEC ID Code LSB DIMM Manufacturers JEDEC ID Code MSB Module Manufacturing Location Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Cyclical Redundancy Code LSB Cyclical Redundancy Code MSB Module Product Type, Char #1 Module Product Type, Char #2 Module Product Type, Char #3 Module Product Type, Char #4 Module Product Type, Char #5 Module Product Type, Char #6 Module Product Type, Char #7 Module Product Type, Char #8 Module Product Type, Char #9
PC2-5300F-555 Rev. 1.1 HEX 60 08 02 00 00 4C 00 00 00 00 00 00 00 85 51 85 51 xx xx xx xx 25 29 37 32 54 35 31 32 34 32 30
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Product Type Organization
HYS72T512420EFA-3S-C 4 GByte x72 2 Ranks (x4)
Label Code JEDEC SPD Revision Byte# 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 175 176 255 Description Module Product Type, Char #10 Module Product Type, Char #11 Module Product Type, Char #12 Module Product Type, Char #13 Module Product Type, Char #14 Module Product Type, Char #15 Module Product Type, Char #16 Module Product Type, Char #17 Module Product Type, Char #18 Module Revision Code Test Program Revision Code DRAM Manufacturers JEDEC ID Code LSB DRAM Manufacturers JEDEC ID Code MSB informal AMB content revision tag (MSB) informal AMB content revision tag (LSB) Not used Blank for customer use
PC2-5300F-555 Rev. 1.1 HEX 45 46 41 33 53 43 20 20 20 0x xx 85 51 43 10 00 FF
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7
Package Outline
Bypass capacitors for DDR2 SDRAM devices are located near the device power pins. The AMB device in the center of the DIMM has a metal Heat Sink.
All Components are surface mounted on one or both sides of the PCB and positioned on the PCB to meet the minimum and maximum trace lengths required for DDR2 SDRAM signals.
TABLE 18
Raw Card Reference
JEDEC Raw Card PCB Dimensions Width [mm] R/C Z
1) 2) 3) 4) 5)
Height [mm] 30.35
Thickness [mm] 8.2
Notes
1)2)3)4)5)
L-DIM-240-36
Figure 4
133.35
Thickness includes Heat Sink. Some early production modules with Heatspreader may be thicker up to 8.2mm. Please contact your sales or marketing representative for more details on package dimensions Drawing according to ISO 8015. Dimensions in mm. General tolerances +/- 0.15.
Attention: Heat Sink heat up during operation. When unplugging a DIMM from a system direct skin contact should be avoided until the Heat Sink has reached room temperature. Attention: The Heat Sink is mechanically loaded. Do not remove. Removal of the clip may cause injuries. Attention: Any mechanical stress on the Heat Sink should be avoided. Touching the Heat Sink while plugging or unplugging the module may permanently damage the DIMM.
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FIGURE 4
Package Outline L-DIM-240-36 with Full Module Heat Sink
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8
DDR2 Nomenclature
TABLE 19
Nomenclature Fields and Examples
Example for
Field Number 1 2 64 18 3 T T 4 64 512 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
Micro-DIMM DDR2 DRAM
HYS HYB
TABLE 20
DDR2 DIMM Nomenclature
Field 1 2 3 4 Description Module Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 512 5 6 7 8 9 Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type 0 .. 9 0, 2, 4 0 .. 9 A .. Z D M R U F 10 Speed Grade -25F -2.5 -3 -3S -3.7 -5 Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3
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Field 11
Description Die Revision
Values -A -B
Coding First Second
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
TABLE 21
DDR2 DRAM Nomenclature
Field 1 2 3 4 Description Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G 5+6 Number of I/Os 40 80 16 7 8 9 Product Variations Die Revision Package, Lead-Free Status Speed Grade 0 .. 9 A B C F 10 -25F -2.5 -3 -3S -3.7 -5 Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, Lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
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HYS72T512420EFA-[25F/3S]-C Fully-Buffered DDR2 SDRAM Modules
Contents
1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.6 3.7 4 4.1 5 5.1 6 7 8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Basic Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Memory Buffer Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot-add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot-remove. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 14 14 14 14 15 15 15 15
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Current Spec. and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ICC/IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DDR2 Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Rev.1.20, 2007-10-19 03202007-06NE-DYYI
36
Internet Data Sheet
Edition 2007-10-19 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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