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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93PW46A
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP93PW46A
Low Voltage/Low Power
CMOS 16-Bit Microcontroller
TMP93PW46AF 1. Outline and Device Characteristics
The TMP93PW46A is OTP type MCU which includes 128-Kbyte One-time PROM. Using the adapter-socket, you can write and verify the data for the TMP93CW46A by general EPROM programmer. The TMP93PW46A has the same pin-assignment as the TMP93CW46A (Mask ROM type). Writing the program to built-in PROM, the TMP93PW46A operates as the same way as the TMP93CW46A.
000000H Internal I/O 000080H Internal RAM 001080H External area 008000H Internal ROM (128 Kbytes)
028000H External area FFFF00H Reserved FFFFFFH = Internal area
Figure 1.1 Memory map of TMP93CW46A/TMP93PW46A MCU
TMP93PW46AF
ROM
OTP 128 Kbytes
RAM
4 Kbytes
Package
P-LQFP100-1414-0.50F
Adapter Socket
BM11129
030619EBP1
* The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions.
93PW46A-1
2004-02-10
TMP93PW46A
PA0 to PA6 PA7 (SCOUT) P50 to P57 (AN0 to AN7) AVCC AVSS VREFH VREFL (TXD0) P90 (RXD0) P91 (SCLK0/ CTS0 ) P92 (TXD1) P93 (RXD1) P94 (SCLK1) P95 (TXD2) P60 (RXD2) P61 (SCLK2/ CTS2 ) P62 (TXD3) P63 (RXD3) P64 (SCLK3/ CTS3 ) P65 (TXD4) P66 (RXD4) P67 (TI0) P70
Port A 900/L CPU 10-bit 8-ch AD
converter
VCC [3] VSS [3] Highfrequency OSC Lowfrequency OSC X1 X2 CLK XT1 XT2 AM8/ AM16
EA RESET
Serial I/O (Channel 0) Serial I/O (Channel 1) Serial I/O (Channel 2) Serial I/O (Channel 3) Serial I/O (Channel 4) 8-bit timer (Timer 0) 8-bit timer (Timer 1)
XWA XBC XDE XHL XIX XIY XIZ XSP
WA BC DE HL IX IY IZ SP 32 bits F SR PC
ALE TEST2, TEST1 Interrupt controller P87 (INT0)
NMI
Watchdog timer
WDTOUT
4-Kbyte RAM
Port 0
P00 to P07 (AD0/ to AD7) P10 to P17 (AD8 to AD15/A8 to A15) P20 to P27 (A0 to A7/A16 to A23) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P33 ( WAIT )
Port 1
(TO1) P71
Port 2
(TO2) P72
8-bit PWM (Timer 2) 8-bit PWM (Timer 3) Port 3
(TO3) P73
P34 ( BUSRQ ) P35 ( BUSAK ) P36 ( R / W ) P37 ( RAS )
(INT4/TI4) P80 (INT5/TI5) P81 (TO4) P82 (TO5) P83 (INT6/TI6) P84 (INT7/TI7) P85 (TO6) P86
16-bit timer (Timer 4)
128-Kbyte ROM
16-bit timer (Timer 5)
CS/WAIT controller (3 blocks)
P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) P42 ( CS2 / CAS2 )
Figure 1.2 TMP93PW46A Block Diagram
93PW46A-2
2004-02-10
TMP93PW46A
2.
Pin Assignment and Functions
The assignment of input/output pins for the TMP93PW46A their names and outline functions are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93PW46AF.
Programmable Pull Pull down up
Programmable Pull Pull up down
TMP93PW46A P66/TXD4 P67/RXD4 VSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC
NMI
Pin no. 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Pin no.
TMP93PW46A

88 P65/ CTS3 /SCLK3 87 P64/RXD3 86 P63/TXD3 85 P62/ CTS2 /SCLK2 84 P61/RXD2 83 P60/TXD2 82 P42/ CS2 / CAS2 81 P41/ CS1 / CAS1 80 P40/ CS 0 / CAS 0 79 P37/ RAS 78 P36/ R / W 77 P35/ BUSAK 76 P34/ BUSRQ 75 P33/ WAIT 74 P32/ HWR 73 P31/ WR 72 71 70 69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 53 52 51 P30/ RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 P21/A1/A17 P20/A0/A16 VCC VSS P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 P06/AD6

SIO
ADC
SIO

P70/TI0 P71/TO1 P72/TO2 P73/TO3 P80/INT4/TI4 P81/INT5/TI5 P82/TO4 P83/TO5 P84/INT6/TI6 P85/INT7/TI7 P86/TO6 P87/INT0 P90/TXD0 P91/RXD0 P93/TXD1 P94/RXD1 P95/SCLK1 AM8/ AM16 CLK VCC VSS
Timer
Top view LQFP100
61 WDTOUT
P92/ CTS 0 /SCLK0 19
50 P05/AD5 49 P04/AD4 48 P03/AD3 47 P02/AD2 46 P01/AD1 45 P00/AD0 44 VCC 43 ALE 42 PA7/SCOUT 41 PA6 40 PA5 39 PA4 38 PA3
Clock, Mode
X1 X2
EA RESET
P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2
Figure 2.1.1 Pin Assignment (100-Pin LQFP)
93PW46A-3
2004-02-10
Memory interface
TMP93PW46A
2.2
Pin Names and Functions
(1) Pin function of TMP93PW46A in MCU mode. Table 2.2.1 Name and Function in MCU Mode (1/4)
Pin Name
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
Number of Pins
8 8
I/O
I/O 3 states I/O 3 states Output I/O Output Output
Function
Port 0: I/O port that allows selection of I/O on a bit basis address/data (lower): Bits 0 to 7 for address/data bus Port 1: I/O port that allows selection of I/O on a bit basis Address data (upper): Bits 8 to 15 of address/data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor) Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data on pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to AD15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port 34: I/O port (with pull-up resistor) Bus request: Signal used to request high impedance for AD0 to AD15, A0 to A23, RD , WR , HWR , R/ W , RAS , CS0 , CS1 , and CS2 pins. (For external DMAC) Port 35: I/O port (with pull-up resistor) Bus acknowledge: Signal indicating that AD0 to AD15, A0 to A23, RD , WR , HWR , R / W , RAS , CS0 , CS1 , and CS2 pins are at high impedance after receiving BUSRQ. (For external DMAC) Port 36: I/O port (with pull-up resistor) Read/write: 1 represents read or dummy cycle. 0 represents write cycle. Port 37: I/O port (with pull-up resistor) Row address strobe: Outputs " RAS " strobe for DRAM. Port 40: I/O port (with pull-up resistor) Chip select 0: Outputs 0 when address is within specified address area. Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area.
8
1 1 1 1 1
Output Output Output Output I/O Output I/O Input I/O Input
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
1
I/O Output
P36
R/W
1
I/O Output I/O Output I/O Output Output
P37
RAS
1 1
P40
CS0 CAS0
Note: This device's built-in memory or built-in I/O cannot be accessed with the external DMA controller using the BUSRQ and BUSAK signals.
93PW46A-4
2004-02-10
TMP93PW46A
Table 2.2.2 Name and Function in MCU Mode (2/4) Pin Name
P41
CS1 CAS1
Number of Pins
1
I/O
I/O Output Output I/O Output Output Input Input Input Input I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O Input I/O Output I/O Output I/O Output
Function
Port 41: I/O port (with pull-up resistor) Chip select 1: Outputs 0 if address is within specified address area. Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area. Port 42: I/O port (with pull-down resistor) Chip select 2: Outputs 0 if address is within specified address area. Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area. Port 5: Input port Analog input: Analog signal input for AD converter Pin for high level reference voltage input to AD converter Pin for low level reference voltage input to AD converter Port 60: I/O port (with pull-up resistor) Serial send data 2 Port 61: I/O port (with pull-up resistor) Serial receive data 2 Port 62: I/O port (with pull-up resistor) Serial data send enable 2 (Clear to send) Serial clock I/O 2 Port 63: I/O port (with pull-up resistor) Serial send data 3 Port 64: I/O port (with pull-up resistor) Serial receive data 3 Port 65: I/O port (with pull-up resistor) Serial data send enable 3 (Clear to send) Serial clock I/O 3 Port 66: I/O port (with pull-up resistor) Serial send data 4 Port 67: I/O port (with pull-up resistor) Serial receive data 4 Port 70: I/O port (with pull-up resistor) Timer input 0: Timer 0 input Port 71: I/O port (with pull-up resistor) Timer output 1: Timer 0 or 1 output Port 72: I/O port (with pull-up resistor) PWM output 2: 8-bit PWM timer 2 output Port 73: I/O port (with pull-up resistor) PWM output 3: 8-bit PWM timer 3 output
P42
CS2 CAS2
1
P50 to P57 AN0 to AN7 VREFH VREFL P60 TXD2 P61 RXD2 P62
CTS2
8 1 1 1 1 1
SCLK2 P63 TXD3 P64 RXD3 P65
CTS3
1 1 1
SCLK3 P66 TXD4 P67 RXD4 P70 TI0 P71 TO1 P72 TO2 P73 TO3 1 1 1 1 1 1
93PW46A-5
2004-02-10
TMP93PW46A
Table 2.2.3 Name and Function in MCU Mode (3/4) Pin Name
P80 TI4 INT4 P81 TI5 INT5 P82 TO4 P83 TO5 P84 TI6 INT6 P85 TI7 INT7 P86 TO6 P87 INT0 P90 TXD0 P91 RXD0 P92
CTS0
Number of Pins
1
I/O
I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Input I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O I/O I/O I/O
Function
Port 80: I/O port (with pull-up resistor) Timer input 4: Timer 4 count/capture trigger signal input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 81: I/O port (with pull-up resistor) Timer input 5: Timer 4 count/capture trigger signal input Interrupt request pin 5: Interrupt request pin with rising edge Port 82: I/O port (with pull-up resistor) Timer output 4: Timer 4 output pin Port 83: I/O port (with pull-up resistor) Timer output 5: Timer 4 output pin Port 84: I/O port (with pull-up resistor) Timer input 6: Timer 5 count/capture trigger signal input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Port 85: I/O port (with pull-up resistor) Timer input 7: Timer 5 count/capture trigger signal input Interrupt request pin 7: Interrupt request pin with rising edge Port 86: I/O port (with pull-up resistor) Timer output 6: Timer 5 output pin Port 87: I/O port (with pull-up resistor) Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Port 90: I/O port (with pull-up resistor) Serial send data 0 Port 91: I/O port (with pull-up resistor) Serial receive data 0 Port 92: I/O port (with pull-up resistor) Serial data send enable 0 (Clear to send) Serial clock I/O 0 Port 93: I/O port (with pull-up resistor) Serial send data 1 Port 94: I/O port (with pull-up resistor) Serial receive data 1 Port 95: I/O port (with pull-up resistor) Serial clock I/O 1 Port A0 to A5: I/O ports (Large current output) Port A6: I/O port
1
1 1 1
1
1 1
1 1 1
SCLK0 P93 TXD1 P94 RXD1 P95 SCLK1 PA0 to PA5 PA6 1 1 1 6 1
93PW46A-6
2004-02-10
TMP93PW46A
Table 2.2.4 Name and Function in MCU Mode (4/4) Pin Name
PA7 SCOUT
WDTOUT NMI
Number of Pins
1
I/O
I/O Output Output Input Output
Function
Port A7: I/O port System clock output: Outputs system clock or 2 oscillation clock for synchronizing to external circuit. Watchdog timer output pin Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at rising edge by program. Clock output: Outputs "System clock / 2" clock. Pulled up during reset. Can be disabled for reducing noise. Fixed to "1". Fixed to "1". Address latch enable (Can be disabled for reducing noise.) Reset: Initializes LSI. (with pull-up resistor) High-frequency oscillator connecting pin Low-frequency oscillator connecting pin Port 96: I/O port (Open-drain output) Low-frequency oscillator connecting pin Port 97: I/O port (Open-drain output) TEST1 should be connected with TEST2 pin. Do not connect to any other pins. Power supply pin GND pin (0 V) Power supply pin for AD converter GND pin for AD converter (0 V)
1 1 1
CLK
EA
1 1 1 1 2 1 1 2 3 3 1 1
Input Input Output Input I/O Input I/O Output I/O Output/Input
AM8/ AM16 ALE
RESET
X1/X2 XT1 P96 XT2 P97 TEST1/TEST2 VCC VSS AVCC AVSS
Note: Built-in pull-up/pull-down resistors can be released from the pins other than the RESET pin by software.
93PW46A-7
2004-02-10
TMP93PW46A
2.3
PROM Mode
Table 2.3.1 Name and Function of PROM Mode
Pin Function
A7 to A0 A15 to A8 A16 D7 to D0
CE OE PGM
Number of Pins
8 8 1 8 1 1 1 1 4 4
Input/ Output
Input Input Input I/O Input Input Input Power supply Power supply Power supply
Function
Memory address of program Memory data of program Chip enable Output enable Program control 12.75 V/5 V (Power supply of program) 6.25 V/5 V 0V
Pin Name (MCU mode)
P27 to P20 P17 to P10 P33 P07 to P00 P32 P30 P31
EA
VPP VCC VSS
VCC, AVCC VSS, AVSS
Pin Function
P34
RESET
Number of Pins
1 1 1 1 1 1 7
Input/ Output
Input Input Input Output Input Output Input Input/ Output Fix to low level (Security pin) Fix to low level (PROM mode) Open Self oscillation with resonator
Pin State
CLK ALE X1 X2 P42 to P40 P37 to P35 AM8/ AM16 TEST1, TEST2 P57 to P50 P67 to P60 P73 to P70 P87 to P80 P97 to P90 PA7 to PA0 VREFH VREFL
NMI WDTOUT
Fix to high level TEST1 should be connected with TEST2 pin. Do not connect to any other pins.
2
48
I/O
Open
93PW46A-8
2004-02-10
TMP93PW46A
3.
Operation
This section describes the functions and basic operational blocks of the TMP93PW46A. The TMP93PW46A has PROM in place of the mask ROM which is included in the TMP93CW46A. The other configuration and functions are the same as the TMP93CW46A. Regarding the function of the TMP93PW46A, which is not described herein, see the TMP93CW46A. The TMP93PW46A has two operational modes: MCU mode and PROM mode.
3.1
MCU Mode
(1) Mode setting and function The MCU mode is set by releasing the CLK pin (Pin open). In the MCU mode, the operation is the same as TMP93CW46A. (2) Memory map The memory map of TMP93PW46A is the same as that of TMP93CW46A. The memory map in MCU mode is shown in Figure 3.2.1, and the memory map in PROM mode is shown in Figure 3.2.2.
3.2
Memory Map
Figure 3.2.1 and 3.2.2 are the memory map of the TMP93PW46A.
000000H Internal I/O 000080H Internal RAM 001080H External area 008000H Internal PROM (128 Kbytes) Internal PROM (128 Kbytes) 0000H
028000H External area FFFF00H Reserved FFFFFFH 1FFFFH = Internal area
Figure 3.2.1 Memory Map in MCU Mode
Figure 3.2.2 Memory Map in PROM Mode
93PW46A-9
2004-02-10
TMP93PW46A
3.3
PROM Mode
(1) Mode setting and programming PROM mode is set by setting the RESET and CLK pins to the "L" level. The programming and verification for the internal PROM is achieved by using a general PROM programmer with the adaptor socket. 1. OTP adaptor BM11129: TMP93PW46AF adaptor 2. Setting OTP adaptor Set the switch (SW1) to N side. 3. Setting PROM programmer i) Set PROM type to TC571000D. Size: 1 Mbits (128 K x 8 bits) VPP: 12.75 V tPW: 100 s The electric signature mode (Hereinafter referred to as "signature") is not supported. Therefore using signature with PROM programmer applies voltage of 12.75 V to pin 9 (A9) of the address, and the device is damaged. Do not use signature. ii) Transferring the data (Copy) In TMP93PW46A, PROM is placed on addresses 00000H to 1FFFFH in PROM mode, and addresses 08000H to 27FFFH in MCU mode. Therefore data should be transferred to addresses 00000H to 1FFFFH in PROM mode using the object converter (tuconv) or the block transfer mode. (See instruction manual of PROM programmer.) iii) Setting program address Start address: 00000H End address: 1FFFFH 4. Programming Program/verify according to the procedures of PROM programmer.
93PW46A-10
2004-02-10
TMP93PW46A
VPP (12.75 V/5 V)
EA
VCC AVCC, VCC P30 P32 P31 P07 to P00
RESET OE CE PGM
TEST1 TEST2 P33 P17 to P10 P27 to P20
A16 to A0
D7 to D0
CLK VCC P42 to P40, P37 to P35, AM8/ AM16 P34 * Use the 10 MHz resonator in case of programming and verification by a general EPROM programmer.
X1 X2 VSS AVSS
Security
Figure 3.3.1 PROM Mode Pin Setting (2) Programming flow chart The programming mode is set by applying 12.75 V (Programming voltage) to the VPP pin when the following pins are set as follows, (VCC: 6.25 V, RESET : "L" level, CLK: "L" level). While address and data are fixed and CE pin is set to "L" level, 0.1 ms of "L" level pulse is applied to PGM pin to program the data. Then the data in the address is verified. If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin. This programming procedure is repeated until correct data is read from the address (25 times maximum). Subsequently, all data are programmed in all addresses. The verification for all data is done under the condition of VPP = VCC = 5 V after all data were written. Figure 3.3.2 shows the programming flowchart.
93PW46A-11
2004-02-10
TMP93PW46A
High speed program writing.
Start
VCC = 6.25 V 0.25 V VPP = 12.75 V 0.25 V
Address = Start address
X=0
Program 0.1 ms pulse X=X+1
X > 25? No Error Address = Address + 1 No Verify OK
Last address?
Yes
Yes VCC = 5 V VPP = 5 V Error
Read all data
OK Pass Failure
Figure 3.3.2 Flowchart
93PW46A-12
2004-02-10
TMP93PW46A
(3) Security bit The TMP93PW46A has a security bit in PROM cell. If the security bit is programmed to "0", the content of the PROM is disable to be read in PROM mode. How to program the security bit 1) 2) 3) 4) Set the PROM mode. Set the security pin (Port 34) to "1". Set programming address to "00000H". Set programming data to "FEH".
93PW46A-13
2004-02-10
TMP93PW46A
4.
4.1
Electrical Characteristic
Maximum Ratings
"X" used in an expression shows a frequency of clock fFPH selected by SYSCR1. If a clock gear or a low speed oscillator is selected, a value of "X" is different. The value as an example is calculated at fc, gear = 1/fc (SYSCR1 = "0000").
Parameter
Power supply voltage Input voltage Output current (Per one pin), ports PA0 to PA5 Output current (Per one pin), excluding ports PA0 to PA5 Output current (Total of ports PA0 to PA5) Output current (Total) Output current (Total) Power dissipation (Ta = 85C) Soldering temperature (10 s) Storage temperature Operating temperature
Symbol
VCC VIN IOL1 IOL2 IOL1 IOL IOH PD TSOLDER TSTG TOPR
Rating
- 0.5 to 6.5 - 0.5 to VCC + 0.5 20 2 80 120 - 80 600 260 - 65 to 150 - 40 to 85
Unit
V
mA
mW C
Note:
The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded.
4.2
DC Characteristics (1/2) (VSS = 0 V, Ta = -40 to 85C)
Parameter Symbol
VCC
Condition
fc = 4 to 20 MHz fc = 4 to 12.5 MHz VCC 4.5 V VCC < 4.5 V fs = 30 to 34 kHz
Min
4.5
Typ. (Note)
Max
5.5
Unit
V
Power supply voltage AVCC = VCC AVSS = VSS Input low voltage AD0 to AD15 Port 2 to port A (except P87)
RESET , NMI , INT0
2.7 0.8 0.6 - 0.3 0.3 VCC 0.25 VCC 0.3 0.2 VCC 2.2 2.0 0.7 VCC 0.75 VCC VCC - 0.3 0.8 VCC VCC + 0.3 V
VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4
EA , AM8/ AM16
VCC = 2.7 to 5.5 V
X1 AD0 to AD15 Port 2 to port A (except P87)
RESET , NMI , INT0 EA , AM8/ AM16
Input high voltage
VCC 4.5 V VCC < 4.5 V
VCC = 2.7 to 5.5 V
X1
Note: Typical values are for Ta = 25C and VCC = 5 V unless otherwise noted.
93PW46A-14
2004-02-10
TMP93PW46A
4.2
DC Characteristics (2/2) (VSS = 0 V, Ta = -40 to 85C)
Parameter
Symbol
VOL IOLA VOH1
Condition
IOL = 1.6 mA (VCC = 2.7 to 5.5 V) VOL = 1.0 V (VCC = 2.7 to 5.5 V) IOH = - 400 A (VCC = 3 V 10%) IOH = - 400 A (VCC = 5 V 10%) VEXT = 1.5 V REXT = 1.1 k (Vcc = 5 V 10% only) 0.0 VIN VCC 0.2 VIN VCC - 0.2 VIL2 = 0.2 VCC, VIH2 = 0.8 VCC Vcc = 5 V 10% Vcc = 3 V 10% fc = 1 MHz
Min
Typ. (Note 1)
Max
0.45
Unit
V mA
Output low voltage Output low current (PA0 to PA5)
10 2.4
Output high voltage VOH2 Darlington drive current (8 output pins max) Input leakage current Output leakage current Power down voltage (at STOP, RAM backup)
RESET pull-up resistor
V 4.2
IDAR (Note 2) ILI ILO VSTOP RRST CIO VTH RKL RKH
- 1.0 0.02 0.05 2.0 50 80
-3.5 5 10 6.0 150 200 10
mA
A V k pF V
Pin capacitance Schmitt width RESET , NMI , INT0 Programmable Pull-down resistor Programmable Pull-up resistor NORMAL (Note 3) RUN IDLE2 IDLE1 NORMAL (Note 3) RUN IDLE2 IDLE1 SLOW (Note 3) RUN IDLE2 IDLE1 STOP
0.4 VCC = 5 V 10% VCC = 3 V 10% VCC = 5 V 10% VCC = 3 V 10% VCC = 5 V 10% fc = 20 MHz 10 30 50 100
1.0 80 150 150 300 35 30 18 3.5 42 37 25 5 16 13.5 7.5 1.5 50 42 33 15 10 0.2 20 50
k
VCC = 3 V 10% fc = 12.5 MHz (Typ.: VCC = 3.0 V) ICC VCC = 3 V 10% fs = 32.768 kHz (Typ.: VCC = 3.0 V) Ta 50C Ta 70C Ta 85C
11 9 5.5 1 35 28 20 9
mA
A
VCC = 2.7 to 5.5 V
Note 1: Typical values are for Ta = 25C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guranteed for total of up to 8 ports.
93PW46A-15
2004-02-10
TMP93PW46A
4.3
AC Characteristics
(1) VCC = 5 V 10%
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Parameter
Osc. period ( = x) CLK pulse width A0 to A23 valid CLK hold CLK valid A0 to A23 hold A0 to A15 valid ALE fall ALE fall A0 to A15 hold ALE high pulse width ALE fall RD / WR fall
RD / WR rise ALE rise
Symbol
tOSC tCLK tAK tKA tAL tLA tLL TLC tCL tACL tACH TCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD
(1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode
Variable Min
50 ns 2x - 40 0.5x - 20 1.5x - 70 0.5x - 15 0.5x - 20 x - 40 0.5x - 25 0.5x - 20 x - 25 1.5x - 50 0.5x - 25 3.0x - 55 3.5x - 65 2.0x - 60 2.0x - 40 0 x - 15 2.0x - 40 2.0x - 55 0.5x - 15 3.5x - 90 3.0x - 80 2.0x + 0 2.5x - 120 2.5x + 50 200 1.0x - 40 0.5x - 15 2.5x - 70 0.5x - 15 2.0x - 40 2.0x - 40 1.0x - 40 0.5x - 25 1.0x - 40 1.5x - 65 1.5x - 30
16 MHz Min
62.5 ns 85 11 24 16 11 23 6 11 38 44 6 133 154 65 85 0 48 85 70 16 129 108 125 36 206 200 23 16 86 16 85 85 23 6 23 29 64
20 MHz Min
50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 60 0 35 60 45 10 85 70 100 5 175 200 10 10 55 10 60 60 10 0 10 10 40
Max
33.3 s
Max
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
A0 to A15 valid RD / WR fall A0 to A23 valid RD / WR fall
RD / WR rise A0 to A23 hold
A0 to A15 valid D0 to D15 input A0 to A23 valid D0 to D15 input
RD fall D0 to D15 input
RD low pulse width RD rise D0 to D15 hold
RD rise A0 to A15 output
WR low pulse width
D0 to D15 valid WR rise
WR rise D0 to D15 hold
A0 to A23 valid WAIT input A0 to A15 valid WAIT input
RD / WR fall WAIT hold
tAWH tAWL tCW tAPH tAPH2 tCP tASRH tASRL tRAC tRAH tRAS tRP tRSH tRSC tRCD tCAC tCAS
A0 to A23 valid Port input A0 to A23 valid Port hold
WR rise Port valid
A0 to A23 valid RAS fall A0 to A15 valid RAS fall
RAS fall D0 to D15 input RAS fall A0 to A15 hold RAS low pulse width RAS high pulse width CAS fall RAS rise RAS rise CAS rise RAS fall CAS fall CAS fall D0 to D15 input CAS low pulse width
AC measuring conditions * Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , R / W , CLK, RAS , CAS0 to CAS2 ) Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 x VCC/Low 0.2 x VCC (except for AD0 to AD15)
*
93PW46A-16
2004-02-10
TMP93PW46A
(2) VCC = 3 V 10% No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Osc. period ( = x) CLK pulse width A0 to A23 valid CLK hold CLK valid A0 to A23 hold A0 to A15 valid ALE fall ALE fall A0 to A15 hold ALE high pulse width ALE fall RD / WR fall
RD / WR rise ALE rise
Parameter
Symbol
Variable Min Max
33.3 s 80 ns 2x - 40 0.5x - 30 1.5x - 80 0.5x - 35 0.5x - 35 x - 60 0.5x - 35 0.5x - 40 x - 50 1.5x - 50 0.5x - 40 3.0x - 110 3.5x - 125 2.0x - 115 2.0x - 40 0 x - 25 2.0x - 40 2.0x - 120 0.5x - 40 3.5x - 130 3.0x - 100 2.0x + 0 2.5x - 195 2.5x + 50 200 1.0x - 60 0.5x - 40 2.5x - 90 0.5x - 25 2.0x - 40 2.0x - 40 1.0x - 55 0.5x - 25 1.0x - 40 1.5x - 120 1.5x - 40
12.5 MHz Min
80 ns 120 10 40 5 5 20 5 0 30 70 0 130 155 45 120 0 55 120 40 0 150 140 160 5 250 200 20 0 110 15 120 120 25 15 40 0 80
Max
Unit
tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD
((1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
A0 to A15 valid RD / WR fall A0 to A23 valid RD / WR fall
RD / WR rise A0 to A23 hold
A0 to A15 valid D0 to D15 input A0 to A23 valid D0 to D15 input
RD fall D0 to D15 input
RD low pulse width
RD rise D0 to D15 hold RD rise A0 to A15 output
WR low pulse width
D0 to D15 valid WR rise
WR rise D0 to D15 hold
A0 to A23 valid WAIT input A0 to A15 valid WAIT input
RD / WR fall WAIT hold
tAWH tAWL tCW tAPH tAPH2 tCP tASRH tASRL tRAC tRAH tRAS tRP tRSH tRSC tRCD tCAC tCAS
A0 to A23 valid Port input A0 to A23 valid Port hold
WR rise Port valid
A0 to A23 valid RAS fall A0 to A15 valid RAS fall
RAS fall D0 to D15 input RAS fall A0 to A15 hold RAS low pulse width RAS high pulse width CAS fall RAS rise RAS rise CAS rise RAS fall CAS fall CAS fall D0 to D15 input CAS low pulse width
AC measuring conditions * * Output level: High 0.7 x VCC/Low 0.3 x VCC, CL = 50 pF Input level: High 0.9 x VCC/Low 0.1 x VCC
93PW46A-17
2004-02-10
TMP93PW46A
(1) Read cycle
tOSC X1 tCLK CLK tAK A0 to A23 tKA
CS0 to CS2
R/W
tAWH tAWL
tCW
WAIT
tAPH tAPH2 Port input (Note) tASRH tRSH
RAS
tRP
tRAS tASRL tRAH tRCD tADH tRAC tCAS tCAC
tRSC
CAS0 to CAS2
tCA tRR tRAE tHR D0 to D15 tCL
RD
tACH tACL tLC
tRD tADL
AD0 to AD15 tAL ALE tLL
A0 to A15 tLA
Note:
Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
93PW46A-18
2004-02-10
TMP93PW46A
(2) Write cycle
X1
CLK
A0 to A23
CS0 to CS2
R/W
WAIT
Port output (Note) tCP
RAS
CAS0 to CAS2
WR
,
HWR
tWW tDW AD0 to AD15 A0 to A15 D0 to D15 tWD
ALE
Note:
Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
93PW46A-19
2004-02-10
TMP93PW46A
4.4
AD Conversion Characteristics (VSS = 0 V, Ta = -40 to 85C, AVCC = VCC, AVSS = VSS)
Parameter Symbol
VREFH VREFL VAIN VCC = 5 V 10% IREF (VREFL = 0 V) VCC = 3 V 10% VCC = 2.7 to 5.5 V -
10
Power Supply
VCC = 5 V 10% VCC = 3 V 10% VCC = 5 V 10% VCC = 3 V 10%
Min
VCC - 1.5 VCC - 0.2 VSS VSS VREFL
Typ.
VCC VCC VSS VSS 0.5 0.3 0.02 1.0 1.0
Max
VCC VCC VSS + 0.2 VSS + 0.2 VREFH 1.5 0.9 5.0 3.0 3.0
Unit
Analog reference voltage (+) Analog reference voltage (-) Analog input voltage range Analog current for analog reference voltage = 1 = 0 Error
V
mA A LSB
VCC = 5 V 10% VCC = 3 V 10%
Note 1: 1LSB = (VREFH - VREFL)/2
[V]
Note 2: Minimum operation frequency The operation of the AD converter is guaranteed only when fc (High-frequency oscillator) is used. (It is not guaranteed when fs is used.) Additionally, it is guaranteed with fFPH 4 MHz. Note 3: The value Icc includes the current which flows through AVCC pin. Note 4: Error excludes quantizing errors.
4.5
Serial Channel Timing (I/O interface mode)
(1) SCLK input mode
Parameter Symbol Min Variable Max 32.768 kHz
(Note)
12.5 MHz Min
1.28 s 190 ns 300 ns 0
20 MHz Min
0.8 s 100 ns 150 ns 0
Min
488 s 91.5 s 152 s 0
Max
Max
Max
SCLK cycle Output data Rising edge of SCLK SCLK rising edge Output data hold SCLK rising edge Input data hold SCLK rising edge Effective data input
tSCY tOSS tOHS tHSR tSRD
16X tSCY/2 - 5X - 50 5X - 100 0 tSCY - 5X - 100
336 s
780 ns
450 ns
(2) SCLK output mode
Parameter
SCLK cycle (Programmable) Output data SCLK rising edge SCLK rising edge Output data hold SCLK rising edge Input data hold SCLK rising edge Effective data input
Symbol
Variable Min Max
8192X
32.768 kHz Min
488 s 427 s 60 s 0
(Note)
12.5 MHz Min
1.28 s 970 ns 80 ns 0
20 MHz Min
0.8 s 550 ns 20 ns 0
Max
250 ms
Max
655.36 s
Max
409.6 s
tSCY tOSS tOHS tHSR tSRD
16X tSCY - 2X - 150 2X - 80 0
tSCY - 2X - 150
428 s
970 ns
550 ns
(3) SCLK input mode (UART mode) Parameter
SCLK cycle SCLK Low level pulse width SCLK High level pulse width
Symbol
tSCY tSCYL tSCYH
Variable Min
4X + 20 2X + 5 2X + 5
32.768 kHz
(Note)
12.5 MHz Min
340 ns 165 ns 165 ns
20 MHz Min
220 ns 105 ns 105 ns
Max
Min
122 s 6 s 6 s
Max
Max
Max
Note: When fs is used as system clock (fSYS) or fs is used as input clock to prescaler.
93PW46A-20
2004-02-10
TMP93PW46A
4.6
Timer/Counter Input Clock (TI0, TI4, TI5, TI6, TI7)
Parameter Symbol
tVCK tVCKL tVCKH
Variable Min
8X + 100 4X + 40 4X + 40
12.5 MHz Max Min
740 360 360
20 MHz Min
500 240 240
Max
Max
Unit
ns ns ns
Clock cycle Low level clock pulse width High level clock pulse width
4.7
Interrupt and Capture
(1) NMI , INT0 interrupt Parameter Symbol
tINTAL tINTAH
Variable Min
4X 4X
12.5 MHz Max Min
320 320
20 MHz Min
200 200
Max
Max
Unit
ns ns
NMI , INT0 low level pulse width NMI , INT0 high level pulse width
(2) INT4 to INT7 interrupt, capture Parameter
INT4 to INT7 low level pulse width INT4 to INT7 high level pulse width
Symbol
tINTBL tINTBH
Variable Min
4X + 100 4X + 100
12.5 MHz Max Min
420 420
20 MHz Min
300 300
Max
Max
Unit
ns ns
4.8
SCOUT Pin AC Characteristics
Parameter Symbol Variable Min
0.5X - 10 tSCH VCC = 3 V 10% VCC = 5 V 10% tSCL VCC = 3 V 10% 0.5X - 20 20 - - 0.5X - 20 0.5X - 10 20 30 - 15 ns -
12.5 MHz Max Min
30
20 MHz Min
15
Max
Max
Unit
High to level pulse width High to level pulse width Low to level pulse width Low to level pulse width
VCC = 5 V 10%
ns
Measurement condition * Output level: High 2.2 V/Low 0.8 V, CL = 10 pF
tSCH tSCL SCOUT
93PW46A-21
2004-02-10
4.9
tSCY
SCLK
tOSS
tOHS
Output data TXD 0 1 2
3
Timing Chart for I/O Interface Mode
tSR tHS Valid
93PW46A-22
Valid
Input data RXD
Valid
Valid
Note: SCLK is reversed in SCLK input falling mode.
TMP93PW46A
2004-02-10
TMP93PW46A
4.10 Timing Chart for Bus Request ( BUSRQ )/Bus Acknowledge ( BUSAK )
(Note 1) CLK tBRC
BUSRQ
tBRC tCBAL tCBAH
BUSAK
tBAA AD0 to AD15, A0 to A23, CS0 to CS2 , R / W , RAS , CAS0 to CAS2 tABA (Note 2)
(Note 2)
RD , WR , HWR
ALE
Parameter
BUSRQ set to up time to CLK
Symbol
tBRC tCBAL tCBAH tABA tBAA
Variable Min
120 1.5x + 120 0.5x + 40 0 0 80 80
12.5 MHz Min
120 240 80 0 0 80 80
20 MHz Min
120 195 65 0 0 80 80
Max
Max
Max
Unit
ns ns ns ns ns
CLK BUSAK falling edge CLK BUSAK rising edge Output buffer is off to BUSAK
BUSAK
to output buffer is on.
Note 1:
The bus will be released after the WAIT request is inactive, when the BUSRQ is set to "0" during "Wait" cycle. This line only shows the output buffer is off to state. It doesn't indicate the signal level is fixed. Just after the bus is released, the signal level which is set before the bus is released is kept dynamically by the external capacitance. Therefore, to fix the signal level by an external resistor during bus releasing, designing is executed carefully because the level to fix will be delayed. The internal programmable pull-up/pull-down resistor is switched active/non-active by an internal signal.
Note 2:
93PW46A-23
2004-02-10
TMP93PW46A
4.11 Read Operation in PROM Mode
DC/AC characteristics
Ta = 25 5C VCC = 5 V 10%
Parameter
VPP read voltage Input high voltage (A0 to A16, CE , OE , PGM ) Input low voltage (A0 to A16, CE , OE , PGM ) Address to output delay TCYC = 400 ns (10 MHz Clock) = 200 ns
Symbol
VPP VIH1 VIL1 tACC
Condition
- - - CL = 50 PF
Min
4.5 2.2 -0.3 -
Max
5.5 VCC + 0.3 0.8 2.25 TCYC +
Unit
V ns
4.12 Program Operation in PROM Mode
DC/AC characteristics
Ta = 25 5C VCC = 6.25 V 0.25 V
Parameter
Programming supply voltage Input high voltage (D0 to D7, A0 to A16, CE , OE , PGM ) Input low voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VCC supply current VPP supply current
PGM program pulse width
Symbol
VPP VIH VIL ICC IPP tPW
Condition
- - - fc = 10 MHz VPP = 13.00 V CL = 50 PF
Min
12.50 2.6 -0.3 - - 0.095
Typ.
12.75
Max
13.00 VCC + 0.3 0.8 50 50
Unit
V
mA ms
0.1
0.105
4.13 Timing Chart of Read Operation in PROM Mode
A0 to A16
CE
OE
PGM
tACC D0 to D7 Data output
93PW46A-24
2004-02-10
TMP93PW46A
4.14 Timing Chart of Program Operation in PROM Mode
High-speed programming formula
A0 to A16
CE
OE
D0 to D7
Unknown
Data-in stable
Data-out valid
tPW
PGM
VPP
Note 1: The power supply of VPP (12.75 V) must be turned on at the same time or the later time for a power supply of VCC and must be clear power-on at the same time or early time for a power supply of VCC. Note 2: The pull-up/pull-down device on condition of VPP = 12.75 V suffers a damage for the device. Note 3: The maximum spec of VPP pin is 14.0 V. Be careful a overshoot at the programming.
93PW46A-25
2004-02-10
TMP93PW46A
5.
Package Dimensions
P-LQFP100-1414-0.50F Unit: mm
93PW46A-26
2004-02-10

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