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ASDL-3212
IrDA Data Compliant Low Power .52 Mbit/s Infrared Transceiver
Data Sheet
Description
The ASDL-3212 is a new generation ultra small low cost infraredtransceivermodulewhichiscompliancetoIrDA Physical Layers specifications version 1.4 low power from 9.6Kbits/s to 1.152Mbit/s (MIR) with extended link distance. It is IEC825-Class 1 eye safe and designed for very low power consumption which is ideal for battery operated handheld devices. ASDL-3212 features lower pin count through integrated input-output function for interfacingwithlowvoltage1.5V
General Features
* Operatingtemperaturefrom-25C~85C - Criticalparametersareguaranteedover temperatureandsupplyvoltage * VccSupply2.4to3.6V * InterfacetoVariousSuperI/OandControllerDevices - Support Integrated Input/Output InterfaceVoltage of1.5V * MiniaturePackage - Height:1.64mm - Width:7.00mm - Depth:2.73mm * MoistureLevel3 * NoProgrammingrequired * LEDStuck-HighProtection * HighEMIPerformance * Designed to Accommodate Light Loss with Cosmetic Windows * IEC825-Class1EyeSafe
Applications
* Mobiledatacommunication - MobilePhones - PDAs - DigitalStillCameras - Printer - HandyTerminals - IndustrialandMedicalInstrument
Application Support Information
The Application Engineering Group is available to assist you with the application design associated with ASDL3212infraredtransceivermodule.Youcancontactthem through your local sales representatives for additional details.
IrDA Features
* Fully ComplianttoIrDA1.4 PhysicalLayer LowPower Specificationsfrom9.6kbit/sto1.15Mbit/s -TypicalLinkDistance>50cm * Completeshutdown * LowPowerConsumption - Lowshutdowncurrent - Lowidlecurrent
Order Information
Part Number ASDL-322-02 Packaging Type Tape and Reel Package Front Option Quantity 2500
Marking Information
Theunitismarkedwith`.PYWWLL' P Y LL =Productcode =1digitnumericcodeforyear =2digitshexadecimalcodeforlotinformation
WW =2digitsnumericcodeforworkweek
Vcc
CX2 CX1 5 6 GnD
Tri-State CMOS buffer
PostAmp
Quantizer
RXD
3
Low Pass Filter
Ambient DC Cancellation
VLED
SD LEDA
4
Regulated Voltage Supply
AGC
R1
1 CX3 r TxD Buffe Stuck One Protection
TXD 2
ASDL-3212 Transceiver Module
Figure 1. Functional Block Diagram
2
PreAmp
PD
Buffer
Recommended Application Circuit Components
Recommended Value R 2.7 5%,0.25 watt for 2.4 VLED < 2.6 3.3 5%,0.25 watt for 2.6 VLED < 2.8 3.9 5%,0.25 watt for 2.8 VLED < 3.0 4.7 5%,0.25 watt for 3.0 VLED < 3.3 5.6 5%,0.25 watt for 3.3 VLED < 3.5 6.8 5%,0.25 watt for 3.5 VLED < 3.8 8.2 5%,0.25 watt for 3.8 VLED < 4.2 0 5%,0.25 watt for 4.2 VLED < 4.7 2 5%,0.25 watt for 4.7 VLED < 5.0 CX2 CX, CX3 00 nF, 20%, X7R Ceramic 6.8 mF, 20%, Tantalum 7 7 Note
Note: 7. CX1 & CX2 must be placed within 0.7cm of ASDL-3212 to obtain optimumnoiseimmunity
I/O Pins Configuration Table
Pin 2 3 4 5 6 Symbol LEDA TxD RxD SD Vcc GND Description LED Anode IrDA transmitter data input. IrDA receive data Shutdown Supply Voltage Ground Input, Active High Output, Active Low Input, Active High I/O Type Notes Note Note 2 Note 3 Note 4 Note 5 Note 6
6 5 4 3 2 1 Rear View
Figure 2. Pin out
Note: 1. Tiedthroughexternalresistor,R1,toVled.Refertothetablebelowforrecommendedseriesresistorvalue. 2. ThispinisusedtotransmitserialdatawhenSDpinislow.Ifheldhighforlongerthan50ms,theLEDisturnedoff.DoNOTfloatthispin. 3. ThispiniscapableofdrivingastandardCMOSorTTLload.Noexternalpull-uporpull-downresistorisrequired.Thepinisintri-statewhenthe transceiverisinshutdownmode 4. CompleteshutdownofICandPINdiode.DoNOTfloatthispin. 5. Regulated,2.4Vto3.6V 6. Connecttosystemground.
CAUTION: The BiCMOS inherent to the design of this component increases the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
3
Absolute Maximum Ratings
Parameter Storage Temperature Junction Temperature Operating Temperature LED Anode Voltage Supply Voltage Input Voltage : TXD, SD/Mode Output Voltage : RXD Peak LED Current DC LED Current Symbol TS TJ TA VLEDA VCC VI VO ILED (PK) ILED (DC) -25 0 0 0 0 Min. -40 Max. +00 +00 +85 6 6 6 6 300 60 Units C C C V V V V mA mA 20% duty cycle, 27ns pulse width Fig. 5 Fig. 6 Conditions Ref
Recommended Operating Conditions
Parameter Operating Temperature Supply Voltage Logic Input Voltage for TXD, SD/Mode Receiver Input Irradiance Logic High Symbol TA VCC VIH VIL EIH Min. -25 2.4 .3 0 0.0090 0.0225 Logic Low LED (Logic High) Current Pulse Amplitude Receiver Data Rate Ambient Light EIL ILEDA 0.0096 250 .52 Typ. Max. +85 3.6 .8 0.5 500 500 0.3 mW/cm2 mA Mbit/s See IrDA Serial Infrared Physical Layer Link Specification, Appendix A for ambient levels Units C V V V mW/cm2 For in-band signals 5.2kbit/s [8] 0.576 Mbit/s in-band signals .52 Mbit/s [8] For in-band signals [8] VLED = 3.0V, RLED = 4.7W, VI(TxD) VIH Conditions
Note : [8] An in-band optical signal is a pulse/sequence where the peak wavelength, lp, is defined as 850 mp 900 nm, and the pulse characteristicsarecompliantwiththeIrDASerialInfraredPhysicalLayerLinkSpecificationv1.4.
4
Electrical and Optical Specifications
Specifications(Min.&Max.values)holdovertherecommendedoperatingconditionsunlessotherwisenoted.Unspecifiedtestconditionsmaybeanywhereintheiroperatingrange.Alltypicalvalues(Typ.)areat25CandVccsetto3.0V unlessotherwisenoted.
Receiver
Parameter Viewing Angle Peak Sensitivity Wavelength RxD_IrDA Output Voltage RxD_IrDA Pulse Width (SIR) [9, 0] RxD_IrDA Pulse Width (MIR) [9, ] RxD_IrDA Rise & Fall Times Receiver Latency Time [2] Receiver Wake Up Time [3] Logic High Logic Low Symbol 2q/2 lP VOH VOL tRPW(SIR) tRPW(MIR) tr, tf tL tRW .3 0 .5 250 60 20 200 Min. 30 875 .8 0.4 Typ. Max. Units nm V V ms ns ns ms ms q/2 5, CL=9pF, EI = 0 mW/cm2 q/2 5, CL=9pF, EI = 0 mW/cm2 CL=9pF EI = 9.0 mW/cm2 EI = 0 mW/cm2 IOH = -00 mA, EI 0.3 mW/cm2 Conditions
Infrared (IR) Transmitter
Parameter IR Radiant Intensity IR Viewing Angle IR Peak Wavelength TxD_IrDA Logic Levels TxD_IrDA Input Current Wake Up Time [4] Maximum Optical Pulse Width [5] TXD Pulse Width (SIR) TXD Pulse Width (MIR) TxD Rise & Fall Times (Optical) IR LED Anode On-State Voltage High Low High Low Symbol IEH 2q/2 lP VIH VIL IH IL tTW tPW(Max) tPW(SIR) tPW(MIR) tr, tf VON (LEDA) 2.0 200 70 .6 27 600 40 .3 0 Min. 9 30 870 .8 0.5 0 0 Typ. 80 60 Max. Units mW/sr nm V V mA mA ns ms ms ns ns ns V tPW (TXD) =.6ms at 5.2 kbit/s tPW (TXD) =27ns at .52 Mbit/s tPW(TXD) =.6ms at 5.2 kbit/s tPW(TXD) =27ns at .5 Mbit/s ILEDA = 250mA, VI(TxD) VIH VI VIH 0 VI VIL Conditions ILEDA = 250mA, q/2 5, VI (TxD) VIH,
Transceiver
Parameters Input Current Supply Current High Low Shutdown Idle (Standby) Symbol IH IL ICC ICC5 445 Min. Typ. Max. 570 Units mA mA mA mA Conditions VI VIH 0 VI VIL VSD > VCC-.3, TA=25C, no DC ambient VI(TxD) VIL, EI=0
5
Note: [9]Anin-bandopticalsignalisapulse/sequencewherethepeakwavelength,lP,isdefinedas850nmlP900nm,andthepulsecharacteristics arecompliantwiththeIrDASerialInfraredPhysicalLayerLinkSpecificationversion1.4. [10]Forin-bandsignals115.2kbit/swhere9mW/cm2EI500mW/cm2. [11]Forin-bandsignals1.152Mbit/swhere22mW/cm2EI500mW/cm2. [12]LatencyisdefinedasthetimefromthelastTxDlightoutputpulseuntilthereceiverhasrecoveredfullsensitivity. [13]ReceiverWakeUpTimeismeasuredfromVccpowerONtovalidRxDoutput. [14]TransmitterWakeUpTimeismeasuredfromVccpowerONtovalidlightoutputinresponsetoaTxDpulse. [15]TheMaxOpticalPWisdefinedasthemaximumtimewhichtheIRLEDwillturnon,this,istopreventthelongTurnOntimefortheIRLED.
2.20 2.10
120 100
Radiant Intensity (mW/sr)
50.0E-3 100.0E-3 150.0E-3 200.0E-3 250.0E-3 300.0E-3 350.0E-3 ILED (A)
2.00 VLED_A (V) 1.90 1.80 1.70 1.60 1.50 1.40 000.0E+0
80 60 40 20 0 000.0E+0
50.0E-3
100.0E-3 150.0E-3 200.0E-3 250.0E-3 300.0E-3 350.0E-3 ILED (A)
Figure 3. VLED_A vs. ILED
Figure 4. Radiant Intensity vs ILED
ILED(PK) Maximum Peak LED Current - mA
I LED(DC) , Maximum DC LED Current - mA
350 300 250 200 150 100 50 0 -40 -20
Max. Permissible Peak LED Current
70 60 50 40 30 20 10 0 -40 -20
Max. Permissible DC LED Current
Rja = 400degC/W
0 20 40 60 TA - Ambient Temperature - oC
80
100
0 20 40 60 TA - Ambient Temperature - oC
80
100
Figure 5. Maximum Peak LED current vs. ambient temperature. Derated based on TJMAX = 100C.
Figure 6 Maximum DC LED current vs. ambient temperature. Derated based on TJMAX = 100C.
6
ASDL-3212 (Option -021) Package Dimensions
Figure 7. Package Dimension for ASDL-3212-021
7
ASDL-3212 (Option -021) Tape & Reel Dimensions
Unit: mm 1.5 POLARITY Pin 6: GND 7.5 0.1 16.0 0.2
+0.1 0
4.0 0.1 2.0 0.1 1.75 0.1
Pin 1: LEDA 0.3 0.05 1.85 0.1
7.4 0.1 2.7 0.1 8.0 0.1 Progressive Direction
Empty (40mm min)
Parts Mounted
Leader (400mm min)
Empty (40mm min)
Option # 021
"B" 330
"C" 80
Quantity 2500
Unit: mm Detail A 2.0 0.5 13.0 0.5 B C
R1.0 LABEL 21 0.8 Detail A 16.4
+2 0
2.0 0.5
Figure 8. Tape and Reel dimensions
8
Moisture Proof Packaging
ASDL-3212 options are shipped in moisture proof package.Onceopened,moistureabsorptionbegins. ThispartiscomplianttoJEDECLevel3.
Units in A Sealed Mositure-Proof Package
Package Is Opened (Unsealed)
Environment less than 30 deg C, and less than 60% RH ?
Yes
No Baking Is Necessary
Yes
Package Is Opened less than 168 hours ?
No
Perform Recommended Baking Conditions
No
Figure 9. Baking Conditions Chart
Baking Conditions
Ifthepartsarenotstoredindryconditions,theymustbe bakedbeforereflowtopreventdamagetotheparts. Package In reels Temp 60 C Time 48hours 4hours
Recommended Storage Conditions
Storage Temperature Relative Humidity 0C to 30C below 60% RH
Time from unsealing to soldering
Afterremovalfromthebag,thepartsshouldbesoldered within7daysifstoredattherecommendedstorageconditions.Iftimeslongerthan7daysareneeded,theparts
In bulk 00 C Bakingshouldonlybedoneonce.
9
Recommended Reflow Profile
255 MAX 260C R3 R4
T - TEMP ERATURE (C)
230 220 200 180 160 120 80 25 0 P1 HEAT UP 50 R1
R2
60 s e c MAX Ab o ve 220 C
R5
100 P2 S OLDER P AS TE DRY
150
200 P3 S OLDER REFLOW
250 P4 COOL DOWN
300 t-TIME (S ECONDS )
Process Zone Heat Up Solder Paste Dry Solder Reflow Cool Down
Symbol P, R P2, R2 P3, R3 P3, R4 P4, R5
DT 25C to 60C 60C to 200C 200C to 255C (260C at 0 seconds max) 255C to 200C 200C to 25C
Maximum DT/Dtime 3C/s 0.5C/s 4C/s -6C/s -6C/s
The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different DT/Dtime temperature change rates. The DT/Dtime rates are detailed intheabovetable.Thetemperaturesaremeasuredatthe componenttoprintedcircuitboardconnections. In process zone P1, the PC board and ASDL-3212 castellation pins are heated to a temperature of 160C to activate the flux in the solder paste. The temperature rampuprate,R1,islimitedto3Cpersecondtoallowfor evenheatingofboththePCboardandASDL-3212castellations. Process zone P2shouldbeofsufficienttimeduration(60 to120seconds)todrythesolderpaste.Thetemperature is raised to a level just below the liquidus point of the solder,usually200C(392F).
Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus pointofsolderto255C(491F)foroptimumresults.The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls intoliquidsolderandtheformationofgoodsolderconnections. Beyond a dwell time of 60 seconds, the intermetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reducedtoapointbelowthesolidustemperatureofthe solder, usually 200C (392F), to allow the solder within theconnectionstofreezesolid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25C (77F) should not exceed 6C per second maximum. This limitation is necessary to allow the PC boardandASDL-3212castellationstochangedimensions evenly,puttingminimalstressesontheASDL-3212transceiver.
0
Appendix A: ASDL-3212 (Option -021) SMT Assembly Application Note Solder Pad, Mask and Metal Stencil
Stencil Aperture Metal Stencil for Solder Paste Printing Aperture As Per Land Dimensions t
Land Pattern Solder Mask l PCBA
w
Figure A3. Solder stencil aperture
Stencil thickness, t (mm)
Figure A1. Stencil and PCBA
Aperture size (mm) Length, l .75 +/- 0.05 2.40 +/- 0.05 Width, w 0.55 +/- 0.05 0.55 +/- 0.05
0.27mm 0.0mm
Recommended land pattern
C L
Adjacent Land Keepout and Solder Mask Areas
Adjacent land keepout is the maximum space occupied bytheunitrelativetothelandpattern.Thereshouldbe nootherSMDcomponentswithinthisarea.Theminimum solderresiststripwidthrequiredtoavoidsolderbridging adjacent pads is 0.2mm. It is recommended that two fiducially crosses be placed at mid length of the pads for unitalignment.
0.775
Mounting Center 0.10
1.75 fiducial 0.60 1.425 2.375 Unit: mm 0.95 Pitch
j
h
k
Figure A2. Land Pattern
Solder mask Units: mm
l
Recommended Metal Solder Stencil Aperture
It is recommended that only a 0.11mm (0.004 inch) or a 0.127mm (0.005 inch) thick stencil be used for solder pasteprinting.Thisistoensureadequateprintedsolder paste volume and no shorting. See the table below the drawing for combinations of metal stencil aperture and metalstencilthicknessthatshouldbeused.Comparedto 0.127mm stencil thickness 0.11mm stencil thickness has longer length in land pattern. It is extended outwardly from transceiver to capture more solder paste volume. Seefigure3. Dimension h l k j mm 0.2 3.0 3.0 8.6
Note:Wet/LiquidPhoto-imaginablesolderresist/maskisrecommended.
Figure A4. Adjacent Land Keepout and solder mask areas
Appendix B: PCB Layout Suggestion
The ASDL-3212 is a shieldless part and hence does not contain a shield trace unlike the other transceivers.The effects of EMI and power supply noise can potentially reducethesensitivityofthereceiver,resultinginreduced linkdistance.ThefollowingPCBlayoutguidelinesshould be followed to obtain a good PSRR and EM immunity resultingingoodelectricalperformance.Thingstonote: 1. The ground plane should be continuous under the part. 2. VLED and Vcc can be connected to either unfiltered or unregulated power supply. If VLED and Vcc share the same power supply, CX3 need not be used. The connections for CX1 and CX2 should be connected beforethecurrentlimitingresistorR1. 3. CX2isgenerallyaceramiccapacitoroflowinductance providing a wide frequency response while CX1 and CX3 are tantalum capacitor of big volume and fast frequency response. The use of a tantalum capacitor ismorecriticalontheVLEDline,whichcarriesahigh current. 4. Preferably a multi-layered board should be used to provide sufficient ground plane. Use the layer underneath and near the transceiver module as Vcc, and sandwich that layer between ground connected board layers. The diagrams below demonstrate an exampleofa4-layerboard: Theareaunderneaththemoduleatthesecondlayer,and 3cminalldirectionaroundthemoduleisdefinedasthe critical ground plane zone.The ground plane should be maximized in this zone.The layout below is based on a 2-layerPCB.
Top Layer
Bottom Layer
Top layer Connect the module ground pin to bottom ground layer Layer 2 Critical ground plane zone. Do not connect directly to the module ground pin Layer 3 Keep data bus away from critical ground plane zone Bottom layer (GND)
2
Appendix C: General Application Guide for the ASDL-3212 Infrared IrDA(R) Compliant 1.15Mb/s Transceiver Description
The ASDL-3212 is a low-cost and ultra small infrared transceiver module that provides the interface between logic and infrared (IR) signals for through air, serial, half duplexIRdatalink.Thedeviceisdesignedtoaddressthe mobilecomputingmarketsuchasPDAs,aswellassmall embeddedmobileproductssuchasdigitalcamerasand cellularphones.ItisfullycomplianttoIrDA1.4lowpower specification from 9.6kb/s to 1.15Mb/s. The design of ASDL-3212alsoincludesthefollowinguniquefeatures: * Lowpassivecomponentcount; * Shutdown mode for low power consumption requirement; * DirectinterfacewithSuperI/Ologiccircuit.
Selection of Resistor R1
Resistor R1 should be selected to provide the appropriate peak pulse LED current at different ranges ofVcc as shown under "Recommended Application Circuit Components".
Interface to the Recommended I/O chip
The ASDL-3212's TXD data input is buffered to allow for CMOS drive levels. No peaking circuit or capacitor is required. Data rate from 9.6kb/s up to 1.15Mb/s is availableatRXDpin. FiguresC1andC2showhowASDL-3212fitsintoamobile phoneandPDAplatformrespectively.
STN/TFT LCD Panel
Key Pad
LCD Control Touch Panel A/D
Peripherial interface PWM
LCD Backlight Contrast
*ASDL 3212
Mobile Application chipset
IrDA interface
AC97 sound Memory Expansion Logic Bus Driver Memory I/F Baseband I2S controller
PCM Sound
Audio Input
ROM FLASH SDRAM
Power Management
Antenna
Figure C1. Mobile Application Platform
3
Color Co Display Antenna
LCD Data/Timing Control *ASDL-3212 LCD Interface
External Memory Interface
Peripheral Interface
Flash/ ROM/DRAM OS/Apps Configuration EEPROM
Key Pad Camera Smart Card MMC SD
PDA Application Chipset
USB Reset
McBSP
Wired Connectivity USB Controller
Stereo Audio
Stereo Speaker Stereo Headphone
Microphone Touch Screen Controller
To Battery Fuel Gauge
Figure C2. PDA Platform
The link distance testing was done using typical ASDL3212unitswithSMC'sFDC37C669andFDC37N769Super I/O controllers. An IR link distance of up to 50 cm was demonstrated.
4
Appendix D: Window Design for ASDL-3212 Window Dimension
OPAQUE MATERIAL IR Transparent Window
Y
IR Transparent Window
X K
OPAQUE MATERIAL
Z
A
D
Figure D1. Window Design for ASDL-3212
To ensure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cones angles are met without vignetting.The maximum dimensions minimize theeffectsofstraylight.Theminimumsizecorresponds to a cone angle of 300 and the maximum size correspondstoaconeangleof600. InfigureD1,Xisthewidthofthewindow,Yistheheight ofthewindowandZisthedistancefromtheASDL-3212 tothebackofthewindow.Thedistancefromthecenter of the LED lens to the center of the photodiode lens, K, is5.1mm.Theequationsforcomputingthewindowdimensionsareasfollows: X=K+2*(Z+D)*tanA Y=2*(Z+D)*tanA
The above equations assume that the thickness of the window is negligible compared to the distance of the modulefromthebackofthewindow(Z).Iftheyarecomparable,Z'replacesZintheaboveequation.Z'isdefined as Z'=Z+t/n where`t'isthethicknessofthewindowand`n'istherefractiveindexofthewindowmaterial. The depth of the LED image inside the ASDL-3212, D, is 4.32mm.`A'istherequiredhalfangleforviewing.ForIrDA compliance, the minimum is 150 and the maximum is 300. Assuming the thickness of the window to be negligible, the equations result in the following table and figures:
5
Module Depth
Aperture Width (x, mm) (z) mm 0 2 3 4 5 6 7 8 9 Max 0.09 .24 2.40 3.55 4.7 5.86 7.02 8.7 9.33 20.48 min 7.42 7.95 8.49 9.02 9.56 0.09 0.63 .7 .70 2.24 Aperture height (y, mm) Max 4.99 6.4 7.30 8.45 9.6 0.76 .92 3.07 4.23 5.38 Min 2.32 2.85 3.39 3.92 4.46 4.99 5.53 6.07 6.60 7.4
Therecommendedminimumaperturewidthandheight isbasedontheassumptionthatthecenterofthewindow and the center of the module are the same. It is recommended that the tolerance for assembly be considered as well.The minimum window size which will take into accountoftheassemblytoleranceisdefinedas: X (min + assembly tolerance) = Xmin + 2*(assembly tolerance)(Dimensionsareinmm) Y (min + assembly tolerance) = Ymin + 2*(assembly tolerance)(Dimensionsareinmm)
Window Material
Almost any plastic material will work as a window material. Polycarbonate is recommended. The surface finish of the plastic should be smooth, without any texture. An IR filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. Light loss should be measured at 885 nm. Therecommendedplasticmaterialsforuseasacosmetic windowareavailablefromGeneralElectricPlastics.
25 20 Aperture Width (x) mm 15 10 5 0
Xmax Xmin
Recommended Plastic Materials:
Material # Lexan 4 Lexan 920A Lexan 940A
0 1 2 3 4 5 6 Module Depth (z) mm 7 8 9
Haze 88% 85% 85% % % %
Refractive Index .586 .586 .586
Note:920Aand940Aaremoreflameretardantthan141.
RecommendedDye:Violet#21051(IRtransmissantabove 625mm)
Figure D2. Aperture Height (x) vs. Module Depth (z)
18 16 Aperture Height (Y) mm 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 Module Depth (z) mm 7 8 9
Shape of the Window
From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiationpatternoftheLED,orthereceivepatternofthe photodiode.Ifthewindowmustbecurvedformechanicalorindustrialdesignreasons,placethesamecurveon thebacksideofthewindowthathasanidenticalradiusas thefrontside.Whilethiswillnotcompletelyeliminatethe lenseffectofthefrontcurvedsurface,itwillsignificantly reducetheeffects.Theamountofchangeintheradiation pattern is dependent upon the material chosen for the window,theradiusofthefrontandbackcurves,andthe distance from the back surface to the transceiver. Once theseitemsareknown,alensdesigncanbemadewhich will eliminate the effect of the front surface curve. The followingdrawingsshowtheeffectsofacurvedwindow ontheradiationpattern.Inallcases,thecenterthickness ofthewindowis1.5mm,thewindowismadeofpolycarbonate plastic, and the distance from the transceiver to thebacksurfaceofthewindowis3mm.
Ymax Ymin
Figure D3. Aperture Height (y) vs. Module Depth (z)
6
Flat Window, (First Choice)
Curved Front and Back, (Second Choice)
Curved Front, Flat Back, (Do not use)
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limited. All rights reserved. AV02-0055EN - January 3, 2007

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