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16-Lane 4-Port Gen2 PCI Express(R) Switch
(R)
89HPES16T4G2 Data Sheet
Advance Information*
Device Overview
The 89HPES16T4G2 is a member of IDT's PRECISETM family of PCI Express(R) switching solutions. The PES16T4G2 is a 16-lane, 4-port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides connectivity and switching functions between a PCI Express upstream port and up to three downstream ports and supports switching between downstream ports.
Features
Block Diagram
4-Port Switch Core / 16 PCI Express Lanes
Frame Buffer Route Table Port Arbitration Scheduler
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Multiplexer / Demultiplexer
Phy Logical Layer
Multiplexer / Demultiplexer
Phy Logical Layer
Multiplexer / Demultiplexer
Phy Logical Layer
Multiplexer / Demultiplexer
Phy Logical Layer
SerDes
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
(Port 4)
(Port 6)
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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(c) 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice
September 4, 2007
DSC 6928
Advance Information
High Performance PCI Express Switch - Sixteen 5 Gbps Gen2 PCI Express lanes - Four switch ports * One x4 upstream port * Three x4 downstream ports - Low latency cut-through switch architecture - Support for Max Payload Size up to 2048 bytes - One virtual channel - Eight traffic classes - PCI Express Base Specification Revision 2.0 compliant
Flexible Architecture with Numerous Configuration Options - Automatic per port link width negotiation to x4, x2 or x1 - Automatic lane reversal on all ports - Automatic polarity inversion - Ability to load device configuration from serial EEPROM Legacy Support - PCI compatible INTx emulation - Bus locking Highly Integrated Solution - Incorporates on-chip internal memory for packet buffering and queueing - Integrates sixteen 5 Gbps embedded SerDes with 8b/10b encoder/decoder (no separate transceivers needed) * Receive equalization (RxEQ) Reliability, Availability, and Serviceability (RAS) Features - Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) - Supports ECRC and Advanced Error Reporting - Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O - Compatible with Hot-Plug I/O expanders used on PC motherboards - Supports Hot-Swap
IDT 89HPES16T4G2 Data Sheet
Product Description Utilizing standard PCI Express interconnect, the PES16T4G2 provides the most efficient fan-out solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 16 GBps (128 Gbps) of aggregated, full-duplex switching capacity through 16 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0. The PES16T4G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 2.0. The PES16T4G2 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded processors with limited connectivity.
The PES16T4G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES16T4G2, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES16T4G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1.
Bit 1 2 3 4 5 6 7
Slave SMBus Address SSMBADDR[1] SSMBADDR[2] SSMBADDR[3] 0 SSMBADDR[5] 1 1
Master SMBus Address MSMBADDR[1] MSMBADDR[2] MSMBADDR[3] MSMBADDR[4] 1 0 1
Table 1 Master and Slave SMBus Address Assignment
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*Notice: The information in this document is subject to change without notice
September 4, 2007
Advance Information
Power Management - Utilizes advanced low-power design techniques to achieve low typical power consumption - Support PCI Express Power Management Interface specification (PCI-PM 2.0) - Unused SerDes are disabled. - Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state Testability and Debug Features - Built in Pseudo-Random Bit Stream (PRBS) generator - Numerous SerDes test modes - Ability to read and write any internal register via the SMBus - Ability to bypass link training and force any link into any mode - Provides statistics and performance counters Sixteen General Purpose Input/Output Pins - Each pin may be individually configured as an input or output - Each pin may be individually configured as an interrupt input - Some pins have selectable alternate functions Packaged in a 23mm x 23mm, 288-ball BGA with 1mm ball spacing
Processor
Processor
North Bridge
Memory Memory Memory Memory
x4
PES16T4G2
x4
PCI Express Slot
x4
I/O 10GbE
x4
I/O 10GbE I/O SATA I/O SATA
Figure 2 I/O Expansion Application
SMBus Interface
IDT 89HPES16T4G2 Data Sheet
As shown in Figure 2, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 2(a), the master and slave SMBuses are tied together and the PES16T4G2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES16T4G2 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES16T4G2 may be configured to operate in a split configuration as shown in Figure 2(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES16T4G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM.
PES16T4G2
Processor SMBus Master
Serial EEPROM
...
Other SMBus Devices
PES16T4G2
Processor SMBus Master
...
Other SMBus Devices
SSMBCLK SSMBDAT MSMBCLK MSMBDAT
SSMBCLK SSMBDAT MSMBCLK MSMBDAT
Serial EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 2 SMBus Interface Configuration Examples
Hot-Plug Interface The PES16T4G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES16T4G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES16T4G2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES16T4G2. In response to an I/O expander interrupt, the PES16T4G2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES16T4G2 provides 16 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
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Advance Information
IDT 89HPES16T4G2 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES16T4G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Note: In the PES16T4G2, the three downstream ports are labeled port 2, port 4, and port 6.
Signal PE0RP[3:0] PE0RN[3:0] PE0TP[3:0] PE0TN[3:0] PE2RP[3:0] PE2RN[3:0] PE2TP[3:0] PE2TN[3:0] PE4RP[3:0] PE4RN[3:0] PE4TP[3:0] PE4TN[3:0] PE6RP[3:0] PE6RN[3:0] PE6TP[3:0] PE6TN[3:0] PEREFCLKP[0] PEREFCLKN[0]
Type I O I O I O I O I
Name/Description PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port. PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for port 6. PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz This pin should be static and not change following the negation of PERSTN. Table 2 PCI Express Interface Pins
REFCLKM
I
Signal MSMBADDR[4:1] MSMBCLK MSMBDAT
Type I I/O I/O
Name/Description Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Table 3 SMBus Interface Pins (Part 1 of 2)
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PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4.
IDT 89HPES16T4G2 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Type I I/O I/O Name/Description Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins (Part 2 of 2)
Signal GPIO[0]
Type I/O
Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2.
GPIO[2]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O expander interrupt 0 input. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 4 General Purpose I/O Pins (Part 1 of 2)
GPIO[3] GPIO[4]
I/O I/O
GPIO[5] GPIO[6] GPIO[7]
I/O I/O I/O
GPIO[9] GPIO[10]
I/O I/O
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GPIO[1]
I/O
General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4.
IDT 89HPES16T4G2 Data Sheet Signal GPIO[11] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 4 General Purpose I/O Pins (Part 2 of 2)
GPIO[12] GPIO[13] GPIO[14] GPIO[15]
I/O I/O I/O I/O
Signal CCLKDS
Type I
Name/Description Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each downstream port's PCIELSTS register. Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Fundamental Reset. Assertion of this signal resets all logic inside PES16T4G2 and initiates a PCI Express fundamental reset. Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES16T4G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. Switch Mode. These configuration pins determine the PES16T4G2 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN. Table 5 System Pins
CCLKUS
I
MSMBSMODE
I
PERSTN RSTHALT
I I
SWMODE[2:0]
I
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IDT 89HPES16T4G2 Data Sheet
Signal JTAG_TCK
Type I
Name/Description JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins
JTAG_TDI JTAG_TDO
I O
JTAG_TMS JTAG_TRST_N
I I
Signal REFRES0
Type I/O
Name/Description Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. Port 2 External Reference Resistor. Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. Port 4 External Reference Resistor. Provides a reference for the Port 4 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. Port 6 External Reference Resistor. Provides a reference for the Port 6 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Analog Power. Serdes analog power supply (1.0V). PCI Express Analog High Power. Serdes analog power supply (2.5V). PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). Ground.
REFRES2
I/O
REFRES4
I/O
REFRES6
I/O
VDDCORE VDDI/O VDDPEA VDDPEHA VDDPETA VSS
I I I I I I
Table 7 Power, Ground, and SerDes Resistor Pins
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IDT 89HPES16T4G2 Data Sheet
Pin Characteristics
Note: Some input pads of the PES16T4G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
Function PCI Express Interface
Pin Name PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PE6RN[3:0] PE6RP[3:0] PE6TN[3:0] PE6TP[3:0] PEREFCLKN[0] PEREFCLKP[0] REFCLKM
Type I I O O I I O O I I O O I I O O I I I I I/O I/O I I/O I/O I/O I I I I I I
Buffer CML
I/O Type Serial Link
Internal Resistor1
Notes
Diff. Clock Input LVTTL LVTTL Input Input STI2 STI Input STI STI LVTTL LVTTL STI, High Drive Input Input Input STI Input Input pull-down pull-down pull-up pull-up pull-up pull-down pull-up pull-down pull-up
Refer to Table 9
SMBus
MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT
pull-up on board pull-up on board pull-up on board pull-up on board
General Purpose I/O System Pins
GPIO[15:0] CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0]
Table 8 Pin Characteristics (Part 1 of 2)
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IDT 89HPES16T4G2 Data Sheet Function EJTAG / JTAG Pin Name JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N SerDes Reference Resistors REFRES0 REFRES2 REFRES4 REFRES6
1. Internal 2.
Type I I O I I I/O I/O I/O I/O
Buffer LVTTL
I/O Type STI STI STI STI
Internal Resistor1 pull-up pull-up pull-up pull-up
Notes
Analog
Table 8 Pin Characteristics (Part 2 of 2)
resistor values under typical operating conditions are 92K for pull-up and 90K for pull-down. Schmitt Trigger Input (STI).
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IDT 89HPES16T4G2 Data Sheet
Logic Diagram -- PES16T4G2
Reference Clocks Reference Clock Frequency Selection PCI Express Switch SerDes Input Port 0
PEREFCLKP[0] PEREFCLKN[0] REFCLKM PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PE2RP[0] PE2RN[0] PE2RP[3] PE2RN[3] PE4RP[0] PE4RN[0] PE4RP[3] PE4RN[3] PE6RP[0] PE6RN[0] PE6RP[3] PE6RN[3]
4
PE0TP[0] PE0TN[0]
PE0TP[3] PE0TN[3] PE2TP[0] PE2TN[0] PE2TP[3] PE2TN[3] PE4TP[0] PE4TN[0] PE4TP[3] PE4TN[3] PE6TP[0] PE6TN[0] PE6TP[3] PE6TN[3]
16
PCI Express Switch SerDes Output Port 0
...
PCI Express Switch SerDes Input Port 2
...
PCI Express Switch SerDes Output Port 2
...
PCI Express Switch SerDes Input Port 6
PES16T4G2
PCI Express Switch SerDes Output Port 6 General Purpose I/O
Master SMBus Interface
MSMBADDR[4:1] MSMBCLK MSMBDAT
GPIO[15:0]
Slave SMBus Interface
SSMBADDR[5,3:1] SSMBCLK SSMBDAT
4
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N REFRES0 REFRES2 REFRES4 REFRES6
JTAG Pins
System Pins
MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN SWMODE[2:0]
SerDes Reference Resistors
3
VDDCORE VDDI/O VDDPEA VDDPEHA VSS VDDPETA
Power/Ground
Figure 3 PES16T4G2 Logic Diagram
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PCI Express Switch SerDes Input Port 4
...
PCI Express Switch SerDes Output Port 4
...
...
...
...
IDT 89HPES16T4G2 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter RefclkFREQ TC-RISE TC-FALL VIH VIL VCROSS VCROSS-DELTA VRB TSTABLE TPERIOD-AVG TPERIOD-ABS TCC-JITTER VMAX VMIN Duty Cycle Rise/Fall Matching ZC-DC
1.
Description Input reference clock frequency range Rising edge rate Falling edge rate Differential input high voltage Differential input low voltage Absolute single-ended crossing point voltage Variation of VCROSS over all rising clock edges Ring back voltage margin Time before VRB is allowed Average clock period accuracy Absolute period, including spread-spectrum and jitter Cycle to cycle jitter Absolute maximum input voltage Absolute minimum input voltage Duty cycle Single ended rising Refclk edge rate versus falling Refclk edge rate Clock source output DC impedance
Condition
Min 100
Typical
Max 1251 4 4
Unit MHz V/ns V/ns mV
Differential Differential Differential Differential Single-ended Single-ended Differential Differential
0.6 0.6 +150
-150 +250 +550 +140 -100 500 -300 9.847 2800 10.203 150 +1.15 -0.3 40 20 40 60 60 +100
mV mV mV mV ps ppm ns ps V V % %
Table 9 Input Clock Requirements
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
AC Timing Characteristics
Gen 1 Min1 Typ1 Max1 Min1 Gen 2 Typ1 Max1
Parameter PCIe Transmit UI TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER
Description
Units
Unit Interval Minimum Tx Eye Width Maximum time between the jitter median and maximum deviation from the median TX Rise/Fall Time: 20% - 80% Minimum time in idle
399.88 0.75
400
400.12
199.94 0.75
200
200.06
ps UI UI
0.125 0.125 20 0.15 20
TTX-RISE, TTX-FALL TTX- IDLE-MIN
UI UI
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
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IDT 89HPES16T4G2 Data Sheet Gen 1 Min1 Typ1 Max1 8 8 1.3 NA HPF: 1.5MHz NA NA 0.9 HPF: 1.0MHz 0.15 0.1 Min1 Gen 2 Typ1 Max1 8 8 1.3
Parameter TTX-IDLE-SET-TOIDLE
Description Maximum time to transition to a valid Idle after sending an Idle ordered set Maximum time to transition from valid idle to diff data Transmitter data skew between any 2 lanes Minimum Instantaneous Lone Pulse Width Transmit Jitter Measurement Filter Transmitter Deterministic Jitter > 1.5MHz Bandwidth Rise/Fall Time Differential Mismatch
Units ns ns ns UI MHz UI UI
TTX-IDLE-TO-DIFFDATA
TTX-SKEW TMIN-PULSED TMEAS-HPF TTX-HF-DJ-DD TRF-MISMATCH PCIe Receive UI TRX-EYE (with jitter) TRX-EYE-MEDIUM TO
MAX JITTER
Unit Interval Minimum Receiver Eye Width (jitter tolerance) Max time between jitter median & max deviation Lane to lane input skew 1.5 -- 100 MHz RMS jitter Maximum tolerable DJ by the receiver 10 KHz to 1.5 MHz RMS jitter Minimum receiver instantaneous eye width
399.88 0.4
400
400.12
199.94 0.4
200.06
ps
0.3 20 NA NA NA NA 0.6 8 4.2 8.8 4.2
UI ns ps ps ps UI
TRX-SKEW TRX-HF-RMS TRX-HF-DJ-DD TRX-LF-RMS TRX-MIN-PULSE
1.
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0
Signal GPIO GPIO[15:0]1
1. 2.
Symbol
Reference Min Max Unit Edge
Timing Diagram Reference
Tpw2
None
50
--
ns
Table 11 GPIO AC Timing Characteristics
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. The values for this symbol were determined by calculation, not by testing.
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UI
IDT 89HPES16T4G2 Data Sheet
Signal JTAG JTAG_TCK
Symbol
Reference Edge
Min
Max
Unit
Timing Diagram Reference
Tper_16a Thigh_16a, Tlow_16a
none
50.0 10.0
-- 25.0 -- -- 20 20 --
ns ns ns ns ns ns ns
See Figure 4.
JTAG_TMS1, JTAG_TDI JTAG_TDO
Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2
JTAG_TCK rising
2.4 1.0
JTAG_TCK falling
-- --
JTAG_TRST_N
1.
none
25.0
Table 12 JTAG AC Timing Characteristics
2.
The values for this symbol were determined by calculation, not by testing.
Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 4 JTAG AC Timing Waveform Tdz_16c Tper_16a
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The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
IDT 89HPES16T4G2 Data Sheet
Recommended Operating Supply Voltages
Symbol VDDCORE VDDI/O VDDPEA
1 2
Parameter Internal logic supply I/O supply except for SerDes LVPECL/CML PCI Express Analog Power PCI Express Analog High Power PCI Express Transmitter Analog Voltage Common ground
Minimum 0.9 3.135 0.95 2.25 0.95 0
Typical 1.0 3.3 1.0 2.5 1.0 0
Maximum 1.1 3.465 1.1 2.75 1.1 0
Unit V V V V V V
VDDPEHA VDDPETA VSS
1.
2.
Table 13 PES16T4G2 Operating Voltages VDDPEA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value.
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence requirements for the various operating supply voltages. The power-down sequence can occur in any order.
Recommended Operating Temperature
Grade Commercial Temperature 0C to +70C Ambient
Table 14 PES16T4G2 Operating Temperatures
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Power-Up/Power-Down Sequence
IDT 89HPES16T4G2 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below).
Number of active Lanes per Port
Core Supply Typ 1.0V Max 1.1V
PCIe Analog Supply Typ 1.0V Max 1.1V
PCIe Analog High Supply Typ 2.5V Max 2.75V
PCIe Termination Supply Typ 1.0V Max 1.1V
I/O Supply Typ 3.3V Max 3.465V
Total Typ Power Max Power
4/4/4/4
mA Watts
852 0.85 TBD TBD
1136 1.25 TBD TBD
518 0.51 TBD TBD
688 0.75 TBD TBD
270 0.67 TBD TBD
361 0.99 TBD TBD
362 0.36 TBD TBD
483 0.53 TBD TBD
10 0.03 TBD TBD
10 .034 TBD TBD
2.4W
3.5W
4/4/1/1
mA Watts
Thermal Considerations
This section describes thermal considerations for the PES16T4G2 (23mm2 SBGA288 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES16T4G2 switch.
Symbol TJ(max) TA(max) JC P
Parameter Junction Temperature Ambient Temperature Thermal Resistance, Junction-to-Case Power Dissipation of the Device
Value 125 70 1.1 3.5
Units
oC oC oC/W
Conditions Maximum Maximum Maximum
Watts
Table 16 Thermal Specifications for PES16T4G2, 23x23 mm SBGA288 Package
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 16. Consequently, the effective junction to ambient thermal resistance (JA) for the worst case scenario must be maintained below the value determined by the formula: JA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired JA becomes a known entity to the system designer. How to achieve the desired JA is left up to the board or system designer, but in general, it can be achieved by adding the effects of JC (value provided in Table 16), thermal resistance of the chosen adhesive (CS), that of the heat sink (SA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios.
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Table 15 PES16T4G2 Power Consumption
IDT 89HPES16T4G2 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing.
Gen 1 Min1 Serial Link PCIe Transmit VTX-DIFFp-p VTX-DIFFp-p-LOW VTX-DE-RATIO3.5dB
I/O Type
Parameter
Description
Gen 2 Max1 Min1 Typ1 Max1
Unit
Conditions
Typ1
Differential peak-to-peak output voltage Low-Drive Differential Peak to Peak Output Voltage De-emphasized differential output voltage De-emphasized differential output voltage DC Common mode voltage RMS AC peak common mode output voltage Abs delta of DC common mode voltage between L0 and idle Abs delta of DC common mode voltage between D+ and DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss
800 400 -3 NA 0
1200 1200 -4
800 400 -3.0 -5.5 -3.5 -6.0
1200 1200 -4.0 -6.5 3.6
mV mV dB dB V mV
6.0dB
VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta
3.6 20 100 25 20 600
0
100 25 20 600 10dB: 0.05 1.25GHz 8dB: 1.25 2.5GHz 6
mV mV mV mV dB
VTX-CM-DC-linedelta
VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF
10
RLTX-CM ZTX-DIFF-DC VTX-CM-ACpp VTX-DC-CM
Transmitter Common Mode Return loss DC Differential TX impedance Peak-Peak AC Common Transmit Driver DC Common Mode Voltage
6 80 100 NA 0 3.6 600 0 120
dB mV V mV
120 100 3.6 600
VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detection ITX-SHORT Transmitter Short Circuit Current Limit 0
90
90
mA
Table 17 DC Electrical Characteristics (Part 1 of 3)
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VTX-DE-RATIO-
IDT 89HPES16T4G2 Data Sheet Gen 1 Min1 Serial Link (cont.) PCIe Receive VRX-DIFFp-p RLRX-DIFF Differential input voltage (peakto-peak) Receiver Differential Return Loss 175 10 1200 120 1200 10dB: 0.05 1.25GHz 8dB: 1.25 2.5GHz 6 100 50 350k 50k 120 60 Refer to return loss spec 40 60 50k 50k mV dB Typ1 Max1 Min1 Gen 2 Typ1 Max1 Unit Conditions
I/O Type
Parameter
Description
RLRX-CM ZRX-DIFF-DC ZRX--DC ZRX-COMM-DC ZRX-HIGH-IMPDC-POS
Receiver Common Mode Return Loss Differential input impedance (DC) DC common mode impedance Powered down input common mode impedance (DC) DC input CM input impedance for V>0 during reset or power down DC input CM input impedance for V<0 during reset or power down Electrical idle detect threshold Receiver AC common-mode peak voltage
6 80 40 200k
dB
ZRX-HIGH-IMPDC-NEG
1.0k
1.0k
VRX-IDLE-DETDIFFp-p
65
175 150
65
175 150
mV mV VRX-CM-ACp
VRX-CM-ACp PCIe REFCLK CIN Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) Input IOL IOH IOL IOH VIL VIH VIL VIH
Input Capacitance
1.5
--
1.5
--
pF
-- -- -- -- -0.3 2.0 -0.3 2.0
2.5 -5.5 12.0 -20.0 -- -- -- --
-- -- -- -- 0.8 VDDI/O + 0.5 0.8 VDDI/O + 0.5
-- -- -- -- -0.3 2.0 -0.3 2.0
2.5 -5.5 12.0 -20.0 -- -- -- --
-- -- -- -- 0.8 VDDI/O + 0.5 0.8 VDDI/O + 0.5
mA mA mA mA V V V V
VOL = 0.4v VOH = 1.5V VOL = 0.4v VOH = 1.5V -- -- -- --
Table 17 DC Electrical Characteristics (Part 2 of 3)
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IDT 89HPES16T4G2 Data Sheet Gen 1 Min1 Capacitance Leakage CIN Inputs I/OLEAK W/O Pull-ups/downs I/OLEAK WITH Pull-ups/downs
1.
I/O Type
Parameter
Description
Gen 2 Max1 8.5 + 10 + 10 + 80 Min1 -- -- -- -- Typ1 -- -- -- -- Max1 8.5 + 10 + 10 + 80
Unit
Conditions
Typ1 -- -- -- --
-- -- -- --
pF
-- VDDI/O (max) VDDI/O (max) VDDI/O (max)
A A A
Table 17 DC Electrical Characteristics (Part 3 of 3)
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0.
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IDT 89HPES16T4G2 Data Sheet
Package Pinout -- 288-BGA Signal Pinout for PES16T4G2
The following table lists the pin numbers and signal names for the PES16T4G2 device.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 VSS VSS VDDI/O VDDCORE PE6RP03 PE6RN03 VDDCORE PE6RP02 PE6RN02 VDDCORE VSS VSS VDDCORE PE6RP01 PE6RN01 VDDCORE PE6RP00 PE6RN00 VDDI/O GPIO_15 GPIO_14 VSS SSMBADDR_5 SSMBADDR_3 SSMBADDR_2 SSMBADDR_1 MSMBCLK MSMBADDR_3 MSMBADDR_2 MSMBADDR_1 VDDPEHA NC REFRES6 VSS Function Alt Pin B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 Function VDDPEHA VSS VSS VDDPEHA VSS VSS VSS REFCLKM GPIO_13 VSS SSMBCLK SSMBDAT MSMBSMODE MSMBDAT MSMBADDR_4 PE6TN03 PE6TP03 VDDI/O PE6TN02 PE6TP02 VSS VDDPEHA VSS VSS PE6TN01 PE6TP01 VDDPEHA PE6TN00 PE6TP00 GPIO_10 GPIO_12 VDDI/O VSS VDDI/O Alt Pin D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E19 E20 E21 E22 F1 F2 F3 F4 F19 F20 Function PE2TP00 VDDPETA VDDPEA VSS VDDPETA VDDPEA VSS VDDPETA VDDPEA VSS VDDPEA VSS VDDPETA VDDPEA VSS VDDCORE VDDPETA GPIO_09 GPIO_11 VDDCORE PE2RN00 VSS PE2TN00 VDDCORE VDDPEA GPIO_07 GPIO_08 PE4RP03 PE2RP00 VSS VDDPEHA VSS VSS PE4TN03 1 1 Alt Pin F21 F22 G1 G2 G3 G4 G19 G20 G21 G22 H1 H2 H3 H4 H19 H20 H21 H22 J1 J2 J3 J4 J19 J20 J21 J22 K1 K2 K3 K4 K19 K20 K21 K22 Function GPIO_06 PE4RN03 VDDCORE VDDPEHA PE2TP01 VDDPEA VDDPETA PE4TP03 GPIO_05 VSS VSS PE2TN01 VDDPETA VDDPEA VDDI/O GPIO_04 PE4RP02 PE2RP01 VSS VSS VSS VSS PE4TN02 VDDPEHA PE4RN02 VDDCORE VDDPEHA VSS VDDPEA VDDPETA PE4TP02 NC VDDCORE 1 PE2RN01 Alt
Table 18 PES16T4G2 288-pin Signal Pin-Out (Part 1 of 2)
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IDT 89HPES16T4G2 Data Sheet Pin L1 L2 L3 L4 L19 L20 L21 L22 M1 M2 M3 M4 M19 M20 M21 M22 N1 N2 N3 N4 N19 N20 N21 N22 P1 P2 P3 P4 P19 P20 P21 P22 R1 R2 R3 R4 R19 R20 VSS VSS VDDPEHA VSS VDDPEA VSS REFRES4 VSS VSS REFRES2 VSS VDDPEA VSS VDDPEHA VSS VSS VDDCORE NC PE2TP02 VDDPETA VDDPEA VSS VDDPEHA VDDCORE PE2RN02 VDDPEHA PE2TN02 VSS VSS VSS VSS PE4RP01 PE2RP02 VDDI/O VDDPETA VDDPEA VDDPETA PE4TN01 Function Alt Pin R21 R22 T1 T2 T3 T4 T19 T20 T21 T22 U1 U2 U3 U4 U19 U20 U21 U22 V1 V2 V3 V4 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 VSS PE4RN01 VDDCORE JTAG_TRST_N PE2TP03 JTAG_TDO VDDPEA PE4TP01 VDDPEHA VDDCORE PE2RN03 JTAG_TMS PE2TN03 VSS VSS VDDPEHA VSS PE4RP00 PE2RP03 VSS VSS VDDPEA VDDCORE PE4TN00 VSS PE4RN00 JTAG_TCK VSS VSS VDDPETA VDDCORE VSS VDDPEA VDDPETA VSS VDDPEA VSS VDDPEA Function Alt Pin W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 Function VDDPETA VSS VDDPEA VDDPETA VSS VDDPEA VDDPETA PE4TP00 VDDI/O VSS JTAG_TDI VDDI/O VDDI/O PE0TP00 PE0TN00 VDDPEHA PE0TP01 PE0TN01 VSS VSS VDDPEHA VSS PE0TP02 PE0TN02 VDDI/O PE0TP03 PE0TN03 SWMODE_1 PERSTN RSTHALT GPIO_03 GPIO_02 VSS VSS VSS VSS VSS VSS 1 Alt Pin AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 Function VDDPEHA VSS VSS VDDPEHA VSS REFRES0 NC VDDPEHA CCLKUS CCLKDS SWMODE_0 SWMODE_2 NC NC GPIO_00 GPIO_01 VSS VSS VSS VDDCORE PE0RN00 PE0RP00 VDDCORE PE0RN01 PE0RP01 VDDCORE PEREFCLKP0 PEREFCLKN0 VDDCORE PE0RN02 PE0RP02 VDDCORE PE0RN03 PE0RP03 VSS VDDI/O VSS VSS 1 1 Alt
Table 18 PES16T4G2 288-pin Signal Pin-Out (Part 2 of 2)
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IDT 89HPES16T4G2 Data Sheet
Alternate Signal Functions
Pin AA21 AA22 Y22 H21 E20 D21 GPIO GPIO_00 GPIO_01 GPIO_02 GPIO_04 GPIO_07 GPIO_11 Alternate P2RSTN P4RSTN IOEXPINTN0 IOEXPINTN2 GPEN P6RSTN
Table 19 PES16T4G2 Alternate Signal Functions
No Connection Pins
NC Pins B10 K21 N2 AA13 AA19 AA20 Table 20 PES16T4G2 No Connection Pins
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IDT 89HPES16T4G2 Data Sheet
Power Pins
VDDCore A4 A7 A10 A13 A16 D18 D22 E4 G1 K1 K22 N1 N22 T1 T22 V19 W5 AB4 AB7 AB10 AB13 AB16 Table 21 PES16T4G2 Power Pins VDDI/O A3 A19 C8 C22 D2 H20 R2 W21 Y2 Y3 Y15 AB20 VDDPEA D5 D8 D11 D13 D16 E19 G4 H19 K4 L19 M4 N19 R4 T19 V4 W7 W10 W12 W15 W18 VDDPEHA B9 B13 B16 C12 C17 F3 G2 J21 K2 L3 M20 N21 P2 T21 U20 Y6 Y11 AA7 AA10 AA14 VDDPETA D4 D7 D10 D15 D19 G19 H4 K19 N4 R3 R19 W4 W8 W13 W16 W19
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IDT 89HPES16T4G2 Data Sheet
Ground Pins
Vss A1 A2 A11 A12 A22 B12 B14 B15 B17 B18 B19 B22 C11 C13 C14 D1 D6 D9 D12 D14 Vss D17 E2 F2 F4 F19 G22 H2 J2 J3 J4 J19 K3 L1 L2 L4 L20 L22 M1 M3 M19 Vss M21 M22 N20 P4 P19 P20 P21 R21 U4 U19 U21 V2 V3 V21 W2 W3 W6 W9 W11 W14 Vss W17 W22 Y9 Y10 Y12 AA1 AA2 AA3 AA4 AA5 AA6 AA8 AA9 AA11 AB1 AB2 AB3 AB19 AB21 AB22
Table 22 PES16T4G2 Ground Pins
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IDT 89HPES16T4G2 Data Sheet
Signals Listed Alphabetically
Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE No Connection PE0RN00 PE0RN01 PE0RN02 I I I AB5 AB8 AB14 I/O Type I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O I I I I I I I/O I/O I Location AA16 AA15 AA21 AA22 Y22 Y21 H21 G21 F21 E20 General Purpose Input/Output Signal Category System
D20 C20 D21 C21 B21 A21 A20 W1 Y1 T4 U2 T2 B8 B7 B6 C5 B5 C4 C3 See Table 20 PCI Express System SMBus JTAG
Table 23 89PES16T4G2 Alphabetical Signal List (Part 1 of 4)
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E21
IDT 89HPES16T4G2 Data Sheet Signal Name PE0RN03 PE0RP00 PE0RP01 PE0RP02 PE0RP03 PE0TN00 PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RN01 PE2RN02 PE2RN03 PE2RP00 PE2RP01 PE2RP02 PE2RP03 PE2TN00 PE2TN01 PE2TN02 PE2TN03 PE2TP00 PE2TP01 PE2TP02 PE2TP03 PE4RN00 PE4RN01 PE4RN02 PE4RN03 PE4RP00 PE4RP01 PE4RP02 I/O Type I I I I I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I I I Location AB17 AB6 AB9 AB15 AB18 Y5 Y8 Y14 Y17 Y4 Y7 Y13 Signal Category PCI Express (Cont.)
E1 H1 P1 U1 F1 J1 R1 V1 E3 H3 P3 U3 D3 G3 N3 T3 V22 R22 J22 F22 U22 P22 H22
Table 23 89PES16T4G2 Alphabetical Signal List (Part 2 of 4)
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Y16
IDT 89HPES16T4G2 Data Sheet Signal Name PE4RP03 PE4TN00 PE4TN01 PE4TN02 PE4TN03 PE4TP00 PE4TP01 PE4TP02 PE4TP03 PE6RN00 PE6RN01 PE6RN02 PE6RN03 PE6RP00 PE6RP01 PE6RP02 PE6RP03 PE6TN00 PE6TN01 PE6TN02 PE6TN03 PE6TP00 PE6TP01 PE6TP02 PE6TP03 PEREFCLKN0 PEREFCLKP0 PERSTN REFCLKM REFRES0 REFRES2 REFRES4 REFRES6 RSTHALT I/O Type I O O O O O O O O I I I I I I I I O O O O O O O O I I I I I/O I/O I/O I/O I Location E22 V20 R20 J20 F20 W20 T20 K20 G20 A18 A15 A9 Signal Category PCI Express (Cont.)
A17 A14 A8 A5 C18 C15 C9 C6 C19 C16 C10 C7 AB12 AB11 Y19 B20 AA12 M2 L21 B11 Y20 System System PCI Express SerDes Reference Resistors
Table 23 89PES16T4G2 Alphabetical Signal List (Part 3 of 4)
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A6
IDT 89HPES16T4G2 Data Sheet Signal Name SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 VDDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA VSS I/O Type I I I I I/O I/O I I I Location B4 B3 B2 B1 C1 C2 AA17 Y18 AA18 See Table 21 for a listing of power pins. System SMBus Signal Category SMBus
See Table 22 for a listing of ground pins. Table 23 89PES16T4G2 Alphabetical Signal List (Part 4 of 4)
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IDT 89HPES16T4G2 Data Sheet
PES16T4G2 Pinout -- Top View
1 A B C D E F G H J K L M N P R T U V W Y AA AB 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 A B C
X
X
X
X
X
D E F
X X X
G H K L M J
X X X
N P R T U V
X
X
X
X
X
W Y AA AB
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 VDDPETA (Transmitter Power) VDDPEA (Analog Power) VDDPEHA (High Analog Power) Signals No Connect
VDDCore (Power) VDDI/O (Power) Vss (Ground)
X
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IDT 89HPES16T4G2 Data Sheet
PES16T4G2 Package Drawing -- 288-Pin BX288/BXG288
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IDT 89HPES16T4G2 Data Sheet
PES16T4G2 Package Drawing -- Page Two
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IDT 89HPES16T4G2 Data Sheet
Revision History
May 4, 2007: Initial publication of Advanced data sheet. September 4, 2007: Added values to Table 16, Thermal Specifications.
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IDT 89HPES16T4G2 Data Sheet
Ordering Information
NN Product Family A Operating Voltage AAA Device Family NNAN Product Detail AN AA AAA A Legend A = Alpha Character N = Numeric Character
Generation Device Revision Series
Package Temp Range
Blank BX BXG ZA G2 16T4 PES
Commercial Temperature (0C to +70C Ambient) BX288 288-ball SBGA BXG288 288-ball SBGA, Green ZA revision Generation 2 16-lane, 4-port PCI Express Switch
H 89
1.0V +/- 0.1V Core Voltage Serial Switching Product
Valid Combinations
89HPES16T4G2ZABX 89HPES16T4G2ZABXG 288-ball SBGA package, Commercial Temperature 288-ball Green SBGA package, Commercial Temperature
(R)
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