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Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
FEATURES
* 1 differential 3.3V LVPECL output pair, 1 differential feedback output pair * Differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Output frequency range: 31.25MHz to 700MHz * Input frequency range: 31.25MHz to 700MHz * VCO range: 250MHz to 700MHz * Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 * External feedback for "zero delay" clock regeneration with configurable frequencies * Cycle-to-cycle jitter: 40ps (maximum) * Static phase offset: 50ps 150ps * 3.3V supply voltage * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8735I-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL clock generator and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The ICS8735I-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
,&6
BLOCK DIAGRAM
PLL_SEL
/1, /2, /4, /8, /16, /32, /64
PIN ASSIGNMENT
0 1 Q nQ QFB nQFB CLK nCLK MR VCC nFB_IN FB_IN SEL2 VEE nQFB QFB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nc SEL1 SEL0 VCC PLL_SEL VCCA SEL3 VCCO Q nQ
CLK nCLK
PLL
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
FB_IN nFB_IN
ICS8735I-21
20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View
SEL0 SEL1 SEL2 SEL3 MR
8735AMI-21
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4, 17 5 6 7 8 9, 10 11, 12 13 14 15 16 18 19 20 Name CLK nCLK MR VCC nFB_IN FB_IN SEL2 VEE nQFB, QFB nQ, Q VCCO SEL3 VCCA PLL_SEL SEL0 SEL1 nc Input Input Input Power Input Input Input Power Output Output Power Input Power Input Input Input Unused Type Pullup Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Q and QFB to go low and the inver ted outputs nQ Pulldown and nQFB to go high. When LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Feedback input to phase detector for regenerating clocks with "zero delay". Pullup Connect to pin 9. Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Connect to pin 10. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Negative supply pin. Differential feedback outputs. LVPECL interface levels. Differential clock outputs. LVPECL interface levels. Output supply pin. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. Pullup When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q, nQ; QFB, nQFB /1 /1 /1 /1 /2 /2 /2 /4 /4 /8 x2 x2 x2 x4 x4 x8
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 250 - 700 125 - 350 62.5 - 175 250 - 700 125 - 350 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 62.5 - 175 31.25 - 87.5 31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
8735AMI-21
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q, nQ; QFB, nQFB /4 /4 /4 /8 /8 /8 / 16 / 16 / 32 / 64 /2 /2 /4 /1 /2 /1
REV. A JANUARY 31, 2003
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Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VCC Outputs, VCCO Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 46.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 150 15 Units V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current SEL0, SEL1, SEL2, SEL3, MR PLL_SEL SEL0, SEL1, SEL2, SEL3, MR PLL_SEL VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK, FB_IN nCLK, nFB_IN CLK, FB_IN nCLK, nFB_IN Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol fIN Parameter Input Frequency CLK, nCLK Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 700 700 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol fMAX tPD tsk(o) t(O) t jit(cc) t jit() tL tR / tF Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 4, 5 Static Phase Offset; NOTE 2, 5 Cycle-to-Cycle Jitter; NOTE 5, 6 Phase Jitter; NOTE 3, 5, 6 PLL Lock Time Output Rise/Fall Time 20% to 80% 200 PLL_SEL = 0V, f 700MHz PLL_SEL = 0V PLL_SEL = 3.3V 2.8 Test Conditions Minimum Typical Maximum 700 4.9 35 200 40 65 1 700 Units MHz ns ps ps ps ps ms ps %
-100
50
odc Output Duty Cycle 47 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Phase jitter is dependent on the input source used. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crosspoints. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz.
8735AMI-21
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO = 2V VCC
Qx
SCOPE
nCLK
LVPECL
nQx
CLK
V
PP
Cross Points
V
CMR
V EE VEE = -1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
nQ, nQFB Q, QFB tCycle n
tJIT(cc) = tCycle n - tCycle n+1
tsk(o)
OUTPUT SKEW
nCLK CLK nFB_IN nFB_IN
CYCLE-TO-CYCLE JITTER
VOH VOL
nCLK
VOH
CLK
VOL t(O)
tjit(O) = t(O) -- t(O) mean = Phase Jitter t(O) mean = Static Phase Offset
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
nQ, nQFB Q, QFB
tPD
PHASE JITTER
nQ, nQFB Q, QFB
AND
STATIC PHASE OFFSET
PROPAGATION DELAY
80%
Pulse Width t
20%
PERIOD
Clock Outputs t
R
odc =
t PW t PERIOD
odc, tPW & tPERIOD
8735AMI-21
OUTPUT RISE/FALL TIME
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REV. A JANUARY 31, 2003
tCycle n + 1
80% V
SW I N G
20% t
F
Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8735I-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10 F 10
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc. TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
Zo = 50
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 5 2 Zo 5 2 Zo
FOUT Zo = 50
FIN Zo = 50 FOUT 50 50 VCC - 2V Zo = 50 3 2 Zo 3 2 Zo FIN
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 3A. LVPECL OUTPUT TERMINATION
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of the ICS8735I-21. In this example, the input is driven by an HCSL driver. The zero delay buffer is configured to operate at 155.52MHz input and 77.75MHz output. The logic control pins are configured as follows:
3.3V VCCA U1 Zo = 50 Ohm
(155.5 MHz)
VCC SEL2 R8 50 R9 50 R1 50 R2 50
Zo = 50 Ohm HCSL
VCC
RU3 1K
RU4 1K
RU5 SP
RU6 1K
RU7 SP PLL_SEL SEL0 SEL1 SEL2 SEL3 R3 50
RD3 SP
RD4 SP
RD5 1K
RD6 SP
RD7 1K
SP = Space (i.e. not intstalled)
FIGURE 4. ICS8735I-21 LVPECL BUFFER SCHEMATIC EXAMPLE
8735AMI-21
RTT
FIGURE 3B. LVPECL OUTPUT TERMINATION
SEL [3:0] = 0101; PLL_SEL = 1 The decoupling capacitors should be physically located near the power pin.
R7 10 1 2 3 4 5 6 7 8 9 10 CLK nCLK MR VCCI nFB_IN FB_IN SEL2 VEE QFB nQFB ICS8735-21 nc SEL1 SEL0 VCCI PLL_SEL VCCA SEL3 VCCO Q nQ 20 19 18 17 16 15 14 13 12 11 SEL1 SEL0 VCC PLL_SEL VCCA SEL3 VCC C11 0.01u C16 10u
VCC
Zo = 50 Ohm + Zo = 50 Ohm -
(77.75 MHz)
R4 50
LVPECL_input R5 50
Bypass capacitors located near the power pins
(U1-4) VCC (U1-17)
C2 0.1uF
R6 50
(U1-13)
C3 0.1uF
VCC=3.3V
C1 0.1uF
SEL[3:0] = 0101, Divide by 2
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc. DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5 to 7 show interface examples for the ICS8735I-21 clock input driven by the most common driver types. The input interfaces suggested here are
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 5. ICS8735I-21 CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
BY
ICS
FIGURE 6. ICS8735I-21 CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
FIGURE 7. ICS8735I-21 CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
8735AMI-21
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8735I-21. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8735I-21 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.75mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 519.75mW + 60.4mW = 580.15mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.580W * 39.7C/W = 108C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE qJA
FOR
20-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8735I-21 is: 2969
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Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
PACKAGE OUTLINE - M SUFFIX
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
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REV. A JANUARY 31, 2003
Integrated Circuit Systems, Inc.
ICS8735I-21
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR
Marking ICS8735AMI-21 ICS8735AMI-21 Package 20 Lead SOIC 20 Lead SOIC on Tape and Reel Count 38 per tube 1000 Temperature -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS8735AMI-21 ICS8735AMI-21T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8735AMI-21
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