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| HV6506 32-Channel LCD Driver with Separate Backplane Output Ordering Information Package Options Device HV6506 44-J Lead Quad Plastic Chip Carrier HV6506PJ 44 Lead Quad Plastic Gullwing HV6506PG Dice in waffle pack HV6506X Features Processed with HVCMOS(R) technology 32 push-pull CMOS output up to 60V Low power level shifting Source/sink current minimum 5mA Shift register speed 5MHz Latched data outputs Bidirectional shift register (DIR) Backplane output General Description The HV65 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver circuit for LCD displays. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capabilities. The inputs are fully CMOS compatible. The device consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity select of the outputs. HVout1 is connected to the first stage of the shift register through the polarity logic. Data is shifted through the shift register on the logic low to high transition of the clock. A DIR pin causes data shifting counterclockwise when grounded and clockwise when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable) or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored after LE transition from high to low. Absolute Maximum Ratings1 Supply voltage, VDD2 Output voltage, Logic input Ground VPP2 levels2 -0.5V to +7.0V -0.5V to +80V -0.5V to VDD + 0.5V 1.5A dissipation4 1200mW -40C to +85C -65C to +125C 260C current3 Continuous total power Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds Notes: 1. Device will survive (but operation may not be specified or guaranteed) at these extremes. 2. All voltages are referenced to VSS. 3. Duty cycle is limited by the total power dissipated in the package. 4. For operation above 25C ambient derate linearly to 85C at 20mW/C. 12-132 HV6506 Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics (VDD = 5V, VPP = 60V, VSS = GND) Symbol IDD IPP IDDQ VOH VOL IIH IIL VOLBP VOHBP Parameter VDD supply current High voltage supply current Min Max 15 0.5 0.5 Quiescent VDD supply current High-level output Q Data out Low-level output Q Data out High-level logic input current Low-level logic input current Low-level output voltage, backplane High-level output viltage, backplane 48 50 4.6 8 0.4 1 -1 8 0.5 Units mA mA mA mA V V V V A A V V Conditions VDD = VDD max fCLK = 5MHz Outputs high Outputs low All VIN = VSS or VDD IO= 5mA, VPP = 60V IO= -100A IO= 5mA, VPP = 60V IO= 100A VIH = VDD VIL = 0V IO = 40mA IO = -40mA AC Characteristics (VDD = 5V, VPP = 60V, TC = 25C) Symbol fCLK tW tSU tH tON, tOFF tON, tOFF tDHL tDLH tDLE tWLE tSLE Parameter Clock frequency Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time from latch enable or POL to HVOUT Time from POL to BP output Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high Width of LE pulse LE set-up time before clock rises 50 100 50 100 25 50 500 500 200 200 Min Max 5 Units MHz ns ns ns ns ns ns ns ns ns ns CL = 30pF CL = 30pF CL = 15pF CL = 15pF Conditions 12 Recommended Operating Conditions Symbol VDD VPP VIH VIL fCLK TA IOD Logic supply voltage Output off voltage High-level input voltage Low-level input voltage Clock frequency Operating free-air temperature Allowable current through output diodes -40 Parameter Min 4.5 0 3.5 0 Max 5.5 60 VDD 0.8 5 +85 200 Units V V V V MHz C mA Notes: 1. Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 2. Power-down sequence should be the reverse of the above. 3. The VPP should not drop below 0V during operation. 12-133 HV6506 Switching Waveforms VIH Data Input 50% tSU Clock 50% tWL 50% tWH 50% VOL Data Out tDLH 50% tDHL VOH VOL Data Valid tH VIH 50% 50% VIL VOH 50% VIL VIH Latch Enable tDLE 50% tWLE 50% tSLE VOH 50% tOFF VOL VOL HVOUT w/ S/R LOW HVOUT w/ S/R HIGH tON VOH 50% VOL POL (ASYNCH w/ Clock) 50% tOFF 50% tON VOHBP 50% 50% VOLBP BPOUT 12-134 HV6506 Functional Block Diagram VPP Polarity Latch Enable VDD Data Input Latch HVOUT1 Clock 32-Bit Shift Register Latch HVOUT2 DIR (Outputs 3 to 30 not shown) HVOUT31 Latch Data Out Latch HVOUT32 BPOUT GND Function Table Inputs Function Load S/R Load latches Data H or L X X All high H L All low H L L Transparent Mode H L H R/L Shift X X CLK H or L H or L LE L L L H H H H H H H H X X POL H H L L H H L H H L L X X DIR X X X X X X X X X X X H L Shift Reg 1 2...32 H or L * * H L H L L H L H *...* *...* *...* *...* *...* *...* *...* *...* *...* *...* *...* Outputs HV Outputs 1 * * * H H L L H L L H * * *...* *...* *...* *...* *...* *...* *...* *...* *...* *...* *...* *...* *...* Data Out 2...32 * * * * * * * * * * * Q32 Q1 BPOUT * H H L L H H L H H L L 12 Qn Qn+1 Qn Qn-1 Notes: H = high level, L = low level, X = irrelevant, = low-to-high transition. * = dependent on previous stage's state before the last CLK or last LE high. 12-135 HV6506 Pin Configuration HV65 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 17/16 HVOUT 16/17 HVOUT 15/18 HVOUT 14/19 HVOUT 13/20 HVOUT 12/21 HVOUT 11/22 HVOUT 10/23 HVOUT 9/24 HVOUT 8/25 HVOUT 7/26 HVOUT 6/27 HVOUT 5/28 HVOUT 4/29 HVOUT 3/30 HVOUT 2/31 HVOUT 1/32 Data Out GND N/C N/C POL Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function LE VDD Clock DIR Data In VPP BP Out HVOUT 32/1 HVOUT 31/2 HVOUT 30/3 HVOUT 29/4 HVOUT 28/5 HVOUT 27/6 HVOUT 26/7 HVOUT 25/8 HVOUT 24/9 HVOUT 23/10 HVOUT 22/11 HVOUT 21/12 HVOUT 20/13 HVOUT 19/14 HVOUT 18/15 HV65 44 Pin Plastic Gullwing (QFP) Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 22/11 HVOUT 21/12 HVOUT 20/13 HVOUT 19/14 HVOUT 18/15 HVOUT 17/16 HVOUT 16/17 HVOUT 15/18 HVOUT 14/19 HVOUT 13/20 HVOUT 12/21 HVOUT 11/22 HVOUT 10/23 HVOUT 9/24 HVOUT 8/25 HVOUT 7/26 HVOUT 6/27 HVOUT 5/28 HVOUT 4/29 HVOUT 3/30 HVOUT 2/31 HVOUT 1/32 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Data Out GND N/C N/C POL LE VDD Clock DIR Data In VPP BP Out HVOUT 32/1 HVOUT 31/2 HVOUT 30/3 HVOUT 29/4 HVOUT 28/5 HVOUT 27/6 HVOUT 26/7 HVOUT 25/8 HVOUT 24/9 HVOUT 23/10 Note: 1. Pin designation for DIR = H/L Example: for DIR = H, Pin 1 = HVOUT 17 for DIR = L, Pin 1 = HVOUT 16 Note: 1. Pin designation for DIR = H/L Example: for DIR = H, Pin 1 is HVOUT 22 for DIR = L, Pin 1 is HVOUT 11 Package Outline 44 43 42 41 40 39 38 37 36 35 34 39 38 37 36 35 34 33 32 31 30 29 1 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 2 3 4 5 6 7 8 9 10 11 top view 44-pin PLCC top view 44-pin Quad Plastic Gullwing Package 12-136 |
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