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HV5522/HV5530 HV5622/HV5630 32-Channel Serial To Parallel Converter With Open Drain Outputs
Ordering Information
Package Options Device HV5522 HV5530 HV5622 HV5630 Recommended Operating VPP max 220V 300V 220V 300V 44 J-Lead Quad Ceramic Chip Carrier HV5522DJ HV5530DJ HV5622DJ HV5630DJ 44 J-Lead Quad Plastic Chip Carrier HV5522PJ HV5530PJ HV5622PJ HV5630PJ 44 Lead Quad Plastic Gullwing HV5522PG HV5530PG HV5622PG HV5630PG Die HV5522X HV5530X HV5622X HV5630X
Features
Processed with HVCMOS(R) technology Sink current minimum 100mA Shift register speed 8MHz Polarity and Blanking inputs CMOS compatible inputs Forward and reverse shifting options Diode to VPP allows efficient power recovery 44-lead ceramic surface mount package Hi-Rel processing available
General Description
The HV55 and HV56 are low-voltage serial to high-voltage parallel converters with open drain outputs. These devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application requiring multiple output high voltage current sinking capabilities such as driving inkjet and electrostatic print heads, plasma panels, vacuum fluorescent, or large matrix LCD displays. These devices consist of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the high to low transition of the clock. The HV55 shifts in the counterclockwise direction when viewed from the top of the package, and the HV56 shifts in the clockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored when LE is low.
Absolute Maximum Ratings
Supply voltage, VDD1 Output voltage, VPP1 HV5530/HV5630 HV5522/HV5622 Logic input Ground levels1 -0.5V to +15V -0.5V to +315V -0.5V to +230V
-0.5V to VDD + 0.5V 1.5A dissipation3 Ceramic Plastic 1500mW 1200mW
current2
Continuous total power
Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds
Ceramic -55C to +125C Plastic -40C to +85C -65C to +150C 260C
Notes: 1. All voltages are referenced to VSS. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25C ambient derate linearly to maximum operating temperature at 20C for plastic and at 15mW/C for ceramic.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to 1 workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV5522/HV5530/HV5622/HV5630
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics
Symbol IDD IDDQ IO(OFF) IIH IIL VOH VOL VOC Parameter VDD supply current Quiescent VDD supply current Off state output current High-level logic input current Low-level logic input current High-level output data out Low-level output voltage HVOUT clamp voltage HVOUT Data out VDD - 1.0V 15.0 1.0 -1.5 Min Max 15 100 10 1 -1 Units mA A A A A V V V V Conditions fCLK = 8MHz FDATA = 4MHz VIN = 0V All outputs high All SWS parallel VIH = VDD VIL = 0V IDout = -100A IHVout = +100mA IDout = +100A IOL = -100mA
AC Characteristics (VDD = 12V, TC = 25C)
Symbol fCLK tW tSU tH tON tDHL tDLH tDLE tWLE tSLE Clock frequency Clock width high or low Data set-up time before clock falls Data hold time after clock falls Turn on time, HVOUT from enable Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high Width of LE pulse LE set-up time before clock falls 50 50 50 62 25 10 500 100 100 Parameter Min Max 8 Units MHz ns ns ns ns ns ns ns ns ns RL = 2K to VPP MAX CL = 15pF CL = 15pF Conditions
Recommended Operating Conditions
Symbol VDD HVOUT VIH VIL fCLK TA Logic supply voltage High voltage output HV5530 and HV5630 HV5522 and HV5622 High-level input voltage Low-level input voltage Clock frequency Operating free-air temperature Plastic Ceramic
Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs to a known state. Power-down sequence should be the reverse of the above.
Parameter
Min 10.8 -0.3 -0.3 VDD - 2V 0
Max 13.2 +300 +220 VDD 2.0 8
Units V V V V V MHz C C
-40 -55
+85 +125
2
HV5522/HV5530/HV5622/HV5630
Input and Output Equivalent Circuits
VDD VDD
HVOUT
Input
Data Out HVIN
VSS VSS Logic Inputs VSS Logic Data Output High Voltage Outputs
Switching Waveforms
VIH Data Input 50% tSU Clock 50% tWH 50% tWL 50% VOL Data Out tDLH 50% tDHL VOH VOL Data Valid tH VIH 50% 50% VIL VOH 50% VIL
Latch Enable tDLE
50% tWLE
50% tSLE
VIH VIL
HVOUT w/ S/R HIGH tON
VOH 10% VOL
3
HV5522/HV5530/HV5622/HV5630
Functional Block Diagram
Polarity Blanking Latch Enable HVOUT1 Data Input Clock Latch 32-Bit Shift Register Latch HVOUT2
(Outputs 3 to 30 not shown) HVOUT31 Latch HVOUT32
Data Out
Latch
Function Table
Inputs Function All on All off Invert mode Load S/R Load Latches Transparent Latch mode Data X X X H or L X X L H CLK X X X
LE X X L L

BL L L H H H H H H
POL L H L H H L H H
Shift Reg 1 2...32 * * * *...* *...* *...*
Outputs HV Outputs 1 2...32 On Off * * * * Off On On...On Off...Off *...* *...* *...* *...* *...* *...*
Data Out * * * * * * * * *
H or L *...* * * L H *...* *...* *...* *...*
H or L H or L

H H
Notes: H = high level, L = low level, X = irrelevant, = high-to-low transition, = low-to-high transistion. * = dependent on previous stage's state before the last CLK or last LE high.
4
HV5522/HV5530/HV5622/HV5630
Pin Configurations
HV55 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 16 HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 Data Out N/C N/C N/C Polarity Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Clock VSS VDD Latch Enable Data In Blanking N/C HVOUT 1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT 10 HVOUT 11 HVOUT 12 HVOUT 13 HVOUT 14 HVOUT 15
Package Outline
39 38 37 36 35 34 33 32 31 30 29 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18
top view 44-pin J-Lead Package
HV56 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 17 HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Data Out N/C N/C N/C Polarity Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Clock VSS VDD Latch Enable Data In Blanking N/C HVOUT 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 HVOUT 24 HVOUT 23 HVOUT 22 HVOUT 21 HVOUT 20 HVOUT 19 HVOUT 18
5
HV5522/HV5530/HV5622/HV5630
Pin Configurations
HV55 44-Pin Quad Plastic Gullwing Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 11 HVOUT 12 HVOUT 13 HVOUT 14 HVOUT 15 HVOUT 16 HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Data Out N/C N/C N/C Polarity Clock VSS VDD Latch Enable Data In Blanking N/C HVOUT 1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT 10
Package Outline
44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23
top view 44-pin Quad Plastic Gullwing Package
HV56 44-Pin Quad Plastic Gullwing Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 22 HVOUT 21 HVOUT 20 HVOUT 19 HVOUT 18 HVOUT 17 HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function Data Out N/C N/C N/C Polarity Clock VSS VDD Latch Enable Data In Blanking N/C HVOUT 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 HVOUT 24 HVOUT 23
12/13/01
(c)2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
6
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com
Package Outline 44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max.), .050in pitch
.048/.042 x 45O 6 D D1 1 44 .056/.042 x 45O
40
.150 MAX
Note 1 (Index Area) .075 MAX E1 E
Note 2 (3 places)
0.20max 3 Places
Top View
View B
Side View
b1 A A2 e A1 Base Plane Seating Plane .020 MIN
b
Side View
View B
Note: 1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Exact shape of this feature is optional.
Symbol MIN Dimension (inches) NOM MAX
A .165 .172 .180
A1 .090 .105 .120
A2 .062 .083
b .013 .021
b1 .026 .036
D .685 .690 .695
D1 .650 .653 .656
E .685 .690 .695
E1 .650 .653 .656
e .050 BSC
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. Drawings are not to scale.
Doc. #: DSPD-44PLCCPJ B051607
Package Outline 44-Lead PQFP Package Outline (PG)
D D1
E
E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane
Top View
View B A A2 Seating Plane A1
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 2.45
A1 0.25 -
A2 1.95 2.00 2.10
b 0.30 0.45
D 13.65 13.90 14.15
D1 9.80 10.00 10.20
E 13.65 13.90 14.15
E1 9.80 10.00 10.20
e 0.80 BSC
L 0.73 0.88 1.03
L1 1.95 REF
L2 0.25 BSC
3.5O 7
O
1 5O 16O
JEDEC Registration M0-112, Variation AA-2, Issue B, Sep.1995.
Doc. #: DSPD-44PQFPPG A031607

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