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PRELIMINARY
Z89462 CP95DSP0400
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
Z89462
16-BIT, FIXED-POINT DIGITAL SIGNAL PROCESSOR
FEATURES
Part Z89462
s s s
Prog. RAM (K Words) 1
Prog./Data Data RAM (K Words) (Words) 64 512
Speed (MHz) 20, 40
s s s
Enhanced Instruction Set Single-Cycle Instruction Execution Four-Stage Pipeline
100-Pin QFP and 124-Pin PGA Packages 0C to +70C Temperature Range 3.3- to 5.0-Volt Operating Range 40 MHz Operation @ 5.0V 20 MHz Operation @ 3.3V Six RAM Pointers for 4K-Word RAM Banks Three Maskable Vectored Interrupts, Edge or Level Trigger Selectable
On-Board Peripherals
s s s s
Dual 8/16-Bit CODEC Interface Wait-State Generator Two 16-Bit Timer/Counters Dynamic Program Bus Sizing
s s
GENERAL DESCRIPTION
The Z89462 is a high-performance Digital Signal Processor (DSP) optimized for processing and transferring data. This enhanced processor provides an upward migration path for its Z89C00/Z89321 predecessors. The DSP provides three 12-bit Register Pointers for each RAM bank. These pointers may be incremented or decremented automatically to implement circular buffers without software overhead. Three prioritized and individually maskable interrupts are provided for use by external peripherals requiring service from the DSP. The interrupt inputs can be individually conditioned for edge or level trigger. Acknowledgement of an activated interrupt occurs at the end of an instruction execution. Two banks of 512 x 16-bit data RAM are available. Expansion of the on-chip data RAM is provided through future upgrades. External interfaces include Address Bus and Data Bus for external Program Memory, Address Bus and Data Bus for external Data Memory, three vectored interrupt ports, and two input/two output user ports.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD
VSS
CP95DSP0400 (8/95)
1
PRELIMINARY
Z89462 CP95DSP0400
GENERAL DESCRIPTION (Continued)
MD15-MD0 MA15-MA0 PD15-PD0 MRD//WR
PA15-PA0
16 Timers CODEC
16
16 16 Program RAM 1KW
RAM0 512W
RAM1 512W
WSG_BYWD
16 MDR MAR SP FPR MBUS_RAM01 Control IDB 16 X Multiplier PH P 32 PB 16 32 MUX B ALU 32 8 AE AH A AL A PL BFB Y BFR Bit Field Unit RC 32 Repeat Count Reg CR Control Reg SR IR DSP Control PDR ds
2 2
waits
rd,wr PAR PC PBUS Control
3 INT CTL INT2-0 /HLTHW /HLTOUT /RESET
Status Reg 2 User Port 2 UI1-0 UO1-0
CLK GEN 8
CLKIN CLK VDD VSS 8
Functional Block Diagram
2
PRD//WR
/MWAIT
RxD SCLK FS0
/PWAIT /PDS /PDSZE /PALSB
TxD
FS1
/MDS
PRELIMINARY
Z89462 CP95DSP0400
PIN DESCRIPTION
/HLTOUT PD9 PD8 /RESET PD7 CKIN PD6 VSSI PD5 CLK /PWAIT PD4 PD15 PD14 PD13 /HLTHW PD12 PD11 PD10 INT0 PDSZE PD3 INT1 VSSP VDDP
75 MA0 PA0 MA1 PA1 MA2 PA2 MA3 PA3 VDDP VSSP MA4 MA5 MA6 MA7 VSSI MRD//WR /MDS /MWAIT MA8 PA4 MA9 VDDP VSSP PA5 MA10 76
70
65
60
55
51 50 PD2 PALSB INT2 PD5 PRD//WR UI1 PD1 UI0 PD0 UO1 UO0 MD15 VDDI MD14 MD13 VSSP VDDP MD12 MD11 MD10 MD9 PA15 MD8 PA14 MD7
80 45
85 40
90
Z89462 100-Pin VQFP
35
95 30
100 1 5 10 15 20 25
26
Pin 1
PA6 MA11 PA7 MA12 PA8 MA13 PA9 MA14 VDDP VSSP MA15 MD0 VDDI MD1 MD2 MD3 PA10 MD4 PA11 MD5 VDDP VSSP PA12 MD6 PA13
100-Pin VQFP Pin Assignments
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PRELIMINARY
Z89462 CP95DSP0400
PIN DESCRIPTION (Continued)
FETCH MA10 MRD//WR VSSI MA7 PA4 MA8 /MWAIT /MDS VDDP MA9 MA4 VSSP VDDP PA3 MA3 PA5 VSSP PA2 MA2 PA1 MA1 PA0 MA0 EXEC
31
63
MA6 MA5
/PAZ PA6 MA11 PA7 MA12 PA8 MA13 PA9 MA14 VDDP VSSP MA15 MD0 VDDI MD1 MD2 MD3 PA10 MD4 PA11 MD5 VDDP VSSP PA12 MD6 PA13 IACK
93 1
/MAZ PD15 PD14 PD13 /HLTHW PD12 PD11 PD10 /HLTOUT PD9 PD8 /RESET
Z89462 124-Pin PGA
PD7 CKIN PD6 VSSI PD5 CLK IPWAIT PD4 INT0 PDSZE PD3 INT1 VSSP VDDP
/MDBEN
MD8 PA15
MD9
MD10 MD11 MD12 VDDP VSSP MD13 MD14
MD7 PA14
PD1 UI1
PRD//WR /PDS
INT2
VDDI MD15 UO0
124-Pin PGA Pin Assignments
4
PALSB PD2
/BRK
UO1 PD0 UI0
PRELIMINARY
Z89462 CP95DSP0400
ABSOLUTE MAXIMUM RATINGS
Description Voltages on VDD with Respect to VSS Voltages on All Pins with Respect to VSS TSTG Storage Temp TA Oper Ambient Temp Min. Max. -0.5 -0.5 -85 0 Units V V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability.
+5.5 (VDD+0.5) +150 +70
STANDARD TEST CONDITIONS
The AC and DC Characteristics listed below apply for standard test conditions, unless otherwise noted. All voltages are referenced to VSS (= Ground = 0V). Positive current flows into the referenced pin. Standard conditions are as follows: 3.0V < VDD < 3.6V VSS = 0V Ambient Temperature = 0C to +70C Standard Test Load on All Outputs
DC ELECTRICAL CHARACTERISTICS (5.0V Operation)
Sym. VIH VIL VOH1 VOH2 VOL IIL ITL IDD IDD2 CIN COUT CIO CL Parameter Input High Voltage Input Low Voltage Output High Voltage (-4 mA IOH) Output High Voltage (-250 A IOH) Output Low Voltage (4 mA IOL) Input Leakage Current Tri-State Leakage Current Power Supply Current (@ 40 Mhz) Stopped Clock Power Supply Current Input Capacitance (f = 1 MHz) Output Capacitance (f = 1 Mhz) I/O Capacitance (f = 1 MHz) Output Load Capacitance Min. 2.0 -0.5 2.4 VDD -0.8 -10 -10 0.5 +10 +10 TBD 20 15 15 15 30 Max. VDD +0.5 0.8 Unit V V V V V A A mA A pF pF pF pF Note
[1] [2] [3] [4] [5] [5] [5]
Notes: [1] VIN = 0.4V [2] 0.4V < VOUT < 2.4V [3] VDD = 5.0V, VIH = 4.8V, VIL = 0.2V [4] VDD = 5.0V, VIH = 4.8V, VIL = 0.2V [5] Unmeasured pins returned to VSS.
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PRELIMINARY
Z89462 CP95DSP0400
AC ELECTRICAL CHARACTERISTICS (5.0V Operation)
Symbol TcCI TwCIh TwCIl TrCI TfCI TdCIr(Cr) TdCIf(Cf) TrC TfC TdCr(PA) TdCr(PALSB) TdCr(PDSr) TdCf(PDSf) TsPW(Cr) ThPW(Cr) TsPSZ(Cr) ThPSZ(Cr) TdCr(PRDWR) TsPD(Cr) ThPD(Cr) TdCR(PD) TdCr(PDt) TdCr(MA) TdCr(MDSr) TdCf(MDSf) TsMW(Cr) ThMW(Cr) TdCr(MRDWR) TsMD(Cr) ThMD(Cr) TdCr(MD) TdCr(MDt) TsINT(Cr) TwINTh TwHLTHWl TwHLTHWh TdCr(HLTOUT) TwRESETl
Parameter CLKIN Cycle Time CLKIN Width High CLKIN Width Low CLKIN Rise Time CLKIN Fall Time CLKIN Rise to CLK Rise Delay CLKIN Fall to CLK Fall Delay CLK Rise Time CLK Fall Time CLK Rise to PA Valid Delay CLK Rise to PALSB Valid Delay CLK Rise to /PDS Rise Delay CLK Fall to /PDS Fall Delay /PWAIT to CLK Rise Setup Time /PWAIT to CLK Rise Hold Time PDSZE to CLK Rise Setup Time PDSZE to CLK Rise Hold Time CLK Rise to PRD//WR Delay PD to CLK Rise Setup Time PD to CLK Rise Hold Time CLK Rise to PD Valid Delay CLK Rise to PD Tri-State Delay CLK Rise to MA Valid Delay CLK Rise to /MDS Rise Delay CLK Rise to /MDS Fall Delay /MWAIT to CLK Rise Setup Time /MWAIT to CLK Rise Hold Time CLK Rise to MRD//WR Delay MD to CLK Rise Setup Time MD to CLK Rise Hold Time CLK Rise to MD Valid Delay CLK Rise to MD Tri-State Delay INT2-0 to CLK Rise Setup Time INT2-0 Width High /HLTHW Width Low /HLTHW Width High CLK Rise to HLTOUT Delay /RESET Width Low
Min. 25 10 10
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TcCI [1] [2] [2] [2]
Note
2 2 8 8 2 2 5 5 4 4 5 0 5 0 5 5 0 5 5 5 4 4 5 0 5 5 0 5 5 5 10 10 2 5 3
TcCI ns TcCI
Notes: [1] INT2-0 can also be asserted/deasserted asynchronously. [2] These signals are asserted/deasserted asynchronously.
.
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PRELIMINARY
Z89462 CP95DSP0400
DC ELECTRICAL CHARACTERISTICS (3.0V Operation)
Sym. VIH VIL VOH VOL IIL ITL IDD IDD2 CIN COUT CIO CL Parameter Input High Voltage Input Low Voltage Output High Voltage (-200 A IOH) Output Low Voltage (4 mA IOL) Input Leakage Current Tri-State Leakage Current Power Supply Current (@ 40 Mhz) Stopped Clock Power Supply Current Input Capacitance (f = 1 MHz) Output Capacitance (f = 1 Mhz) I/O Capacitance (f = 1 MHz) Output Load Capacitance Min. 2.0 -0.5 2.15 -10 -10 Max. VDD +0.5 0.6 0.4 +10 +10 TBD 20 15 15 15 30 Unit V V V V A A mA A pF pF pF pF [1] [2] [3] [4] [5] [5] [5] Note
Notes: [1] VIN = 0.4V [2] 0.4V < VOUT < 2.15V [3] VDD = 3.3V, VIH = 3.0V, VIL = 0.2V [4] VDD = 3.3V, VIH = 3.0V, VIL = 0.2V [5] Unmeasured pins returned to VSS.
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PRELIMINARY
Z89462 CP95DSP0400
Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-
conformance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues.
Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain
and delays. No production release is authorized or committed until the Customer and Zilog have agreed upon a Customer Procurement Specification for this project.
and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com
(c) 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
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