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WM8774
24-bit, 192kHz 8-Channel Input Stereo Codec
DESCRIPTION
The WM8774 is a high performance, stereo audio codec with an 8 channel input selector. The WM8774 is ideal for surround sound processing applications for home hi-fi, automotive and other audio visual equipment. A stereo 24-bit multi-bit sigma delta ADC is used with an eight stereo channel input selector. Each channel has analogue domain mute and programmable gain control. Digital audio output word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported. A stereo 24-bit multi-bit sigma delta DAC is used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent analogue volume and mute control, with a set of input multiplexors allowing selection of an external analogue input into these volume controls. The audio data interface supports I2S, left justified, right justified and DSP digital audio formats. The device is controlled via a 3 wire serial interface. The interface provides access to all features including channel selection, volume controls, mutes, de-emphasis and power management facilities. The device is available in a 64-pin TQFP package.
FEATURES
* Audio Performance - 106dB SNR (`A' weighted @ 48kHz) DAC - 101dB SNR (`A' weighted @ 48kHz) ADC DAC Sampling Frequency: 8kHz - 192kHz ADC Sampling Frequency: 8kHz - 96kHz 3-Wire SPI Compatible Serial Control Interface Master or Slave Clocking Mode Programmable Audio Data Interface Modes - I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths Stereo DAC with independent analogue and digital volume controls Analogue Bypass Path Feature Selectable AUX input to the volume controls Eight stereo ADC inputs with analogue gain adjust from +19dB to -12dB in 1dB steps 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation 5V tolerant digital inputs
* * * * *
* * * * * *
APPLICATIONS
* * Surround Sound AV Processors and Hi-Fi systems Automotive Audio
DACREFN2 DACREFP1 VMIDDAC
BLOCK DIAGRAM
VMIDADC REFADC AINVGR ZFLAGR ZFLAGL AINVGL AGND AVDD
MCLK DOUT ADCLRC BCLK DACLRC DIN
AGND2
AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R AIN6L AIN6R AIN7L AIN7R AIN8L AIN8R
INPUT SOURCE SELECTOR
AUDIO INTERFACE STEREO ADC AND DIGITAL FILTERS STEREO DAC
LOW PASS FILTERS
AVDD2
VOUTL VOUTR
AINOPL AINOPR RECL RECR
MUTE
CONTROL INTERFACE
WM8774
GR1 GR2 AUXL AUXR
CL
RESETB
DGND
WOLFSON MICROELECTRONICS LTD w :: www.wolfsonmicro.com
DVDD
CE
DI
Product Preview, June 2002, Rev 1.0 Copyright 2002 Wolfson Microelectronics Ltd.
WM8774 PIN CONFIGURATION
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ORDERING INFORMATION
DEVICE WM8774IFT/V TEMP. RANGE -40 to +85oC PACKAGE 64-pin TQFP
ADCLRC
DACLRC
RESETB
ZFLAGR
ZFLAGL
MCLK
BCLK
AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R AIN6L AIN6R AIN7L AIN7R AIN8L AIN8R
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
DVDD
DOUT
DIN
NC
NC
NC
CE
CL
DI
DGND AGND2 NC NC DACREFP2 NC GR2 NC VMIDDAC NC GR1 NC DACREFP1 VOUTR VOUTL AVDD2
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND1
AVDD1
AUXR
AINVGR
AINOPR
RECL
REFADC
AINOPL
AINVGL
VMIDADC
AUXL
NC
NC
NC
RECR
NC
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Product Preview
WM8774
NAME AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R AIN6L AIN6R AIN7L AIN7R AIN8L AIN8R AINOPL AINVGL AINVGR AINOPR RECL RECR REFADC VMIDADC AGND1 AVDD1 AUXL AUXR TYPE Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Output Analogue Input Analogue Input Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Supply Supply Analogue input Analogue input NC NC NC NC AVDD2 VOUTL VOUTR DACREFP1 GR1 VMIDDAC GR2 DACREFP2 Supply Analogue output Analogue output Supply NC Supply NC Analogue output NC Supply NC Supply NC NC AGND2 DGND DVDD Supply Supply Supply DESCRIPTION Channel 1 left input multiplexor virtual ground Channel 1 right input multiplexor virtual ground Channel 2 left input multiplexor virtual ground Channel 2 right input multiplexor virtual ground Channel 3 left input multiplexor virtual ground Channel 3 right input multiplexor virtual ground Channel 4 left input multiplexor virtual ground Channel 4 right input multiplexor virtual ground Channel 5 left input multiplexor virtual ground Channel 5 right input multiplexor virtual ground Channel 6 left input multiplexor virtual ground Channel 6 right input multiplexor virtual ground Channel 7 left input multiplexor virtual ground Channel 7 right input multiplexor virtual ground Channel 8 left input multiplexor virtual ground Channel 8 right input multiplexor virtual ground Left channel multiplexor output Left channel multiplexor virtual ground Right channel multiplexor virtual ground Right channel multiplexor output Left channel input mux select output Right channel input mux select output ADC reference buffer decoupling pin; 10uF external decoupling ADC midrail divider decoupling pin; 10uF external decoupling Analogue negative supply and substrate connection Analogue positive supply Multiplexor channel left virtual ground input 3.1 Multiplexor channel right virtual ground input No connection No connection No connection No connection Analogue positive supply DAC channel 1 left output DAC channel 1 right output DAC positive reference supply No connection DAC ground reference No connection DAC midrail decoupling pin ; 10uF external decoupling No connection DAC ground reference No connection DAC positive reference supply No connection No connection Analogue negative supply and substrate connection Digital negative supply Digital positive supply
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
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WM8774
PIN 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DACLRC ADCLRC BCLK MCLK CL DI CE RESETB NAME ZFLAGL ZFLAGR DOUT DIN TYPE Digital output Digital output Digital output Digital Input NC NC NC Digital input/output Digital input/output Digital input/output Digital input Digital input Digital input Digital input Digital input DAC Zero Flag output DAC Zero Flag output ADC data output DAC channel 1 data input No connection No connection No connection DAC left/right word clock ADC left/right word clock ADC and DAC audio interface bit clock DESCRIPTION
Product Preview
Master DAC and ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency) Serial interface clock (5V tolerant) Serial interface data (5V tolerant) Serial interface Latch signal (5V tolerant) Device reset input (mutes DAC outputs, resets gain stages to 0dB) (5V tolerant)
Note : Digital input pins have Schmitt trigger input buffers and are 5V tolerant.
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WM8774
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs (DI, CL, CE & RESETB) Voltage range digital inputs (MCLK, DIN[3:0], ADCLRC, DACLRC & BCLK) Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Notes: 1. Analogue and digital grounds must always be within 0.3V of each other.
MIN -0.3V -0.3V DGND -0.3V DGND -0.3V AGND -0.3V
MAX +3.63V +7V +7V DVDD + 0.3V AVDD +0.3V 37MHz
-40C -65C
+85C +150C +240C +183C
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WM8774 RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. SYMBOL DVDD AVDD AGND, DGND -0.3 TEST CONDITIONS MIN 2.7 2.7 0 0 +0.3 TYP MAX 3.6 5.5
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UNIT V V V V
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance VVMID RVMID AVDD to VMID and VMID to AGND AVDD/2 - 50mV 40k AVDD/2 50k AVDD/2 + 50mV 60k V Ohms VIL VIH VOL VOH IOL=1mA IOH-1mA 0.9 x DVDD 2.0 0.1 x DVDD 0.8 V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DAC Performance (Load = 10k ohms, 50pF) 0dBFs Full scale output voltage SNR (Note 1,2) SNR (Note 1,2) Dynamic Range (Note 2) Total Harmonic Distortion (THD) DAC channel separation DAC analogue Volume Gain Step Size DAC analogue Volume Gain Range DAC analogue Volume Mute Attenuation Power Supply Rejection Ratio PSRR 1kHz Input 1kHz Input, 0dB gain 1kHz 100mVpp 20Hz to 20kHz 100mVpp ADC Performance Input Signal Level (0dB) SNR (Note 1,2) SNR (Note 1,2) Dynamic Range (note 2) Total Harmonic Distortion (THD) A-weighted, 0dB gain @ fs = 48kHz A-weighted, 0dB gain @ fs = 96kHz A-weighted, -60dB full scale input kHz, 0dBFs 1kHz, -3dBFs 93 1.0 x AVDD/5 102 98 102 -90 -95 -80 -85 Vrms dB dB dB DB dB 0.5 -100 100 50 45 DNR A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted, -60dB full scale input 1kHz, 0dBFs 104 104 1.0 x AVDD/5 106 106 106 -97 100 1 1.5 0 -90 Vrms dB dB dB dB dB dB dB dB dB dB
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Product Preview
WM8774
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER ADC Channel Separation Programmable Gain Step Size Programmable Gain Range Mute Attenuation Power Supply Rejection Ratio PSRR 1kHz Input 1kHz Input, 0dB gain 1kHz 100mVpp 20Hz to 20kHz 100mVpp 0dB Full scale output voltage SNR (Note 1) THD Power Supply Rejection Ratio PSRR 1kHz, 0dB 1kHz, -3dB 1kHz 100mVpp 20Hz to 20kHz 100mVpp Mute Attenuation Supply Current Analogue supply current Digital supply current Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). AVDD = 5V DVDD = 3.3V 100 20 mA mA 1kHz, 0dB 90 SYMBOL TEST CONDITIONS 1kHz Input 0.5 -12 97 50 45 MIN TYP 90 1.0 1.5 +19 MAX UNIT dB dB dB dB dB dB
Analogue input (AIN) to Analogue output (VOUT) (Load=10k ohms, 50pF, gain = 0dB) Bypass Mode 1.0 x AVDD/5 100 -90 -95 50 45 100 Vrms dB dB dB dB dB dB
3.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
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WM8774
MASTER CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Product Preview
Figure 1 Master Clock Timing Requirements Test Conditions o AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information
MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle
SYMBOL tMCLKH tMCLKL tMCLKY
TEST CONDITIONS
MIN 11 11 28 40:60
TYP
MAX
UNIT ns ns ns
60:40
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE - MASTER MODE
BCLK ADCLRC WM8774 CODEC DACLRC DOUT DIN DVD Controller
Figure 2 Audio Interface - Master Mode
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Product Preview
WM8774
BCLK (Output) ADCLRC/ DACLRC (Outputs) tDL
tDDA DOUT
DIN tDST tDHT
Figure 3 Digital Audio Data Timing - Master Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER ADCLRC/DACLRC propagation delay from BCLK falling edge DOUT propagation delay from BCLK falling edge DIN setup time to BCLCK rising edge DIN hold time from BCLK rising edge SYMBOL tDL TEST CONDITIONS MIN 0 TYP MAX 10 UNIT ns
Audio Data Input Timing Information
tDDA tDST tDHT
0 10 10
10
ns ns ns
Table 2 Digital Audio Data Timing - Master Mode
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WM8774
DIGITAL AUDIO INTERFACE - SLAVE MODE
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BCLK ADCLRC WM8774 CODEC DACLRC DOUT DIN DVD Controller
Figure 4 Audio Interface - Slave Mode
tBCH BCLK tBCY DACLRC/ ADCLRC tDS DIN tDD DOUT tDH tLRH tLRSU tBCL
Figure 5 Digital Audio Data Timing - Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low DACLRC/ADCLRC set-up time to BCLK rising edge DACLRC/ADCLRC hold time from BCLK rising edge DIN set-up time to BCLK rising edge DIN hold time from BCLK rising edge DOUT propagation delay from BCLK falling edge Note: 1. ADCLRC and DACLRC should be synchronous with MCLK, although the WM8774 interface is tolerant of phase variations or jitter on these signals. PP Rev 1.0 June 2002 10 SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH tDD TEST CONDITIONS MIN 50 20 20 10 10 10 10 0 10 TYP MAX UNIT ns ns ns ns ns ns ns ns
Audio Data Input Timing Information
Table 3 Digital Audio Data Timing - Slave Mode
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WM8774
MPU INTERFACE TIMING
tRCSU RESETB tCSL CE tSCY tSCH CL tSCL tSCS tCSS tCSH tRCHO
DI tDSU tDHO
LSB
Figure 6 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER CE to RESETB hold time RESETB to CL setup time CL rising edge to CE rising edge CL pulse cycle time CL pulse width low CL pulse width high DI to CL set-up time CL to DI hold time CE pulse width low CE pulse width high CE rising to CL rising SYMBOL tRCSU tRCHO tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS MIN 20 20 60 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns ns
Table 4 3 Wire SPI compatible Control Interface Input Timing Information
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WM8774 DEVICE DESCRIPTION
INTRODUCTION
Product Preview
WM8774 is a complete 2-channel DAC, 2-channel ADC audio codec, with flexible input multiplexor including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-bit sigma delta DACs with analogue volume controls on each channel and output smoothing filters. It is available in a single package and controlled by a single interface. An analogue bypass path option is available, to allow stereo analogue signals from any of the 8 stereo inputs to be sent to the stereo outputs via the main volume controls. This allows a purely analogue input to analogue output high quality signal path to be implemented if required. The DAC and ADC have separate left/right clocks and data I/Os. However, BITCLK and MCLK are shared between the ADC and DAC. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode ADCLRC, DACLRC and BCLK are all inputs. In Master mode ADCLRC, DACLRC and BCLK are outputs. The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC, using external resistors to reduce the amplitude of larger signals to within the normal operating range of the ADC. The ADC input PGA also allows input signals to be gained up to +19dB and attenuated down to -12dB. This allows the user maximum flexibility in the use of the ADC. A selectable stereo record output is also provided on RECL/R. It is intended that the RECL/R outputs are only used to drive a high impedance buffer. The DAC has its own analogue and separate digital volume control. The analogue volume control is adjustable in 1dB steps and the digital volume control in 0.5dB steps. The analogue and digital volume controls may be operated independently. In addition a zero cross detect circuit is provided for both analogue and digital volume controls. When analogue volume zero-cross detection is enabled the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and `zipper' noise as the gain values change. The DAC output incorporates an input selector and mixer allowing an signal to be either switched into the signal path in place of the DAC signal or mixed with the DAC signal before the volume control. Use of external resistors allows larger input levels to be accepted by the device, giving maximum user flexibility. Control of internal functionality of the device is by 3-wire serial control interface. An SPI type control interface is used, which may be asynchronous to the audio data interface as control data will be resynchronised to the audio processing internally. CE, CL, DI and RESETB are 5V tolerant with TTL input thresholds, allowing the WM8774 to used with DVDD = 3.3V and be controlled by a controller with 5V output. Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided. In Slave mode selection between clock rates is automatically controlled. In master mode the master clock to sample rate ratio is set by control bits ADCRATE and DACRATE. ADC and DAC may run at different rates within the constraint of a common master clock for the ADC and DACs. For example with master clock at 24.576MHz, a DAC sample rate of 96kHz (256fs mode) and an ADC sample rate of 48kHz (512fs mode) can be accommodated. Master clock sample rates (fs) from less than 8kHz up to 192kHz are allowed, provided the appropriate system clock is input. The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP serial port interface.
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the MCLK input pin with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC.
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Product Preview
WM8774
The master clock for WM8774 supports DAC and ADC audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (DACLRC or ADCLRC) typically 32kHz, 44.1kHz, 48kHz or 96kHz (the DAC also supports operation at 128fs and 192fs and 192kHz sample rate). The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8774 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock must be synchronised with ADCLRC/DACLRC, although the WM8774 is tolerant of phase variations or jitter on this clock. Table 5 shows the typical master clock frequency inputs for the WM8774. The signal processing for the WM8774 typically operates at an oversampling rate of 128fs for both ADC and DAC. The exception to this for the DAC is for operation with a 128 or 192fs system clock, e.g. for 192kHz operation where the oversampling rate is 64fs. For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. SAMPLING RATE (DACLRC/ ADCLRC) 32kHz 44.1kHz 48kHz 96kHz 192kHz System Clock Frequency (MHz) 128fs 192fs 256fs 384fs 512fs 768fs
DAC ONLY 4.096 5.6448 6.144 12.288 24.576 6.144 8.467 9.216 18.432 36.864 8.192 11.2896 12.288 24.576 12.288 16.9340 18.432 36.864 16.384 22.5792 24.576 24.576 33.8688 36.864
Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 5 System Clock Frequencies Versus Sampling Rate In Master mode BCLK, DACLRC and ADCLRC are generated by the WM8774. The frequencies of ADCLRC and DACLRC are set by setting the required ratio of MCLK to DACLRC and ADCLRC using the DACRATE and ADCRATE control bits (Table 6). ADCRATE[2:0]/ DACRATE[2:0] 000 001 010 011 100 101 MCLK:ADCLRC/DACLRC RATIO 128fs (DAC Only) 192fs (DAC Only) 256fs 384fs 512fs 768fs
Table 6 Master Mode MCLK:ADCLRC/DACLRC Ratio Select Table 7 shows the settings for ADCRATE and DACRATE for common sample rates and MCLK frequencies. SAMPLING RATE (DACLRC/ ADCLRC) System Clock Frequency (MHz) 128fs
DACRATE =000
192fs
DACRATE =001
256fs
ADCRATE/ DACRATE =010
384fs
ADCRATE/ DACRATE =011
512fs
ADCRATE/ DACRATE =100
768fs
ADCRATE/ DACRATE =101
32kHz 44.1kHz 48kHz 96kHz 192kHz
4.096 5.6448 6.144 12.288 24.576
6.144 8.467 9.216 18.432 36.864
8.192 11.2896 12.288 24.576
12.288 16.9340 18.432 36.864
16.384 22.5792 24.576
24.576 33.8688 36.864
Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 7 Master Mode ADC/DACLRC Frequency Selection
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WM8774
Product Preview BCLK is also generated by the WM8774. The frequency of BCLK depends on the mode of operation. In 128/192fs modes (DACRATE=000 or 001) BCLK = MCLK/2. In 256/384/512fs modes (ADCRATE/DACRATE=010 or 011, 100 or 101) BCLK = MCLK/4. However if DSP mode is selected as the audio interface mode then BCLK=MCLK. This is to ensure that there are sufficient BCLKs to clock in all eight channels. Note that DSP mode cannot be used in 128fs mode for word lengths greater than 16 bits or in 192fs mode for word lengths greater than 24 bits.
ZERO DETECT
The WM8774 has a zero detect circuit for each channel, which detects when 1024 consecutive zero samples have been input. Two zero flag outputs (ZFLAGL and ZFLAGR) may be programmed to output the zero detect signals (see Table 8) which may then be used to control external muting circuits. A `1' on ZFLAGL or ZFLAGR indicates a zero detect. The zero detect may also be used to automatically enable the PGA mute by setting IZD. The zero flag output may be disabled by setting DZFM to 00. The zero flag signal for each DAC channel will only be enabled if that channel is enabled as an input to the output summing stage. DZFM[1:0] 00 01 10 11 ZFLAGL Zero flag disabled Both channels zero Left channel zero Both channels zero ZFLAGR Zero flag disabled Both channels zero Right channel zero -
Table 8 Zero Flag Output Select
POWERDOWN MODES
The WM8774 has powerdown control bits allowing specific parts of the WM8774 to be powered off when not being used. The 8-channel input source selector and input buffer may be powered down using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN8L/R) are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input PGAs. The four stereo DACs each have a separate powerdown control bit, DACPD allowing individual stereo DACs to be powered off when not in use. The analogue output mixers and EVRs may also be powered down by setting OUTPD. OUTPD also switches the analogue outputs VOUTL/R to VMIDDAC to maintain a dc level on the output. Setting AINPD, ADCPD, DACPD and OUTPD will powerdown everything except the references VMIDADC, ADCREF and VMIDDAC. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the 8-channel input mux and buffer, ADC, DAC, output mixer and EVR are powered down before setting PDWN. The default is for all powerdown bits to be set except PDWN. The Powerdown control bits allow parts of the device to be powered down when not in use. For example, if only an analogue bypass path from AINL/R to VOUTL/R is required the ADCPD and DACPD control bits may be set, leaving the analogue input and analogue output powered up.
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DACDAT is always an input to the WM8774 and ADCDAT is always an output. The default is Slave mode. In Slave mode (MS=0) ADCLRC, DACLRC and BCLK are inputs to the WM8774 (Figure 7). DIN, ADCLRC and DACLRC are sampled by the WM8774 on the rising edge of BCLK. ADC data is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so that DIN, ADCLRC and DACLRC are sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK.
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Product Preview
WM8774
BCLK ADCLRC WM8774 CODEC DACLRC DOUT DIN DVD Controller
Figure 7 Slave Mode In Master mode (MS=1) ADCLRC, DACLRC and BCLK are outputs from the WM8774 (Figure 8). ADCLRC, DACLRC and BITCLK are generated by the WM8774. DIN is sampled by the WM8774 on the rising edge of BCLK so the controller must output DAC data that changes on the falling edge of BCLK. ADCDAT is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so that DIN is sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK.
BCLK ADCLRC WM8774 CODEC DACLRC DOUT DIN DVD Controller
Figure 8 Master Mode
AUDIO INTERFACE FORMATS
Audio data is applied to the internal DAC filters, or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP Early mode DSP Late mode
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN inputs and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with ADCLRC/DACLRC indicating whether the left or right channel is present. ADCLRC/DACLRC is also used as a timing reference to indicate the beginning or end of the data words.
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WM8774
Product Preview In left justified, right justified and I2S modes, the minimum number of BCLKs per DACLRC/ADCLRC period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on ADCLRC/DACLRC is acceptable provided the above requirements are met. In DSP early or DSP late mode, multiple DACs channel can be time multiplexed onto DIN. DACLRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per DACLRC period is 8 times the selected word length. Any mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP early or late modes, with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of BCLKs per ADCLRC period is 2 times the selected word length
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN is sampled by the WM8774 on the first rising edge of BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of BCLK as ADCLRC and may be sampled on the rising edge of BCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 9).
1/fs
LEFT CHANNEL DACLRC/ ADCLRC
RIGHT CHANNEL
BCLK
DIN/ DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 9 Left Justified Mode TIming Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN is sampled by the WM8774 on the rising edge of BCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of BCLK preceding an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples ( Figure 10).
1/fs
LEFT CHANNEL DACLRC/ ADCLRC
RIGHT CHANNEL
BCLK
DIN/ DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 10 Right Justified Mode Timing Diagram
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WM8774
I S MODE
In I2S mode, the MSB of DIN is sampled by the WM8774 on the second rising edge of BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.
1/fs
2
LEFT CHANNEL DACLRC/ ADCLRC
RIGHT CHANNEL
BCLK
1 BCLK 1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n
DIN/ DOUT
1
2
MSB
LSB
MSB
LSB
Figure 11 I2S Mode TIming Diagram
DSP EARLY MODE
In DSP early mode, the MSB of DAC channel left data is sampled by the WM8774 on the second rising edge on BCLK following a DACLRC rising edge (Figure 12).
1 BCLK 1/fs 1 BCLK
DACLRC
BCK
CHANNEL LEFT
CHANNEL RIGHT
NO VALID DATA
DIN
1
2
n-1
n
1
2
n-1
n
MSB
Word Length (IWL)
LSB
Figure 12 DSP Early Mode Timing Diagram - DAC Data Input The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 13)
1 BCLK 1/fs 1 BCLK
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
MSB
LSB
Input Word Length (IWL)
Figure 13 DSP Early Mode Timing Diagram - ADC Data Output
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DSP LATE MODE
Product Preview
In DSP late mode, the MSB of DAC channel left data is sampled by the WM8774 on the first BCLK rising edge following a DACLRC rising edge (Figure 14).
1/fs
DACLRC
BCK
CHANNEL LEFT
CHANNEL RIGHT
NO VALID DATA
DIN
1
2
n-1
n
1
2
n-1
n
1
MSB
Word Length (WL)
LSB
Figure 14 DSP Late Mode Timing Diagram - DAC Data Input The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of BCLK as the low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 15).
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
1
MSB
Word Length (WL)
LSB
Figure 15 DSP Late Mode Timing Diagram - ADC Data Output In both early and late DSP modes, DACL is always sent first, followed immediately by DACR. No BCLK edges are allowed between the data words.
CONTROL INTERFACE OPERATION
The WM8774 is controlled using a 3-wire serial interface a SPI compatible. The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD. RESETB is also 5V tolerant.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
DI is used for the program data, CL is used to clock in the program data and CE is used to latch the program data. DI is sampled on the rising edge of CL. The 3-wire interface protocol is shown in Figure 16.
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WM8774
CE
CL
DI
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 16 3-Wire SPI Compatible Interface 1. 2. 3. B[15:9] are Control Address Bits B[8:0] are Control Data Bits CE is edge sensitive - the data is latched on the rising edge of CE.
CONTROL INTERFACE REGISTERS
DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS 10110 Interface Control BIT 1:0 LABEL FMT[1:0] DEFAULT 10 DESCRIPTION Interface format Select 00 : right justified mode 01: left justified mode 10: I2S mode 11: DSP (early or late) mode
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the opposite of that shown, Figure 10 and. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select between early and late modes. REGISTER ADDRESS 10110 Interface Control BIT 2 LABEL LRP DEFAULT 0 DESCRIPTION In left/right/ I S modes: ADCLRC/DACLRC Polarity (normal) 0 : normal ADCLRC/DACLRC polarity 1: inverted ADCLRC/DACLRC polarity In DSP mode: 0 : Early DSP mode 1: Late DSP mode By default, ADCLRC/DACLRC and DIN is sampled on the rising edge of BCLK and should ideally change on the falling edge. Data sources that change ADCLRC/DACLRC and DIN on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14 and Figure 15. REGISTER ADDRESS 10110 Interface Control BIT 3 LABEL BCP DEFAULT 0 DESCRIPTION BCLK Polarity (DSP modes) 0 : normal BCLK polarity 1: inverted BCLK polarity
2
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The WL[1:0] bits are used to control the input word length. REGISTER ADDRESS 10110 Interface Control BIT 5:4 LABEL WL[1:0] DEFAULT 10
Product Preview
DESCRIPTION Input Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: If 32-bit mode is selected in right justified mode, the WM8774 defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8774 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC channels. Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC, DACLRC and BCLK are outputs and are generated by the WM8774. In Slave mode ADCLRC, DACLRC and BCLK are inputs to WM8774. REGISTER ADDRESS 10111 Interface Control BIT 8 LABEL MS DEFAULT 0 DESCRIPTION Audio Interface Master/Slave Mode select: 0 : Slave Mode 1: Master Mode
MASTER MODE ADCLRC/DACLRC FREQUENCY SELECT
In Master mode the WM8774 generates ADCLRC, DACLRC and BCLK. These clocks are derived from master clock and the ratio of MCLK to ADCLRC and DACLRC are set by ADCRATE and DACRATE. REGISTER ADDRESS 10111 ADCLRC and DACLRC frequency select BIT 2:0 LABEL ADCRATE[2:0] DEFAULT 010 DESCRIPTION Master Mode MCLK:ADCLRC ratio select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs Master Mode MCLK:DACLRC ratio select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs
6:4
DACRATE[2:0]
010
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WM8774
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz, it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. REGISTER ADDRESS 10111 ADC Oversampling Rate BIT 3 LABEL ADCOSR DEFAULT 0 DESCRIPTION ADC oversampling rate select 0: 128x oversampling 1: 64x oversampling
MUTE MODES
Setting DMUTE will apply a `soft' mute to the input of the DAC digital filters. REGISTER ADDRESS 10100 DAC Mute BIT 0 LABEL DMUTE DEFAULT 0 DESCRIPTION DAC Soft Mute select 0 : Normal Operation 1: Soft mute enabled
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 17 Application and Release of Soft Mute Figure 17 shows the application and release of DMUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When DMUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If DMUTE is applied for 1024 or more input samples, the DAC will be muted if IZD is set. When DMUTE is de-asserted, the output will restart immediately from the current input sample. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output.
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Product Preview Each ADC channel also has an individual mute control bit, which mutes the input to the ADC. In addition both channels may be muted by setting ADCMUTE. REGISTER ADDRESS 11001 ADC Mute 11001 ADC Mute Left 11010 ADC Mute Right BIT 7 LABEL ADCMUTE DEFAULT 0 DESCRIPTION ADC MUTE Left and Right 0 : Normal Operation 1: mute ADC left and ADC right ADC Mute select 0 : Normal Operation 1: mute ADC left ADC Mute select 0 : Normal Operation 1: mute ADC right
5
MUTE
0
5
MUTE
0
The Record outputs may be enabled by setting RECEN, where RECEN enables the RECL and RECR outputs. REGISTER ADDRESS 10100 REC Enable BIT 5 LABEL RECEN DEFAULT 0 DESCRIPTION REC Output Enable 0 : REC output muted 1: REC output enabled
DE-EMPHASIS MODE
A digital De-emphasis filter may be applied to the DAC. The De-emphasis filter for each stereo channel is enabled under the control of DEEMP. REGISTER ADDRESS 10101 DAC De-emphasis Control BIT 0 LABEL DEEMPH DEFAULT 0 DESCRIPTION De-emphasis mode select: 0 : Normal Mode 1: De-emphasis Mode
Refer to Figure 26, Figure 27, Figure 28, Figure 29, Figure 30 and Figure 31 for details of the DeEmphasis modes at different sample rates.
POWERDOWN MODE AND ADC/DAC DISABLE
Setting the PDWN register bit immediately powers down the WM8774, including the references, overriding all other powerdown control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised. It is recommended that the 8-channel input mux and buffer, ADC, DAC and output mixers and EVRs are powered down before setting PDWN. REGISTER ADDRESS 11000 Powerdown Control BIT 0 LABEL PDWN DEFAULT 0 DESCRIPTION Power Down Mode Select: 0 : Normal Mode 1: Power Down Mode
The ADC and DACs may also be powered down by setting the ADCD and DACD disable bits. Setting ADCD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCD is reset. Setting DACD disable the DAC and select a low power mode. Resetting DACD will reinitialise the digital filters. REGISTER ADDRESS 11000 Powerdown Control BIT 1 LABEL ADCD DEFAULT 1 DESCRIPTION ADC Disable: 0 : Normal Mode 1: Power Down Mode DAC Disable: 0 : Normal Mode 1: Power Down Mode
2
DACD
1111
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WM8774
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 10011 DAC Channel Control BIT 1 LABEL ATC DEFAULT 0 DESCRIPTION Attenuator Control Mode: 0 : Right channels use Right attenuations 1: Right Channels use Left Attenuations
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS 10011 DAC Channel Control BIT 2 LABEL IZD DEFAULT 0 DESCRIPTION Infinite zero Mute Enable 0 : disable infinite zero mute 1: enable infinite zero Mute
With IZD enabled, applying 1024 consecutive zero input samples to both DAC channels will cause the outputs to be muted. Mute will be removed as soon as any channel receives a non-zero input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS 10011 DAC Control BIT 7:4 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
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DAC ANALOGUE VOLUME CONTROL
Product Preview
The DAC volume may be adjusted independently in both the analogue and digital domain using separate volume control registers. REGISTER ADDRESS 00000 Analogue Attenuation DACL BIT 6:0 7 LABEL LA[6:0] LZCEN DEFAULT 1111111 (0dB) 0 DESCRIPTION Attenuation data for Left channel DACL in 1dB steps. See Table 10 DACL zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of all Attenuation Latches 0: Store LA in intermediate latch (no change to output) 1: Store LA and update attenuation on all channels. Attenuation data for Right channel DACR in 1dB steps. See Table 10 DACR zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of all Attenuation Latches 0: Store RA in intermediate latch (no change to output) 1: Store RA and update attenuation on all channels. Attenuation data for all channel DAC in 1dB steps. See Table 10 Master zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels.
8
UPDATE
Not latched
00001 Analogue Attenuation DACR
6:0 7
RA[6:0] RZCEN
1111111 (0dB) 0
8
UPDATE
Not latched
01000 Master Analogue Attenuation (both channels)
6:0 7
MASTA[6:0] MZCEN
1111111 (0dB) 0
8
UPDATE
Not latched
Table 9 Attenuation Register Map Each DAC channel volume can be controlled digitally in an analogue volume stage after the DAC. Attenuation is 0dB by default but can be set between 0 and -100dB in 1dB steps using the 7 Attenuation control words. All attenuation registers are double latched allowing new values to be prelatched to several channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A master attenuation register is also included, allowing all volume levels to be set to the same value in a single write. Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the prelatch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample. Writing to MASTA[6:0] overwrites any values previously sent to LA[6:0] and RA[6:0]. In addition a zero cross detect circuit is provided for each DAC volume under the control of bit 7 (xZCEN) in each DAC attenuation register. When ZCEN is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises audible clicks and `zipper' noise as the gain values change. A timeout clock is also provided which will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by setting TOD.
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WM8774
BIT LABEL DEFAULT DESCRIPTION
10011 Timeout Clock Disable
3
TOD
0
DAC Analogue Zero cross detect timeout disable 0 : Timeout enabled 1: Timeout disabled
DAC ANALOGUE OUTPUT ATTENUATION
Register bits LA and RA control the left and right channel attenuation of DAC. Register bits MASTA can be used to control attenuation of both channels. Table 8 shows how the attenuation levels are selected from the 7-bit words. L/RA[6:0] 00(hex) : 1A(hex) 1B(hex) : 7D(hex) 7E(hex) 7F(hex) ATTENUATION LEVEL -dB (mute) : -dB (mute) -100dB : -2dB -1dB 0dB
Table 10 Analogue Volume Control Attenuation Levels
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS 01001 Digital Attenuation DACL 01010 Digital Attenuation DACR BIT 7:0 8 LABEL LDA[7:0] UPDATE DEFAULT 11111111 (0dB) Not latched DESCRIPTION Digital Attenuation data for Left channel DACL in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA in intermediate latch (no change to output) 1: Store LDA and update attenuation on all channels Digital Attenuation data for Right channel DACR in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA in intermediate latch (no change to output) 1: Store RDA and update attenuation on all channels. Digital Attenuation data for both DAC channels in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels.
7:0 8
RDA[6:0] UPDATE
11111111 (0dB) Not latched
10001 Master Digital Attenuation (both channels)
7:0 8
ASTDA[7:0] UPDATE
11111111 (0dB) Not latched
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L/RDAX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex) ATTENUATION LEVEL - dB (mute) -127.5dB : : : -0.5dB 0dB
Product Preview
Table 11 Digital Volume Control Attenuation Levels The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS 10011 DAC Control BIT 0 LABEL DZCEN DEFAULT 0 DESCRIPTION DAC Digital Volume Zero Cross Enable: 0: Zero cross detect disabled 1: Zero cross detect enabled
DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS 10010 DAC Phase BIT 1:0 LABEL PH[1:0] DEFAULT 00 Bit 0 1 DESCRIPTION DAC DACL DACR Phase 1 = invert 1 = invert
ADC GAIN CONTROL
Control bits LAG[4:0] and RAG[4:0] control the ADC input gain, allowing the user to attenuate the ADC input signal to match the full-scale range of the ADC. The gain is independently adjustable on left and right inputs. Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to write the same attenuation value to both left and right volume control registers. The ADC volume and mute also applies to the bypass signal path. REGISTER ADDRESS 11001 Attenuation ADCL BIT 4:0 5 LABEL LAG[4:0] MUTE DEFAULT 01100 (0dB) 0 DESCRIPTION Attenuation data for Left channel ADC gain in 1dB steps. See Table 12 Mute for Left channel ADC: 0: Mute off 1: Mute on Setting LRBOTH will write the same gain value to LAG[4:0] and RAG[4:0] Attenuation data for right channel ADC gain in 1dB steps. See Table 12 Mute for Right channel ADC: 0: Mute off 1: Mute on Setting LRBOTH will write the same gain value to RAG[4:0] and LAG[4:0]
6 11010 Attenuation ADCR 4:0 5
LRBOTH RAG[4:0] MUTE
0 01100 (0dB) 0
6
LRBOTH
0
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WM8774
ADC INPUT GAIN
Registers LAG and RAG control the left and right channel gain into the stereo ADC in 1dB steps from +19dB to -12dB Table 8 shows how the attenuation levels are selected from the 5-bit words. L/RAG[6:0] 0 : 01100 : 11111 Table 12 ADC Gain Control ATTENUATION LEVEL -12dB : 0dB : +19dB
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS 10110 ADC control BIT 8 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC Highpass filter disable: 0: Highpass filter enabled 1: Highpass filter disabled
ADC INPUT MUX AND POWERDOWN CONTROL
REGISTER ADDRESS 11011 ADC mux and powerdown control BIT 2:0 6:4 8 LABEL LMX[2:0] RMX[2:0] AINPD DEFAULT 000 000 1 DESCRIPTION ADC left channel input mux control bits (see Table 13) ADC right channel input mux control bits (see Table 13) Input mux and buffer powerdown 0: Input mux and buffer enabled 1: Input mux and buffer powered down
Register bits LMX and RMX control the left and right channel inputs into the stereo ADC. The default is AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 8-channel mux inputs are switched to buffered VMIDADC. LMX[2:0] 000 001 010 011 100 101 110 111 LEFT ADC INPUT AIN1L AIN2L AIN3L AIN4L AIN5L AIN6L AIN7L AIN8L RMX[2:0] 000 001 010 011 100 101 110 111 RIGHT ADC INPUT AIN1R AIN2R AIN3R AIN4R AIN5R AIN6R AIN7R AIN8R
Table 13 ADC Input Mux Control
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OUTPUT SELECT AND ENABLE CONTROL
Product Preview
Register bits MX controls the output selection. The output select block consists of a summing stage and an input select switch for each input allowing each signal to be output individually or summed with other signals and output on the analogue output. The default for the output is DAC playback only. VOUT may be selected to output DAC playback, AUX, analogue bypass or a sum of these using the output select controls MX[2:0]. For example, to select sum of DAC and AUX, set MX[2:0] to 110. The output mixer and EVR can be powered down under control of OUTPD. Setting OUTPD will power off the mixer and EVR and switch the analogue outputs VOUTL/R to VMIDDAC to maintain a dc level on the output. REGISTER ADDRESS 11100 Output mux And Powerdown control BIT 2:0 7 LABEL MX[2:0] OUTPD DEFAULT 001 (DAC playback) 1 DESCRIPTION VOUT Output select (see Figure 18) Mixer and EVR Powerdown select 0: mixer and EVR enabled 1: mixer and EVR powered down
MX[2:0] selects the output for VOUT.
MX[0] DAC MX[1] AUX MX[2] BYPASS VOUT
Figure 18 MX[2:0] Output Select
SOFTWARE REGISTER RESET
Writing to register 11111 will cause a register reset, resetting all register bits to their default values.
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WM8774
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8774 can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER B15 R0(00h) R1(01h) R8(08h) R9(09h) R10(0Ah) R17(11h) R18(12h) R19(13h) R20(14h) R21(15h) R22(16h) R23(17h) R24(18h) R25(19h) R26(1Ah) R27(1Bh) R28(1Ch) R31(1Fh) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B14 B13 B12 B11 B10 B9
B8 UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE x x x x ADCHPD MS x x x AINPD x
B7 LZCEN RZCEN MZCEN
B6
B5
B4
B3 LA[6:0] RA[6:0] MASTA[6:0]
B2
B1
B0
DEFAULT X01111111 X01111111 X01111111 X11111111 X11111111 X11111111 000000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1
0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
LDA[7:0] RDA[7:0] MASTDA[7:0] PHASE[7:0] PL x x x x x
ADCMUTE
TOD RECEN x WL[1:0] x x x x BCP ADCOS R x x
IZD x x LRP
ATC x x
DZCEN DMUTE DEEM P
010010000 000000000 000000000 000100010 000010010 000111110 000001100 000001100
x x x
FMT[1:0] ADCRATE[2:0]
DACRATE[2:0] x LRBOTH LRBOTH x MUTE MUTE RMX[2:0] x x x RESET DATA
DACD LAG[4:0] RAG[4:0]
ADCD
PWDN
x 0 OUTPD
x x
LMX[2:0] MX[2:0]
100000000 110001001 not reset DEFAULT
ADDRESS
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REGISTER ADDRESS 00000 Analogue Attenuation DACL BIT 6:0 LABEL LA[6:0] DEFAULT 1111111 (0dB) 0 DESCRIPTION
Product Preview
Attenuation data for Left channel DACL in 1dB steps. See Table 10 DACL zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of all Attenuation Latches 0: Store DACL in intermediate latch (no change to output) 1: Store DACL and update attenuation on all channels. Attenuation data for Right channel DACR in 1dB steps. See Table 10 DACR zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of all Attenuation Latches 0: Store DACR in intermediate latch (no change to output) 1: Store DACR and update attenuation on all channels. Attenuation data for all DAC gains in 1dB steps. See Table 10 Master zero cross detect enable 0: zero cross disabled 1: zero cross enabled Controls simultaneous update of all Attenuation Latches 0: Store gains in intermediate latch (no change to output) 1: Store gains and update attenuation on all channels. Digital Attenuation data for Left channel DACL in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store LDA in intermediate latch (no change to output) 1: Store LDA and update attenuation on all channels Digital Attenuation data for Right channel DACR in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store RDA in intermediate latch (no change to output) 1: Store RDA and update attenuation on all channels. Digital Attenuation data for both DAC channels in 0.5dB steps. See Table 11 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels. Controls phase of DAC outputs 0: Sets non inverted output phase 1: inverts phase of DAC output
7
LZCEN
8
UPDATE
Not latched
00001 Analogue Attenuation DACR
6:0
RA[6:0]
1111111 (0dB) 0
7
RZCEN
8
UPDATE
Not latched
01000 Analogue Master Attenuation (both channels)
6:0 7
MASTA[6:0] MZCEN
1111111 (0dB) 0
8
UPDATE
Not latched
01001 Digital Attenuation DACL
7:0 8
LDA[7:0] UPDATE
11111111 (0dB) Not latched
01010 Digital Attenuation DACR
7:0 8
RDA[6:0] UPDATE
11111111 (0dB) Not latched
10001 Master Digital Attenuation (both channels) 10010 Phase swaps
7:0
MASTDA[7:0]
11111111 (0dB) Not latched
8
UPDATE
1:0
PH
00
PP Rev 1.0 June 2002 30
Product Preview REGISTER ADDRESS 10011 DAC Control BIT 0 LABEL DZCEN DEFAULT 0 DESCRIPTION DAC Digital Volume Zero Cross Enable: 0: Zero Cross detect disabled 1: Zero Cross detect enabled
WM8774
1
ATC
0
Attenuator Control 0: All DACs use attenuations as programmed. 1: Right channel DACs use corresponding left DAC attenuations Infinite zero detection circuit control and automute control 0: Infinite zero detect automute disabled 1: Infinite zero detect automute enabled DAC Analogue Zero cross detect timeout disable 0 : Timeout enabled 1: Timeout disabled DAC Output Control PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left PL[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
2
IZD
0
3 7:4
TOD PL[3:0]
0 1001
10100 DAC Mute
0
DMUTE
0
DAC channel soft mute enables: 0: mute disabled 1: mute enabled REC Output Enable 0 : REC output muted 1: REC output enabled De-emphasis mode select: 0 : Normal Mode 1: De-emphasis Mode
5
RECEN
0
10101 DAC Control
3:0
DEEMP
0
1:0 10110 Interface Control 2
FMT[1:0]
10
Interface format select
00: right justified mode 01: left justified mode 10: I2S mode 11: DSP mode ADCLRC/DACLRC Polarity or DSP Early/Late mode select Left Justified / Right Justified / I2S 0: Standard DACLRC Polarity 1: Inverted DACLRC Polarity DSP Mode 0: Early DSP mode 1: Late DSP mode
LRP
0
PP Rev 1.0 June 2002 31
WM8774
REGISTER ADDRESS BIT 3 LABEL BCP DEFAULT 0 DESCRIPTION
Product Preview
BITCLK Polarity 0: Normal - DIN, DACLRC & ADCLRC sampled on rising edge of BCLK; DOUT changes on falling edge of BCLK. 1: Inverted - DIN, DACLRC & ADCLRC sampled on falling edge of BCLK; DOUT changes on rising edge of BCLK. Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) ADC Highpass Filter Disable: 0: Highpass Filter enabled 1: Highpass Filter disabled Master Mode MCLK:ADCLRC ratio select: 010: 256fs 011: 384fs 100: 512fs ADC oversample rate select 0: 128x oversampling 1: 64x oversampling Master Mode MCLK:DACLRC ratio select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs Maser/Slave interface mode select 0: Slave Mode - ADCLRC, DACLRC and BCLK are inputs 1: Master Mode - ADCLRC, DACLRC and BCLK are outputs Chip Powerdown Control (works in tandem with ADCD and DACD): 0: All circuits running, outputs are active 1: All circuits in power save mode, outputs muted ADC powerdown: 0: ADC enabled 1: ADC disabled DAC powerdown 0: DAC enabled 1: DAC disabled Attenuation data for left channel ADC gain in 1dB steps Mute for Left channel ADC: 0: Mute off 1: Mute on Setting LRBOTH will write the same gain value to LAG[4:0] and RAG[4:0] Mute for Left and Right channel ADC: 0: Mute off 1: Mute on
5:4
WL[1:0]
10
8
ADCHPD
0
10111 Master Mode control
2:0
ADCRATE[2:0]
010
3
ADCOSR
0
6:4
DACRATE[2:0]
010
8
MS
0
11000 Powerdown Control
0
PWDN
0
1
ADCD
1
2
DACD
1
11001 Attenuation ADCL
4:0 5
LAG[4:0] MUTE
01100 (0dB) 0
6 7
LRBOTH ADCMUTE
0 0
PP Rev 1.0 June 2002 32
Product Preview REGISTER ADDRESS 11010 Attenuation ADCR BIT 4:0 5 LABEL RAG[4:0] MUTE DEFAULT 01100 (0dB) 0 DESCRIPTION
WM8774
Attenuation data for right channel ADC gain in 1dB steps Mute for Right channel ADC: 0: Mute off 1: Mute on Setting LRBOTH will write the same gain value to RAG[4:0] and LAG[4:0] ADC left channel input mux control bits ADC right channel input mux control bits VOUT1 Output select (see Figure 18) Mixer and EVR Powerdown select 0: mixer and EVR enabled 1: mixer and EVR powered down Writing to this register will apply a reset to the device registers.
6 11011 ADC mux control 11100 Output mux and powerdown control 11111 Software reset 2:0 6:4 8 2:0 8:7
LRBOTH LMX[2:0] RMX[2:0] AINPD MX[2:0] OUTPD
0 000 000 1 001 1
[8:0]
RESET
Not reset
Table 14 Register Map Description
PP Rev 1.0 June 2002 33
WM8774 DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband ripple Stopband Stopband Attenuation Group Delay DAC Filter Passband Passband ripple Stopband Stopband Attenuation Group Delay Table 15 Digital Filter Characteristics f > 0.555fs 0.555fs -60 16 dB fs 0.05 dB -3dB 0.487fs 0.05 dB 0.444fs f > 0.5465fs 0.5465fs -65 22 dB fs 0.01 dB -6dB 0 0.5fs 0.01 dB 0.4535fs TEST CONDITIONS MIN TYP MAX UNIT
Product Preview
PP Rev 1.0 June 2002 34
Product Preview
WM8774
0.2
DAC FILTER RESPONSES
0 0.15 -20 0.1
Response (dB) Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 19 DAC Digital Filter Frequency Response - 44.1, 48 and 96kHz
Figure 20 DAC Digital Filter Ripple - 44.1, 48 and 96kHz
0.2 0 0 -20
Response (dB) Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 21 DAC Digital Filter Frequency Response - 192kHz
Figure 22 DAC Digital filter Ripple - 192kHz
PP Rev 1.0 June 2002 35
WM8774 ADC FILTER RESPONSES
0.02
Product Preview
0
0.015 0.01
-20
Response (dB)
Response (dB)
0.005 0 -0.005 -0.01 -0.015 -0.02
-40
-60
-80
0
0.5
1
1.5 Frequency (Fs)
2
2.5
3
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 23 ADC Digital Filter Frequency Response
Figure 24 ADC Digital Filter Ripple
ADC HIGH PASS FILTER
The WM8774 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial.
H(z) =
1 - z-1 1 - 0.9995z-1
0
Response (dB)
-5
-10
-15
0
0.0005
0.001 Frequency (Fs)
0.0015
0.002
Figure 25 ADC Highpass Filter Response
PP Rev 1.0 June 2002 36
Product Preview
WM8774
1 0.5
DIGITAL DE-EMPHASIS CHARACTERISTICS
0
-2 0
Response (dB)
Response (dB)
-4
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 26 De-Emphasis Frequency Response (32kHz)
0
Figure 27 De-Emphasis Error (32KHz)
0.4 0.3
-2 0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 28 De-Emphasis Frequency Response (44.1KHz)
0
Figure 29 De-Emphasis Error (44.1KHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 30 De-Emphasis Frequency Response (48kHz)
Figure 31 De-Emphasis Error (48kHz)
PP Rev 1.0 June 2002 37
WM8774 EXTERNAL CIRCUIT CONFIGURATION
Product Preview
In order to allow the use of 2V rms and larger inputs to the ADC and AUX inputs, a structure is used that uses external resistors to drop these larger voltages. This also increases the robustness of the circuit to external abuse such as ESD pulse. Figure 32 shows the ADC input multiplexor circuit with external components allowing 2Vrms inputs to be applied.
5K
AINOPL
10uF 10K
AINVGL AIN1L
10uF
10K
AIN2L
10uF 10K
AIN3L
10uF
10K
AIN7L
10uF 10K
AIN8L
SOURCE SELECTOR INPUTS
5K
AINOPR
10uF 10K
AINVGR AIN1R
10uF
10K
AIN2R
10uF 10K
AIN3R
10uF
10K
AIN7R
10uF 10K
AIN8R
Figure 32 ADC Input Multiplexor Confiuration
10K
DAC AUX BYPASS INPUTS
10uF
MX[0]
DACL/R
10K
MX[1]
AUXL/R BYPASSL/R
10K
MX[2]
10K
Figure 33 5.1 Channel Input Multiplexor Configuration
PP Rev 1.0 June 2002 38
Product Preview
WM8774
RECOMMENDED EXTERNAL COMPONENTS
It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8774 produces much less high frequency output noise than competitors devices). This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Figure 34 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results.
4.7k 4.7k
+VS
_
51 10uF 1.8k 7.5K
+
+
1.0nF 47k 680pF -VS
Figure 34 Recommended Post DAC Filter Circuit
PP Rev 1.0 June 2002 39
WM8774 PACKAGE DIMENSIONS
FT: 64 PIN TQFP (10 x 10 x 1.0 mm)
b e
48 33
Product Preview
DM027.A
49
32
E1
E
64
17
1
16
4
c
D1 D L
A
A2
A1
-Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L
4
ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 1.00 1.05 0.95 0.27 0.17 0.22 0.09 ----0.20 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ACD. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
PP Rev 1.0 June 2002 40
Product Preview
WM8774
IMPORTANT NOTICE
Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is neither responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics Ltd 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
PP Rev 1.0 June 2002 41
WM8774 REVISION HISTORY
DATE REV ORIGINATOR CHANGES
Product Preview
PP Rev 1.0 June 2002 42

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