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ADVANCE INFORMATION
WCMC1616V9X
Features
* 1T Cell, PSRAM Architecture * High speed: 70 ns * Wide Voltage range: -- VCC range: 2.7V to 3.3V * Low active power -- Typical active current: 2 mA @ f = 1 MHz -- Typical active current: 13 mA @ f = fMAX * Low standby power * Automatic power-down when deselected
Functional Description[1]
The WCMC1616V9X is a high-performance CMOS pseudo static RAMs (PSRAM) organized as 1M words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life TM
(MoBL(R) ) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption by more than 99% when deselected using CE LOW, CE 2 HIGH or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O 1 5) are placed in a high-impedance state when: deselected (CE HIGH, CE 2 LOW OE is deasserted HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling even when the chip is selected (Chip Enable CE LOW, CE 2 HIGH and both BHE and BLE are LOW). Reading from the device is accomplished by asserting the Chip Enables (CE LOW and CE 2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O 0 to I/O 7. If Byte High Enable (BHE ) is LOW, then data from memory will appear on I/O8 to I/O 15 . See the Truth Table for a complete description of read and write modes.
1Mb x 16 Pseudo Static RAM
Logic Block Diagram
DATA IN DRIVERS A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
RO W DECODER
1M x 16 RAM Array 1T
SENSE AMPS
I/O0 -I/O7 I/O8 -I/O15
COLUMN DECODER
A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19
BHE WE OE BLE CE2 CE
CE2 CE
Pow er Down Circuit
BHE BLE
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress .com.
WeidaSemiconductor, Inc. Document #: 38-14027 Rev. **
Revised August 22, 2001
ADVANCE INFORMATION
Pin Configuration[2, 3, 4]
WCMC1616V9X
FBGA Top View
1 BLE I/O 8 I/O 9 V SS V CC
2 O E BHE I/O 10 I/O 11
3 A 0 A 3 A5 A17
4 A 1 A 4 A6 A 7 A 16 A 15 A 13 A 10
5 A 2 CE I/O 1 I/O 3 I/O 4 I/O 5 W E A 11
6 CE 2 I/O 0 I/O 2 VCC VSS I/O 6 I/O 7 NC A B C D E F G H
I/O DNU 12 A 14 A 12 A 9
I/O 14 I/O 13 I/O 15 A18 A19 A 8
Note: 2. DNU pins are to be left floating or tied to Vss. 3. Ball H6 is the address expansion pin for the 32Mb density. 4. NC "no connect" - not connected internally to the die.
Document #: 38-14027 Rev. **
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ADVANCE INFORMATION
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied ............................................... -40C to +85C Supply Voltage to Ground Potential ................. -0.4V to 4.6V
WCMC1616V9X
DC Voltage Applied to Outputs in High-Z State [5, 6, 7] ......................... DC Input Voltage
[5, 6, 7]
.....-0.4V to 3.3V ....-0.4V to 3.3V
......................
Output Current into Outputs (LOW).............................20 mA Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .....................................................> 200 mA
Operating Range[9]
Range Industrial Ambient Temperature (T A) -25o C to +85o C VCC 2.7V to 3.3V
Product Portfolio
Power Dissipation VCC Range(V) Product WCMC1616V9X-FI70 Min. 2.7 Typ. 3.0 Max. 3.3 Operating, Icc (mA) f = 1 MHz f = fMAX Typ. [8] 2 Max. 3.5 Typ. [8] 13 Max. 17 Standby, ISB2 (A) Typ.[8] 80 Max. 150
Speed (ns) 70
Notes: 5. VIH(MAX) = V C C + 0.5V for pulse durations less than 20ns. 6. VIL(MIN) = -0.5V for pulse durations less than 20ns. 7. Overshoot and undershoot specifications are characterized and are not 100% tested. 8. Typical values are included for reference only and are not guranteed or tested. Typical values are measured at VCC = V C C (typ) and TA = 25C 9. Vcc must be at minimal operational levels before inputs are turned ON.
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ADVANCE INFORMATION
DC Electrical Characteristics (Over the Operating Range)
Parameter Vcc VOH VOL VIH VIL I IX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current - CMOS Inputs F=0 GND < VI < Vcc GND < VO < Vcc, Output Disabled f = fMAX = 1/tRC f = 1 MHz Vcc = 3.3V, IOUT = 0mA, CMOS level Test Conditions Supply Voltage IOH = -1 mA IOL = 2 mA
WCMC1616V9X
WCMC1616V9X-70 Min. Typ. [8] Max. 2.7 VCC - 0.4 0.4 0.8*VCC -0.4 -1 -1 13 2 100 VCC + 0.4 0.4 +1 +1 17 3.5 525 3.3
Unit V V V V V A A mA
ISB1
CE > VCCQ - 0.2V, CE 2 < 0.2V VIN > V CCQ - 0.2V, VIN < 0.2V, f = f MAX(Address and Data Only), f = 0 (OE, WE, BHE and BLE) CE > VCCQ - 0.2V, CE 2 < 0.2V VIN > VCCQ - 0.2V or VIN < 0.2V, f = 0, VCC =3.3V
A
ISB2
Automatic CE Power-down Current - CMOS Inputs
80
150
A
Capacitance [10]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions T A = 25C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF
Thermal Resistance[10]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board FBGA 55 17 Unit C/W C/W
Note: 10. Tested initially and after design or process changes that may affect these parameters.
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ADVANCE INFORMATION
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10%
WCMC1616V9X
Fall Time = 1 V/ns
Equivalento: t
THE VENINEQUIVALENT RTH OUTPUT VTH
Parameters R1 R2 RTH VTH
3.0V Vcc 1179 1941 733 1.87
Unit W W W V
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ADVANCE INFORMATION
Switching Characteristics (Over the Operating Range)[11]
WCMC1616V9X
WCMC1616V9X-70 Parameter Read Cycle tRC tA A t OHA tACE t DOE t LZOE t HZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK Write Cycle tWC tAW tHA tS A tPWE tBW tSD tHD tHZWE t LZWE
[13]
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[12, 14] OE HIGH to High Z[12, 14] CE LOW and CE2 HIGH to Low Z CE HIGH and CE 2 LOW to High Z[12, 14] BLE /BHE LOW to Data Valid BLE/BHE LOW to Low Z [12, 14] BLE/BHE HIGH to High-Z [12, 14] Address Skew Write Cycle Time CE LOW and CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High Z[12, 14] WE HIGH to Low Z[12, 14]
[12, 14]
Min. 70
Max.
Unit ns
70 10 70 35 5 25 5 25 70 5 25 10 70 55 55 0 0 55 55 25 0 25 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSCE
Notes: 11. Test conditions assume signal transition time of 1V/ns or higher , timing reference levels of V CC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL /I O H and 30-pF load cpacitance 12. t HZOE, t HZCE, t HZBE and t HZWE transitions are measured when the outputs enter a high-impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write 14. High-Z and Low-Z parameters are characterized and are not 100% tested.
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ADVANCE INFORMATION
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
[15]
WCMC1616V9X
tRC ADDRESS tSK DATA OUT tOHA tAA DATA VALID
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)
[15]
ADDRESS tRC
CE 1
tSK
tPD tHZCE t ACE
CE2
BHE/BLE
tDBE tLZBE
OE
t HZBE
DATA OUT VC C SUPPLY CURRENT
tDOE tLZOE HIGH IMPEDANCE t LZCE tPU 50%
t HZOE HIGH IMPEDANCE ICC I SB
DATA VALID
50%
Note: 15. WE is HIGH for Read Cycle.
Document #: 38-14027 Rev. **
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ADVANCE INFORMATION
Write Cycle No. 1(WE Controlled)[13, 14, 16, 17, 18,]
tWC ADDRESS tSCE
CE1
WCMC1616V9X
CE 2 tAW tSA
WE
tHA tPWE
BHE/BLE
tBW
OE
t SD DATAI/O
DON'T CARE
tHD
VALID DATA tHZOE
Write Cycle No. 2 (CE Controlled)[13, 14, 16, 17, 18]
tWC ADDRESS tSCE CE 1 CE 2 tSA tAW tPWE WE tBW tHA
BHE/BLE
OE t SD DATAI/O
DON'T CARE
tH D
VALID DATA tHZOE
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ADVANCE INFORMATION
WCMC1616V9X
Notes: 16. Data I/O is high impedance if OE = VIH . 17. If Chip Enable goes INACTIVE simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18] tWC ADDRESS t SCE
CE1
CE 2
BHE/ BLE
tBW tAW tSA tPWE tHA
WE
t SD DATAI/O
DON'T CARE
tHD
VALID DATA tHZWE tLZWE
Write Cycle No. 4 (BHE /BLE Controlled, OE LOW)[17, 18] tWC ADDRESS CE1 CE2
tSCE tAW tBW
tHA
BHE/BLE tSA WE tPWE tSD DATA I/O
DON'T CARE
t HD
VALID DATA
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ADVANCE INFORMATION
Truth Table [19]
CE H X X L L L L L L L L L CE 2 H H L H H H H H H H H H WE X X L H H H H H H L L L OE X X X L L L H H H X X X BHE X H X L H L L H L L H L BLE X H X L L H L L H L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0 -I/O1 5) Data Out (I/O0 -I/O7 ); I/O8 -I/O15 in High Z Data Out (I/O8 -I/O1 5); I/O0 -I/O7 in High Z High Z High Z High Z Data In (I/O0 -I/O15 ) Data In (I/O0 -I/O7); I/O8 -I/O15 in High Z Data In (I/O8 -I/O15 ); I/O0 -I/O 7 in High Z Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled
WCMC1616V9X
Power Standby (I SB ) Standby (I SB ) Standby (I SB ) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only)
Notes: 19. H = V IH, L = VIL, X = Don't Care
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ADVANCE INFORMATION
Ordering Information
Speed (ns) 70 Ordering Code WCMC1616V9X-FI70 Package Name BV48A Package Type
WCMC1616V9X
Operating Range Industrial
48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm)
Package Diagrams
48-Ball (6 mm x 8 mm x 1.2 mm) FBGA BA48K
51-85193-*A
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ADVANCE INFORMATION
WCMC1616V9X
MoBL is a registered trademark of Cypress Semiconductor. MoBL2, MoBL3, MoBL4, and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-14027 Rev. **
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(c) Weida Semiconductor, Inc., 2003. The information contained herein is subject to change without notice. Weida Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Weida Semiconductor product. Nor does it convey or imply any license under patent or other rights. Weida Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Weida Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Weida Semiconductor against all charges.
ADVANCE INFORMATION
Document History Table
Document Title: WCMC1616V9X MoBL3TM(R) 16Mb (1Mb x 16) Pseudo Static RAM Document Number: 38-14027 REV. ** ECN NO. 130544 Issue Date 10/16/03 Orig. of Change MPR New Data Sheet
WCMC1616V9X
Description of Change
Document #: 38-14027 Rev. **
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