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R EM MICROELECTRONIC-MARIN SA V6310 Ultra Low Power 3-Pin Voltage Window Surveillance with Time-out Features n n n n n n n n n Voltage Window monitoring Clear microprocessor restart after power up Processor reset at power down Reset output guaranteed down to VDD = 1 V - 40 to +85 OC temperature range On request extended temperature range, -40 to +125 OC On-chip oscillator No external components required Push-pull or Open drain output 1) Typical Operating Configuration VDD n Low power consumption: typ. 3 mA at VDD = 5 V VDD VDD RES or RES RES Microor RES processor VSS V6310 VSS n TO-92, SOT-23 5L and SOT-223 packages n Pin compatible with DS 1233 A in TO-92 and SOT-223 GND 1) On request For Open drain version: Fig. 1 Description The V6310 is a CMOS device which monitors the supply voltage of any electronic system, and generates the appropriate Reset signal. The g ap between the two thresholds defines the allowed voltage range. As long as VDD stays inside this voltage window, the output stays inactive. If V DD drops below VTHlow, or rises above VTHhigh, the output gets active. When V DD enters into the allowed range, the output remains active for an additional 50 ms (typ.). This allows the system to stabilize before getting fully active. The lower thresho ld voltage may be obtained in different versions: 2.0 V to 6 V 2.4 V to 6 V 2.8 V to 6 V 3.5 V to 6 V 4.0 V to 6 V 4.5 V to 6 V Pin Assignment TO-92 View Flat Front V6310 1 2 3 VDD RES VSS or RES SOT-223 1) SOT-23 5L VSS 4 Applications All microprocessor applications where an automatic restart is required: n Computer electronics n White / Brown goods n Automotive electronics n Industrial electronics n Telecom systems n Hand-held systems NC VSS NC 3 2 1 V6310 1 2 3 4 V6310 5 RES or VSS RES 1) VDD RES or RES VDD Fig. 2 On request 1 R V6310 Absolute Maximum Ratings Parameter Voltage at VDD to VSS Min. voltage at RES or RES Max. voltage at RES or RES Storage temperature range Symbol VDD Vmin Vmax TSTO Conditions -0.3V to+10 V VSS - 0.3 V VDD + 0.3 V -65O to +150 OC Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Operating Conditions Parameter Operating temperature Positive supply voltage 1) Symbol Min. Typ . Max. Units TA VDD -40 1 +125 8 O C V Table 2 1) The maximum operating temperature is confirmed by sampling at initial device qualification. Electrical Characteristics TA = -40 to +85 OC, unless otherwise specified Parameter Supply current 1) Symbol IDD IDD IDD VTHlow VTHlow VTHlow VTHlow VTHlow VTHlow VTHhigh VHYS VOL VOL VOL VOH VOH VOH ILEAK Test Conditions VDD = 2 V VDD = 5 V VDD = 8 V Version: A,G,M Version: B,H,N Version: C,I,O Version: D,J,P Version: E,K,Q Version: F,L,R Min. Min. at 25 OC Typ. 1.5 3.0 5.2 1.95 2.32 2.73 3.42 3.88 4.42 6.10 25 175 140 20 4.5 2.6 950 0.05 Max. Max. at 25 OC 2.1 3.9 6.8 2.04 2.41 2.86 3.59 4.08 4.67 6.42 3.1 5.7 10.0 2.17 2.55 3.03 3.80 4.32 4.95 6.82 400 300 90 Units mA mA mA V V V V V V V mV mV mV mV V V mV mA Table 3 Threshold Low Voltage Threshold High Voltage Threshold hysteresis RES Output Low Level 1.77 2.09 2.48 3.11 3.55 4.05 5.58 1.84 2.18 2.59 3.23 3.70 4.22 5.79 RES Output High Level Output leakage current 1) 2) 2) VDD = 5 V, IOL = 8 mA VDD = 3 V, IOL = 4 mA VDD = 1 V, IOL = 50 mA VDD = 5 V, IOH= -8 mA VDD = 3 V, IOH = -4 mA VDD = 1 V, IOH = -100 mA VDD = 5.5 V 4.3 2.3 850 1 RES or RES open Only for Open drain versions Timing Characteristics VDD = 5.0 V, TA = -40 to +85OC, unless otherwise specified Parameter Power on reset time Sensitivity around VTHhigh 3) Sensitivity around VTHlow Reaction time around VTHhigh 3) Reaction time around VTHlow 3) Symbol tPOR tSEN high tSEN low TRhigh TRlow Test Conditions for VDD = 5 V to 7 V in 5 ms for VDD = 5 V to 3 V in 5 ms for VDD = 5 V to 7 V in 5 ms for VDD = 5 V to 3 V in 5 ms Min. 25 18 20 20 22 Typ. 50 0.8 tRhigh 0.8 tRlow 55 75 Max. 75 Units ms ms ms ms ms 90 150 Tested on versions with VTHlow higher than 3 V Table 4 2 R V6310 Timing Waveforms VDD VTHhigh VTHlow tSENhigh tSENlow 1V tPOR tRhigh tPOR tRlow t RES t RES Logic "0" t Fig.3 Logic "1" Logic "0" Logic "1" Block Diagram VDD Voltage Reference + Reset Logic Timer Oscillator RES or RES Vss Pin Description TO-92 Pin 1 2 3 Name VDD RES or RES VSS Function Positive Supply Reset output Supply ground Table 5 SOT-23 5L Pin 1 2 3 4 5 Name NC VSS NC RES or RES VDD Function No connection Supply ground No connection Reset output Positive supply Table 6 + SOT-223 Pin 1 2 3 4* 1) Fig.4 Name RES or RES VSS VDD VSS Function Reset output Supply ground Positive Supply Supply ground Table 7 * Internally connected to pin 2 1) On request 3 R V6310 Ordering Information The V 6310 is available with Push-pull or Open drain output stage and Reset active low or high. Ordering form: V6310 Version letter definition Output stage Threshold Low Voltage [V] 2.0 2.4 2.8 3.5 4.0 4.5 1) Push-pull, Reset active low A 1) Push-pull, Reset active high G 1) Open drain, Reset active low M B 1) H 1) N 1) C 1) I O 1) D E F 1) 1) 1) J K L 1) 1) 1) P QR 1) 1) 1) Table 7 1) V6310 O TO-92 When ordering, please specify the complete part number. EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date O 2000 EM Microelectronic-Marin SA, 10/00, Rev. D/317 4 |
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