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V104
10 BIT LVDS RECEIVER FOR VIDEO
General Description
The V104 10 Bit LVDS Receiver for Video is designed to support video data transmission between display engines and video processing engines for television and projector applications. The V104 supports up to WXGA resolutions for Plasma, Rear Projection, Front Projection, CRT and LCD applications. The V104 converts the 6 LVDS (Low Voltage Differential Signaling) video data stream pairs to 35 CMOS/TTL data bits with a rising or falling edge clock. The clock edge selection is performed using a dedicated pin. In conjunction with the V103 transmitter, the V104 can transmit 10 bits per color (R, G, B) along with 5 bits of control and timing data (HSYNC, VSYNC, DE, CNTL1, CNTL2) over a low EMI, low bus width connection including connectors and standard LVDS cabling.
PRELIMINARY
Features
* * * * * * * * *
Pin & function compatible with the THC63LVD104A Wide pixel clock range: 8 - 90 MHz Supports resolutions from 480p to WXGA Internal PLL does not require external loop filter Clock edge selection for TTL alignment selectable Power down mode Single 3.3V supply Low power consumption CMOS design 64-pin TQFP lead free package
Block Diagram
LVDS Input
RA+/7
CMOS/TTL Output
7
RA6-RA0 RB6-RB0 RC6-RC0 RD6-RD0 RE6-RE0 CLKOUT
RB+/RC+/RD+/RE+/RCLK+/(8 to 90 MHz)
Serial to Parallel
7
7
7
PLL
CMOS/TTL Input
TEST PD OE R/F
V104 Datasheet
1
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
Pin Assignment
PVCC PGND RE+ RERD+ RDLGND RCLK+ RCLKRC+ RCLVCC RB+ RBRA+ RA64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Pin Descriptions
Pin Number
50, 49 52, 51 55, 54 60, 59 62, 61 57, 56 40, 41, 42, 43, 45, 46, 47 32, 33, 34, 35, 36, 38, 39 22, 24, 25, 26, 27, 28, 29 14, 15, 17, 18, 19, 20, 21
Pin Name
RA+, RARB+, RBRC+, RCRD+, RDRE+, RERCLK+, RCLKRA6 ~ RA0 RB6 ~ RB0 RC6 ~ RC0 RD6 ~ RD0
Pin Type
LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT OUT LVDS Data In LVDS Data In LVDS Data In LVDS Data In LVDS Data In LVDS Clock In CMOS/TTL Data Outputs CMOS/TTL Data Outputs CMOS/TTL Data Outputs CMOS/TTL Data Outputs
V104 Datasheet
RD4 RD3 RD2 RD1 RD0 RC6 VCC RC5 RC4 RC3 RC2 RC1 RC0 GND CLKOUT RB6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND TEST PD OE R/F RE6 RE5 RE4 VCC RE3 RE2 RE1 RE0 RD6 RD5 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64-pin TQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCC RA0 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VCC RB2 RB3 RB4 RB5
Pin Description
2
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
Pin Number
6, 7, 8, 10, 11, 12, 13 2 3 4 5 9, 23, 37, 48 31 1, 16, 30, 44 53 58 64 63
PRELIMINARY
Pin Name
RE6 ~ RE0 TEST PD OE R/F VCC CLKOUT GND LVCC LGND PVCC PGND
Pin Type
OUT IN IN IN IN Power OUT Ground Power Ground Power Ground CMOS/TTL Data Outputs. Not used. Tie LOW.
Pin Description
HIGH: normal operation; LOW: Power down (all outputs are "L"). HIGH: Output enable (normal operation); LOW: Output disable (all outputs are high impedance). Output Clock triggering edge select. High: Rising edge; Low: Falling edge. Power supply pins for TTL outputs and digital circuitry. Clock out. Ground pins for TTL outputs and digital circuitry. Power supply pins for LVDS inputs. Ground pins for LVDS inputs. Power supply pin for PLL circuitry. Ground pin for PLL circuitry.
PD
0 0 0 0 1 1 1 1
R/F
0 0 1 1 0 0 1 1
OE
0 1 0 1 0 1 0 1
Data Outputs (Rxn)
High impedance All 0 High impedance All 0 High impedance Data Out High impedance Data Out
CLKOUT
High impedance Fixed Low High impedance Fixed Low High impedance Latches output data on falling edge High impedance Latches output data on rising edge
**Rxn x = A, B, C, D, E n = 0, 1, 2, 3, 4, 5, 6
V104 Datasheet
3
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
External Components
The V104 requires no external components.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V104. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item
Supply Voltage, VCC CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Output Current Storage Temperature Junction Temperature Soldering Temperature (10 seconds) Maximum Power Dissipation @ +25C -0.3 V to +4.0 V -0.3 V to VCC+0.3 V -0.3 V to VCC+0.3 V -0.3 V to VCC+0.3 V -30 mA to 30 mA -55 to +125C 125C 260C 1.0 W
Rating
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.0
Typ.
Max.
+70 +3.6
Units
C V
V104 Datasheet
4
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
Electrical Characteristics
VDD=3.3 V 10%, Ambient temperature 0 to +70C Parameter
CMOS/TTL DC Specifications Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Current LVDS Receiver DC Specifications Differential Input High Threshold Differential Input Low Threshold Input Current VTH VTL IINL VOC = 1.2 V VOC = 1.2 V VIN = 2.4 V / 0V VIN = 3.6 V -100 20 100 mV mV A VIH VIL VOH VOL IINC IOH = -4 mA (data) IOH = -8 mA (clock) IOH = -4 mA (data) IOH = -8 mA (clock) 0VSymbol
Conditions
Min.
Typ.
Max.
Units
Parameter
Supply Current Receiver Supply Current (Gray Scale Pattern) Receiver Supply Current (Checker Pattern) Receiver Power Down Supply Current
Symbol
IRCCG IRCCW IRCCS
Conditions
fCLKOUT = 90 MHz fCLKOUT = 90 MHz PD = L CL=8 pF, VCC = 3.3 V CL=8 pF, VCC = 3.3 V
Typ.
70 112
Max.
Units
mA mA
10
A
V104 Datasheet
5
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
Incremental Pattern (Gray Scale)
CLKOUT Rx0
PRELIMINARY
Rx1
Rx2
Rx3
Rx4
Rx5
Rx6
X = A, B, C, D, E
Toggle Pattern (Checker)
CLKOUT Rx0
Rx1
Rx2
Rx3
Rx4
Rx5
Rx6
X = A, B, C, D, E
V104 Datasheet
6
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
Parameter
Switching Characteristics CLKOUT Period CLK IN High Time CLK IN Low Time TTL Data Setup to CLKOUT TTL Data Hold from CLKOUT TTL Low to High Transition Time TTL High to Low Transition Time Input Data Position0 Input Data Position1
Symbol
tRCP tRCH tRCL tRS tRH tTLH tTHL tRIP1 tRIP0
Min.
11.1
Typ.
T (T-1)/2 (T-1)/2
Max.
125.0
Units
ns ns ns ns ns
4.5 2.5 1.0 1.0 -0.25 tRCIP -0.25 7 t 2 RCIP -0.25 7 t 3 RCIP -0.25 7 t 4 RCIP -0.25 7 t 5 RCIP -0.25 7 t 6 RCIP -0.25 7 0.0 tRCIP 7 t 2 RCIP 7 t 3 RCIP 7 t 4 RCIP 7 t 5 RCIP 7 t 6 RCIP 7 2.0 2.0 +0.25 tRCIP +0.25 7 t 2 RCIP +0.25 7 t 3 RCIP +0.25 7 t 4 RCIP +0.25 7 t 5 RCIP +0.25 7 t 6 RCIP +0.25 7 10.0 11.1 0 125.0 1.6
ns ns ns ns
Input Data Position2
tRIP6
ns
Input Data Position3
tRIP5
ns
Input Data Position4
tRIP4
ns
Input Data Position5
tRIP3
ns
Input Data Position6 Phase Lock Loop Set CLKIN Period Device-device data output skew
tRIP2 tRPLL tRCIP
ns ms ns ns
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
53 40 33 8
Max.
Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
JC
V104 Datasheet
7
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
AC Timing Diagrams
TTL Outputs
80%
80%
20% tTLH TTL Output
CL = 8 pF
20% tTHL
TTL Output Load
TTL Outputs
2.0 V
tRCH
2.0 V 2.0 V
tRCL
R/F = L
CLK OUT
0.8 V 0.8 V
tRCP tRS
2.0 V 0.8 V
R/F = H
tRH
2.0 V 0.8 V
Rxn
x = A, B, C, D, E n = 0, 1, 2, 3, 4, 5, 6
Phase Lock Loop Set Time
3.0 V VCC RCLK+/2.0 V PD
tRPLL
2.0 V CLKOUT
V104 Datasheet
8
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
Power Up Sequence
Sequence 1 VCC PVCC LVCC PD Recommended PD Pin Circuit VCC
100 kohm VCC/2 Min 100 sec VCC/2
PD Pin
0.1 F
Sequence 2
3.0 V VCC
VCC PVCC GND LVCC PD
GND GND
VCC
V104 Datasheet
9
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
LVDS Inputs
tRIP2 tRIP3 tRIP4 tRIP5 tRIP6 tRIP0 tRIP1
Rx+/-
Rx6
Rx5
Rx4
Rx3
Rx2
Rx1
Rx0
Rx6
Rx5
Rx4
Rx3
Rx2
Rx1
RCLK+ VDIFF = 0V VDIFF = 0V
tRCIP
x = A, B, C, D, E
LVDS Inputs
VDIFF = 0V RCLK+ (Differential RA+/RB+/RA3' RA2' RA1' RA0' RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA6" VDIFF = 0V
RB3'
RB2'
RB1' RB0'
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RB6"
RC+/-
RC3' RC2'
RC1' RC0'
RC6
RC5
RC4
RC3
RC2
RC1
RC0 RC6"
RD+/-
RD3' RD2'
RD1' RD0'
RD6
RD5
RD4
RD3
RD2
RD1
RD0 RD6"
RE+/-
RE3'
RE2'
RE1' RE0'
RE6
RE5
RE4
RE3
RE2
RE1
RE0
RE6"
Previous Cycle
Current Cycle
Next Cycle
tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2
V104 Datasheet
10
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V104
10 BIT LVDS RECEIVER FOR VIDEO
PRELIMINARY
Package Outline and Package Dimensions (64-pin TQFP)
Package dimensions are kept current with JEDEC Publication No. 95, variation ACD.
SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L MIN/MAX 64 -- / 1.20 0.05 / 0.15 0.95 / 1.05 0.17 / 0.27 0.09 / 0.20 12.00 BASIC 10.00 BASIC 7.50 Ref. 12.00 BASIC 10.00 BASIC 7.50 Ref. 0.50 BASIC 0.45 / 0.75 0 / 7 -- / 0.08 -
ALL DIMENSIONS ARE IN MILLIMETERS.
ccc D3&E3
Ordering Information
Part / Order Number V104YLF V104YLFT Marking V104YLF V104YLF Shipping Packaging
Tubes Tape and Reel
Package
64-pin TQFP 64-pin TQFP
Temperature
0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
V104 Datasheet
11
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m

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