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USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator
April 2005 Revised May 2005
USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator
General Description
This chip provides a USB Transceiver functionality with a voltage regulator that is compliant to USB Specification Rev 2.0. this integrated 5V to 3.3V regulator allows interfacing of USB Application specific devices with supply voltages ranging from 1.65V to 3.6V with the physical layer of Universal Serial Bus. It is capable of operating at 12Mbits/s (full speed) data rates and hence is fully compliant to USB Specification Rev 2.0. The Vbusmon terminal allows for monitoring the Vbus line. The USB1T1103 also provides exceptional ESD protection with 15kV contact HBM on D, D terminals.
Features
s Complies with Universal Serial Bus Specification 2.0 s Integrated 5V to 3.3V voltage regulator for powering VBus s Utilizes digital inputs and outputs to transmit and receive USB cable data s Supports full speed (12Mbits/s) data rates s Ideal for portable electronic devices s MLP technology package (16 terminal) with HBCC footprint s 15kV contact HBM ESD protection on bus terminals s Supports disable mode and is functionally equivalent to Philips ISP1102
Applications
* PDA * PC Peripherals * Cellular Phones * MP3 Players * Digital Still Camera * Information Appliance
Ordering Code:
Order Number USB1T1103MPX USB1T1103MHX Package Number MLP14D MLP16HB Package Description Pb-Free 14-Terminal Molded Leadless Package (MLP), 2.5mm Square Pb-Free 16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square
Pb-Free package per JEDEC J-STD-020B.
(c) 2005 Fairchild Semiconductor Corporation
DS500905
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USB1T1103
Logic Diagram
Connection Diagrams
MLP16 GND Exposed Diepad MLP14 GND Exposed Diepad
(Bottom View) (Bottom View)
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USB1T1103
Terminal Descriptions
Terminal Number MLP14 1 MLP16 1 Terminal Name OE I/O I Terminal Description Output Enable: Active LOW enables the transceiver to transmit data on the bus. When not active the transceiver is in the receive mode (CMOS level is relative to VCCIO) Receive Data Output: Non-inverted CMOS level output for USB differential Input (CMOS output level is relative to VCCIO). Driven LOW when SUSPN is HIGH; RCV output is stable and preserved during SE0 condition. Single-ended D receiver output VP (CMOS level relative to VCCIO): Used for external detection of SE0, error conditions, speed of connected device; Terminal also acts as drive data input Vpo (see Table 1 and Table 2). Output drive is 4 mA buffer. Single-ended D receiver output Vm (CMOS level relative to VCCIO): Used for external detection of SE0, error conditions, speed of connected device; Terminal also acts as drive data input Vmo (see Table 1 and Table 2). Output drive is 4 mA buffer. Suspend: Enables a low power state (CMOS level is relative to VCCIO). While the SUSPND terminal is active (HIGH) it will drive the RCV terminal to logic "0" state. No Connect Supply Voltage for digital I/O terminals (1.65V to 3.6V): When not connected the D and D terminals are in 3-STATE. This supply bus is totally independent of VCC (5V) and VREG (3.3V), and must never exceed the VREG (3.3) voltage. For VCCIO disconnected the O/O terminals are HIGH Impedance and the VPU (3.3V) is turned off. O Vbus monitor output (CMOS level relative to VCCIO): When Vbus ! 4.1V then Vbusmon HIGH and when Vbus 3.6V then Vbusmon LOW. If SUSPND HIGH then Vbusmon is pulled HIGH. Data , Data : Differential data bus conforming to the USB standard. Terminals are HIGH Impedance for bus powered mode when Vbus 3.6V. For ByPass Mode then HIGH Impedance when VREG/ Vbus VREG minimum. No Connect No Connect Internal Regulator Option: Regulated supply output voltage (3.0V to 3.6V) during 5V operation; decoupling capacitor of at least 0.1 PF is required. Regulator ByPass Option: Used as supply voltage input for 3.3V operation. Internal Regulator Option: Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB line Vbus. Regulator ByPass Option: Connected to VREG (3.3V) Pull-up Supply Voltage (3.3V r 10%): Connect an external 1.5k: resistor on D (FS data rate); Terminal function is controlled by Config input terminal: Config LOW VPU (3.3V) is floating (HIGH Impedance) for zero pull-up current. Config HIGH VPU (3.3V) 3.3V; internally connected to VREG (3.3V). VPU is OFF in disable mode. I GND USB connect or disconnect software control input. Configures 3.3V to external 1.5k: resistor on D when HIGH. GND supply down bonded to exposed diepad to be connected to the PCB GND.
2
2
RCV
O
3
3
Vp/Vpo
I/O
4
4
Vm/Vmo
I/O
5
5
SUSPND
I
-- 6
6 7
NC VCCIO
7
8
Vbusmon
9, 8
10, 9
D, D
AI/O
10 -- 11
11 12 13
NC NC VREG (3.3V)
12
14
VCC (5.0V)
13
15
VPU (3.3V)
14
16
Config GND
Exposed Exposed Diepad Diepad
3
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USB1T1103
Functional Description
The USB1T1103 transceiver is designed to convert CMOS data into USB differential bus signal levels and to convert USB differential bus signal to CMOS data. To minimize EMI and noise the outputs are edge rate controlled with the rise and fall times controlled and defined for full speed data rates only (12Mbits/s). The rise, fall times are balanced between the differential terminals to minimize skew. The USB1T1103 differs from earlier USB Transceiver in that the Vp/Vm and Vpo/Vmo terminals are now I/O terminals rather than discrete input and output terminals. Table 1 describes the specific terminal functionality selection. Table 2 and Table 3 describe the specific Truth Tables for Driver and Receiver operating functions. The USB1T1103 also has the capability of various power supply configurations, including a disable mode for VCCIO disconnected, to support mixed voltage supply applications (see Table 4) and Section 2.1 for detailed descriptions.
Functional Tables
TABLE 1. Function Select SUSPND L L H H OE L H L H D, D Driving & Receiving Receiving (Note 1) Driving 3-STATE (Note 1) RCV Active Active Inactive (Note 2) Inactive (Note 2) Vp/Vpo Vpo Input Vp Output Vpo Input Vp Output Vm/Vmo Function
Vmo Input Normal Driving (Differential Receiver Active) Vm Output Receiving Vmo Input Driving during Suspend (Differential Receiver Inactive) Vm Output Low Power State
Note 1: Signal levels is function of connection and/or pull-up/pull-down resistors. Note 2: For SUSPND HIGH mode the differential receiver is inactive and the output RCV is forced LOW. The out-of-suspend signaling (K) is detected via the single-ended receivers of the Vp/Vpo and Vm/Vmo terminals.
TABLE 2. Driver Function (OE Vm/Vmo L L H H
Note 3: SE0 Single Ended Zero
L) using Differential Input Interface Data (D / D) SE0 (Note 3) Differential Logic 1 Differential Logic 0 Illegal State
Vp/Vpo L H L H
TABLE 3. Receiver Function (OE D, D Differential Logic 1 Differential Logic 0 SE0 RCV H L X
H) Vp/Vpo H L L Vm/Vmo L H L
X Don't Care RCV(0) denotes the signal level on output RCV just prior to the SE0 or SE1 event. This level is stable during the SE0 or SE1 event period.
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USB1T1103
Power Supply Configurations and Options
The three modes of power supply operation are: * Normal Mode: Regulated Output and Regulator Bypass 1. Regulated Output: VCCIO is connected and VCC(5.0) is connected to 5V (4.0V to 5.5V) and the internal voltage regulator then produces 3.3V for the USB connections. 2. Internal Regulator Bypass Mode: VCCIO is connected and both VCC(5.0) and VREG(3.3) are connected to a 3.3V source (3.0V to 3.6V). In both cases for normal mode the VCCIO is an independent voltage source (1.65V to 3.6V) that is a function of the external circuit configuration. * Sharing Mode: VCCIO is only supply connected. VCC and VREG are not connected. In this mode the D and D terminals are 3-STATE and the USB1T1103 allows external signals up to 3.6V to share the D and D bus lines. Internally the circuitry limits leakage from D and D terminals (maximum 10 PA) and VCCIO such that device is in low power (suspended) state. Terminals Vbusmon and RCV are forced LOW as an indication of this mode with Vbusmon being ignored during this state. * Disable Mode: VCCIO is not connected. VCC is connected, or VCC and VREG are connected. 0V to 3.3V in this mode D and D are 3-STATE and VPU is HIGH Impedance (switch is turned off). The USB1T1103 allows external signals up to 3.6V to share the D and D bus lines. Internally the circuitry limits leakage from D and D pins (maximum 10PA). A summary of the Supply Configurations is described in Table 4.
TABLE 4. Power Supply Configuration Options Power Supply Mode Configuration Terminals VCC (5V) Disable Connected to 5V source Sharing Not Connected or Normal (Regulated Output) Connected to 5V Source Normal (Regulator Bypass) Connected to VREG (3.3V) [Max Drop of 0.3V] (2.7V to 3.6V) Connected to 3.3V Source 1.65V to 3.6V Source 3.3V Available if Config HIGH Function of Mode Set Up Function of Mode Set Up Function of Mode Set Up Function of Mode Set Up Function of Mode Set Up
3.6V
VREG (3.3V) VCCIO VPU (3.3V) D, D Vp/Vpo, Vm/Vmo RCV Vbusmon OE, SUSPND, Config
3.3V, 300PA Regulated Output
Not Connected 1.65V to 3.6V Source 3-STATE (Off) 3-STATE L L L Hi-Z
3.3V, 300 PA Regulated Output 1.65V to 3.6V Source 3.3V Available if Config HIGH Function of Mode Set Up Function of Mode Set Up Function of Mode Set Up Function of Mode Set Up Function of Mode Set Up
d0.5V
3-STATE (off) 3-STATE (off) Invalid [I] Invalid [I] Invalid [I] Hi-Z
Invalid [I] I/O are to be 3-STATE, outputs to be LOW.
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USB1T1103
ESD Protection
ESD Performance of the USB1T1103 HBM D/D: 15.0kV HBM, all other terminals (Mil-Std 883E): 6.5kV ESD Protection: D/D Terminals Since the differential terminals of a USB transceiver may be subjected to extreme ESD voltages, additional immunity has been included in the D and D terminals without compromising performance. The USB1T1103 differential terminals have ESD protection to the following limits: * 15kV using the contact Human Body Model * 8kV using the Contact Discharge method as specified in IEC 61000-4-2
Human Body Model Figure 1 shows the schematic representation of the Human Body Model ESD event. Figure 2 is the ideal waveform representation of the Human Body Model. IEC 61000-4-2, IEC 60749-26 and IEC 60749-27 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment, and as such evaluates the equipment in its entirety for ESD immunity. Fairchild Semiconductor has evaluated this device using the IEC 6100-4-2 representative system model depicted in Figure 3. Under the additional standards set forth by the IEC, this device is also compliant with IEC 60749-26 (HBM) and IEC 60749-27 (MM). Additional ESD Test Conditions For additional information regarding our product test methodologies and performance levels, please contact Fairchild Semiconductor.
FIGURE 1. Human Body ESD Test Model
FIGURE 2. HBM Current Waveform
FIGURE 3. IEC 61000-4-2 ESD Test Model
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USB1T1103
Absolute Maximum Ratings(Note )
Supply Voltage (VCC)(5V) I/O Supply Voltage (VCCIO) Latch-up Current (ILU) VI
0.5V to 6.0V 0.5V to 4.6V
150 mA
Recommended Operating Conditions
DC Supply Voltage VCC (5V) I/O DC Voltage VCCIO DC Input Voltage Range (VI) DC Input Range for AI/O (VAI/O) Terminals D and D Operating Ambient Temperature (TAMB) 4.0V to 5.5V 1.65V to 3.6V 0V to VCCIO 5.5V 0V to VCC 0V to 3.6V
1.8V to 5.4V
DC Input Current (IIK) VI 0 DC Input Voltage (VI) (Note ) DC Output Diode Current (IOK) VO ! VCC or VO 0 DC Output Voltage (VO) (Note ) Output Source or Sink Current (IO) VO 0 to VCC Current for D, D Terminals Current for RCV, Vm/Vp DC VCC or GND Current (ICC, IGND) ESD Immunity Voltage (VESD); Contact HBM [3] Terminals D, D, ILI 1PA All Other Terminals [3] ILI 1 PA Storage Temperature (TSTO) Power Dissipation (PTOT) ICC (5V) ICCIO 48 mW 9 mW
18 mA 0.5V to VCCIO 0.5V r18 mA 0.5V to VCCIO 0.5V
40qC to 85qC
r12 mA r12 mA r100 mA
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristic tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Per ESD Methodology described in page 5.
r15kV r6.5kV 40qC to 125qC
DC Electrical Characteristics (Supply Terminals)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). VCC (5V) 4.0V to 5.5V or VREG (3.3V) 3.0V to 3.6V, VCCIO 1.65V to 3.6V Limits Symbol VREG (3.3V) Parameter Regulated Supply Output Conditions Min Internal Regulator Option; ILOAD d 300 PA ICC ICCIO ICC (IDLE) ICCIO (STATIC) ICC(DISABLE) ICC(SUSPND) Operating Supply Current (VCC5.0) I/O Operating Supply Current Supply Current during FS IDLE and SE0 (VCC5.0) I/O Static Supply Current Disable Supply Current Suspend Supply Current USB1T1103 ICCIO(SHARING) I/O Sharing Mode Supply Current ID (SHARING) ID/ ID(DISABLE) ID/ Sharing Mode Load Current on D/D Terminals Disable Mode Load Current on D/D Terminals Transmitting and Receiving at 12 Mbits/s; CLOAD 12 Mbits/s IDLE: VD t 2.7V, VD d 0.3V; SE0: VD d 0.3V, VD d 0.3V IDLE, SUSPND or SE0 VCCIO 0V HIGH OPEN 20.0 10.0 10.0 VCC Connected SUSPND OE Vm HIGH Vp 50 pF (D, D) Transmitting and Receiving at 3.0 (Note 7) (Note 8) 4.0 (Note 9) 1.0 (Note 9) 300 (Note 10) 20.0 25.0 25.0 (Note 10) 2.0 8.0
40qC to 85qC
Typ 3.3 Max 3.6
Units
V
mA mA
PA PA PA
PA PA PA PA
VCC (5V) Not Connected VCC (5V) Not Connected Config Config LOW; VDr VD r 3.6V VCCIO Not Connected or 0V 3.6V LOW or HIGH
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USB1T1103
DC Electrical Characteristics
Symbol VCCTH Parameter VCC Threshold Detection Voltage
(Continued)
Limits Conditions Min
40qC to 85qC
Typ Max 3.6 4.1 70.0
Units
1.65V d VCCIO d 3.6V Supply Lost Supply Present V
VCCHYS VCCIOTH
VCC Threshold Detection Hysteresis Voltage VCCIO Threshold Detection Voltage
VCCIO
1.8V
mV
2.7V d VREG d 3.6V Supply Lost Supply Present 1.4 450 mV 0.5 V
VCCIOHYS VREGTH
VCCIO Threshold Detection Hysteresis Voltage Regulated Supply Threshold Detection Voltage
VREG
3.3V
1.65V d VCCIO d VREG 2.7V d VREG d 3.6V Supply Lost Supply Present 2.4 (Note 12) 450 mV 0.8 V
VREGHYS
Regulated Supply Threshold Detection Hysteresis Voltage
VCCIO
1.8V
Note 7: ILOAD includes the pull-up resistor current via terminal VPU Note 8: The minimum voltage in Suspend mode is 2.7V. Note 9: Not tested in production, value based on characterization. Note 10: Excludes any current from load and VPU current to the 1.5k: resistor. Note 11: Includes current between Vpu and the 1.5k internal pull-up resistor. Note 12: When VCCIO 2.7V, minimum value for VREGTH 2.0V for supply present condition.
DC Electrical Characteristics
Symbol Input Levels VIL VIH VOL VOH LOW Level Input Voltage HIGH Level Input Voltage OUTPUT LEVELS: LOW Level Output Voltage HIGH Level Output Voltage Parameter
(Digital Terminals - excludes D, D Terminals)
1.65V to 3.6V Units Limits Test Conditions
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). VCCIO
40qC to 85qC
Min Max 0.3*VCCIO 0.6*VCCIO
V V
IOL IOL IOH IOH
2 mA 100 PA 2 mA 100 PA 1.65V to 3.6V VCCIO - 0.4 VCCIO- 0.15
0.4 0.15
V V
Leakage Current ILI Capacitance CIN, CI/O Input Capacitance Terminal to GND 10.0 pF
Note 13: If VCCIO t VREG then leakage current will be higher than specified.
Input Leakage Current
VCCIO
r1.0
(Note 13)
PA
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USB1T1103
DC Electrical Characteristics (Analog I/O Terminals - D, D Terminals)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). VCC 4.0V to 5.5V or VREG 3.0V to 3.6V Limits Symbol Parameter Test Condition Min Input Levels - Differential Receiver VDI VCM VIL VIH VHYS Output Levels VOL VOH LOW Level Output Voltage HIGH Level Output Voltage RL RL 1.5k: to 3.6V 15k: to GND 2.8 (Note 14) 0.3 3.6 V V Differential Input Sensitivity Differential Common Mode Voltage LOW Level Input Voltage HIGH Level Input Voltage Hysteresis Voltage 2.0 0.30 0.7 | VI(D) - VI(D) | 0.2 0.8 2.5 0.8 V V V V V
40qC to 85qC
Typ Max
Units
INPUT LEVELS - Single-ended Receiver
Leakage Current IOFF CI/O Resistance ZDRV ZIN RSW VTERM Driver Output Impedance Driver Input Impedance Switch Resistance Termination Voltage RPU Upstream Port 3.0 (Note 16) (Note 17) 34.0 10.0 10.0 3.6 V 41.0 (Note 15) 44.0 Input Leakage Current Off State CAPACITANCE I/O Capacitance Terminal to GND 20.0 pF
r1.0
PA
:
M:
:
Note 14: If VOH min.
VREG - 0.2V.
Note 15: Includes external resistors of 27: on both D and D terminals. Note 16: This voltage is available at terminal VPU and VREG. Note 17: Minimum voltage is 2.7V in the suspend mode.
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USB1T1103
AC Electrical Characteristics (A I/O Terminals Full Speed)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). VCC 4.0V to 5.5V or VREG 3.0V to 3.6V, VCCIO 1.65V to 3.6V, CL 50 pF; RL 1.5K on D to VPU Limits Symbol Driver Characteristics tR tF tRFM VCRS (Note 18) Driver Timing tPLH tPHL tPHZ tPLZ tPZH tPZL tPLH tPHL tPLH tPHL Propagation Delay (Vp/Vpo, Vm/Vmo to D/D) Driver Disable Delay (OE to D/D) Driver Enable Delay (OE to D/D) Propagation Delay (Diff) (D/D to Rev) Single Ended Receiver Propagation Delay (D/D to Vp/ Vpo, Vm/Vmo) Figures 5, 8 Figures 7, 8 Figures 7, 9 18.0 15.0 15.0 ns ns ns Output Rise Time Output Fall Time Rise/Fall Time Match Output Signal Crossover Voltage CL 50 125 pF 4.0 4.0 90.0 1.3 20.0 ns 20.0 111.1 2.0 % V 10% to 90% Figures 4, 8 tF/ tR Excludes First Transition from Idle State Excludes First Transition from Idle State see Waveform Parameter Test Conditions Min
40qC to 85qC
Typ Max
Unit
Receiver Timing Figures 6, 10 Figures 6, 10 15.0 18.0 ns ns
Note 18: Not production tested, limits guaranteed by design.
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USB1T1103
Typical Application Configurations
Upstream Connection in Bypass Mode with Differential Outputs
Downstream Connection in Normal Mode with Differential Outputs
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USB1T1103
AC Waveforms
FIGURE 4. Rise and Fall Times FIGURE 5. Vpo, Vmo to D/D
FIGURE 6. D/D to RCV, Vpo/Vp and Vmo/Vm
FIGURE 7. OE to D/D
Test Circuits and Waveforms
CL CL
50 pF Full Speed Propagation Delays
125 pF Edge Rates only
V V
0 for tPZH, tPHZ VREG for tPZL
FIGURE 8. Load for D/D
FIGURE 9. Load for Enable and Disable Times
FIGURE 10. Load for Vm/Vmo, Vp/Vpo and RCV
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USB1T1103
Tape and Reel Specification
Tape Format for MHBCC and MLP Package Tape Designator MHX/MPX Section Leader (Start End) Carrier Trailer (Hub End) TAPE DIMENSIONS inches (millimeters) Number Cavities 125 (typ) 2500/3000 75 (typ) Cavity Status Empty Filled Empty Cover Tape Status Sealed Sealed Sealed
REEL DIMENSIONS inches (millimeters)
Tape Size 12 mm
A 13.0 330
B 0.059 (1.50)
C 0.512 (13.00)
D 0.795 (20.20)
N 7.008 (178)
W1 0.488 (12.4)
W2 0.724 (18.4)
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USB1T1103
Physical Dimensions inches (millimeters) unless otherwise noted
Pb-Free 14-Terminal Molded Leadless Package (MLP), 2.5mm Square Package Number MLP14D
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USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 16-Terminal Molded Leadless Package (MHBCC), JEDEC MO-217, 3mm Square Package Number MLP16HB
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 15 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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