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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16704
240-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The PD16704 is a TFT-LCD gate driver equipped with 240-output lines. It can output a high-gate scanning voltage in response to CMOS level input because it is provided with a level-shift circuit inside the IC circuit.
FEATURES
* CMOS level input (3.0 to 3.6 V) * 240 outputs * High-output voltage (VDD2 to VEE2: 40 V MAX.) * Double scan inversion function * COG inversion
ORDERING INFORMATION
Part Number Package Chip
PD16704P
Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representavies.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S15809EJ1V0DS00 (1st edition) Date Published December 2002 NS CP (K) Printed in Japan
2001
PD16704
1. BLOCK DIAGRAM
R,/L LS1 Note
DS
LS1 Note
DSOE
LS1 Note
CLK
LS1 Note
STV
LS1 Note
SR1
SR2
SR3
240 - bit shift resister
SR238 SR239 SR240
OE
LS1 Note
LS2 Note LS2 Note LS2 Note VEE2
LS2 Note LS2 Note LS2 Note
O1
O2
O3
O238
O239
O240
Note LS1: shifts CMOS level and internal level, LS2: shifts interval level and output level (VDD2 to VEE2). Remark /xxx indicates active low signal.
2
Data Sheet S15809EJ1V0DS
PD16704
2. PIN CONFIGURATION (IC Pad Surface)
Chip Size: 1.06 x 15.39 mm
Dummy
2
VDD2 VDD2 VDD2 Alignment Mark Dummy
Dummy
TEST1 O1 TEST1 O2 VEE2 VEE2 VEE2 VEE2 VEE1 VEE1 VEE1 VEE1 Dummy VDD1 VDD1 VDD1 VDD1 DS DS R/L R/L STV STV CLK CLK Dummy
0
Dummy OE OE DSOE
Y(+)
X(+)
DSOE VSS VSS VSS VSS VCC VCC VCCC VCCC Dummy VEE1 VEE1 VEE1 VEE1 VEE2 VEE2 VEE2 O239 VEE2 O240 TEST2 Dummy TEST2 Alignment Mark Dummy Dummy VDD2 VDD2 VDD2
* Bump size : 40 x 80 m
2 2
: 110 x 60 m * Alignment : 50 x 50 m
2
Alignment Mark Coordinate (Unit: mm): (7570, 405) , (-7570, 405)
Remark This figure does not specify the TCP package.
Data Sheet S15809EJ1V0DS
3
PD16704
Figure 2-1. Pad Coordinate (1/3) -
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PAD Name TEST1 TEST1 VEE2 VEE2 VEE2 VEE2 VEE1 VEE1 VEE1 VEE1 DUMMY VDD1 VDD1 VDD1 VDD1 DS DS RL RL STV STV CLK CLK DUMMY DUMMY OE OE DSOE DSOE VSS VSS VSS VSS VCC VCC VCCC VCCC DUMMY VEE1 VEE1 VEE1 VEE1 VEE2 VEE2 VEE2 VEE2 TEST2 TEST2 DUMMY DUMMY
X[m] -7061.8 -6931.8 -6801.8 -6671.8 -6541.8 -6411.8 -6193.8 -6063.8 -5933.8 -5803.8 -5673.8 -5490.8 -5360.8 -4999.0 -4450.2 -4120.4 -3809.4 -3362.4 -2924.2 -2280.2 -1969.2 -1522.2 -1084.0 -440.0 182.2 826.2 1264.4 1711.4 2022.4 2194.2 2564.8 2926.6 3056.6 3433.4 4073.4 4450.2 5090.2 5691.8 5821.8 5951.8 6081.8 6211.8 6429.8 6559.8 6689.8 6819.8 6949.8 7079.8 7556.0 7556.0
Y[m] -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -375.0 -220.0 -80.0
Bump size (X:Y)[m] 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 110:60 80:40 80:40
No 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
PAD Name VDD2 VDD2 VDD2 DUMMY O240 O239 O238 O237 O236 O235 O234 O233 O232 O231 O230 O229 O228 O227 O226 O225 O224 O223 O222 O221 O220 O219 O218 O217 O216 O215 O214 O213 O212 O211 O210 O209 O208 O207 O206 O205 O204 O203 O202 O201 O200 O199 O198 O197 O196 O195
X[m] 7556.0 7556.0 7556.0 7200.0 7140.0 7080.0 7020.0 6960.0 6900.0 6840.0 6780.0 6720.0 6660.0 6600.0 6540.0 6480.0 6420.0 6360.0 6300.0 6240.0 6180.0 6120.0 6060.0 6000.0 5940.0 5880.0 5820.0 5760.0 5700.0 5640.0 5580.0 5520.0 5460.0 5400.0 5340.0 5280.0 5220.0 5160.0 5100.0 5040.0 4980.0 4920.0 4860.0 4800.0 4740.0 4680.0 4620.0 4560.0 4500.0 4440.0
Y[m] 136.0 216.0 296.0 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5
Bump size (X:Y)[m] 110:60 110:60 110:60 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80
4
Data Sheet S15809EJ1V0DS
PD16704
Figure 2-1. Pad Coordinate (2/3) -
No 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
PAD Name O194 O193 O192 O191 O190 O189 O188 O187 O186 O185 O184 O183 O182 O181 O180 O179 O178 O177 O176 O175 O174 O173 O172 O171 O170 O169 O168 O167 O166 O165 O164 O163 O162 O161 O160 O159 O158 O157 O156 O155 O154 O153 O152 O151 O150 O149 O148 O147 O146 O145
X[um] 4380.0 4320.0 4260.0 4200.0 4140.0 4080.0 4020.0 3960.0 3900.0 3840.0 3780.0 3720.0 3660.0 3600.0 3540.0 3480.0 3420.0 3360.0 3300.0 3240.0 3180.0 3120.0 3060.0 3000.0 2940.0 2880.0 2820.0 2760.0 2700.0 2640.0 2580.0 2520.0 2460.0 2400.0 2340.0 2280.0 2220.0 2160.0 2100.0 2040.0 1980.0 1920.0 1860.0 1800.0 1740.0 1680.0 1620.0 1560.0 1500.0 1440.0
Y[um] 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5
Bump size (X:Y)[um] 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80
No 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
PAD Name O144 O143 O142 O141 O140 O139 O138 O137 O136 O135 O134 O133 O132 O131 O130 O129 O128 O127 O126 O125 O124 O123 O122 O121 O120 O119 O118 O117 O116 O115 O114 O113 O112 O111 O110 O109 O108 O107 O106 O105 O104 O103 O102 O101 O100 O99 O98 O97 O96 O95
X[m] 1380.0 1320.0 1260.0 1200.0 1140.0 1080.0 1020.0 960.0 900.0 840.0 780.0 720.0 660.0 600.0 540.0 480.0 420.0 360.0 300.0 240.0 180.0 120.0 60.0 0.0 -60.0 -120.0 -180.0 -240.0 -300.0 -360.0 -420.0 -480.0 -540.0 -600.0 -660.0 -720.0 -780.0 -840.0 -900.0 -960.0 -1020.0 -1080.0 -1140.0 -1200.0 -1260.0 -1320.0 -1380.0 -1440.0 -1500.0 -1560.0
Y[m] 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5
Bump size (X:Y)[m] 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80
Data Sheet S15809EJ1V0DS
5
PD16704
Figure 2-1. Pad Coordinate (3/3) -
No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
PAD Name O94 O93 O92 O91 O90 O89 O88 O87 O86 O85 O84 O83 O82 O81 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 O50 O49 O48 O47 O46 O45
X[m] -1620.0 -1680.0 -1740.0 -1800.0 -1860.0 -1920.0 -1980.0 -2040.0 -2100.0 -2160.0 -2220.0 -2280.0 -2340.0 -2400.0 -2460.0 -2520.0 -2580.0 -2640.0 -2700.0 -2760.0 -2820.0 -2880.0 -2940.0 -3000.0 -3060.0 -3120.0 -3180.0 -3240.0 -3300.0 -3360.0 -3420.0 -3480.0 -3540.0 -3600.0 -3660.0 -3720.0 -3780.0 -3840.0 -3900.0 -3960.0 -4020.0 -4080.0 -4140.0 -4200.0 -4260.0 -4320.0 -4380.0 -4440.0 -4500.0 -4560.0
Y[m] 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5
Bump size (X:Y)[m] 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80
No 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
PAD Name O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 DUMMY VDD2 VDD2 VDD2 DUMMY DUMMY
X[m] -4620.0 -4680.0 -4740.0 -4800.0 -4860.0 -4920.0 -4980.0 -5040.0 -5100.0 -5160.0 -5220.0 -5280.0 -5340.0 -5400.0 -5460.0 -5520.0 -5580.0 -5640.0 -5700.0 -5760.0 -5820.0 -5880.0 -5940.0 -6000.0 -6060.0 -6120.0 -6180.0 -6240.0 -6300.0 -6360.0 -6420.0 -6480.0 -6540.0 -6600.0 -6660.0 -6720.0 -6780.0 -6840.0 -6900.0 -6960.0 -7020.0 -7080.0 -7140.0 -7200.0 -7260.0 -7556.0 -7556.0 -7556.0 -7556.0 -7556.0
Y[m] 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 310.5 296.0 216.0 136.0 -80.0 -220.0
Bump size (X:Y)[m] 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 40:80 110:60 110:60 110:60 80:40 80:40
6
Data Sheet S15809EJ1V0DS
PD16704
3. PIN FUNCTIONS
(1/2)
Pin Symbol O1 to O240 Pin Name Driver output Pad No 294 - 55 I/O Description
Output These pins output scan signals that drive the vertical direction (gate lines) of a TFT-LCD. The output signals change in synchronization with the rising edge of shift clock CLK. The driver output amplitude is VDD2 to VEE2.
R,/L
Shift direction select input
18, 19
Input
R,/L = H (right shift) : STV O1 O240 R,/L = L (left shift) : STV O240 O1
STV
Start pulse input/output
20, 21
I/O
This is the input of the internal shift register. The start pulse is written at the rising edge of shift clock CLK. The pulse range is less than one cycle of CLK. The input level is a VDD1 to VSS (logic level).
CLK
Shift clock input
22, 23
Input
This pin inputs a shift clock to the internal shift register. The shift operation is performed in synchronization with the rising edge of this input.
OE
Output enable input
26, 27
Input
When this pin goes low level, the driver output is fixed to VEE2 level. The shift register is not cleared. Refer to 4. TIMING CHART for details.
DS
Double scan control input
16, 17
Input
This pin outputs scan signals simultaneously from two outputs in synchronization with the rise of CLK when DS = H is written. Refer to 4. TIMING CHART for details.
DSOE
Double scan pulse width control input
28, 29
Input
This pin controls the fall timing of one of the scan signals (the output side in normal scan mode) when the DS signal is used to output scan signals simultaneously from two outputs. This signal is input asynchronously to the clock. Refer to 4. TIMING CHART for details.
VCC, VCCC TEST1, TEST2 Dummy
IC internal reference voltage TEST pins
34, 35, 36, 37 1, 2, 47, 48
-
Short the VCC pin to the VCCC pin so that these pins are in a floating state.
-
Short TEST1 and TEST2 separately inside the IC. These pins are not connected to any other pins inside the IC.
Dummy pin
11, 24, 25, 38, 49, 50, 54, 295, 299, 300
-
No dummy pins are connected to any other pins inside the IC.
VDD1
Logic power supply
12 - 15
-
3.3 0.3 V
VDD2
Driver positive power supply
51 - 53, 296 - 298
-
15 to 25 V The driver output: high level
Data Sheet S15809EJ1V0DS
7
PD16704
(2/2)
Pin Symbol VSS VEE1 Pin Name Logic ground Negative power supply for internal operation VEE2 Driver negative power supply 3 - 6, 43 - 46 - The driver output: low level (VEE2 to VEE1 < 6.0 V) Pad No 30 - 33 7 - 10, 39 - 42 I/O - - Description Connect this pin to the ground of the system. -15 to -5 V
Cautions 1. To prevent latch-up, turn on power to VDD1, VEE1, VEE2, VDD2, and logic input in this order. Turn off power in the reverse order. transition period. 2. Insert a capacitor of about 0.1 F between each power line, as shown below, to secure noise margin such as VIH and VIL.
VDD2 VDD1 0.1 F VSS 0.1 F VEE1 VEE2 0.1 F
These power up/down sequence must be observed also during
8
Data Sheet S15809EJ1V0DS
PD16704
4. TIMING CHART (R,/L = H)
As shown in the figure below, when DS = H, scan signals are output successively from two outputs in synchronization with the rise of CLK (double scan operation). It is also possible to accelerate the fall timing of one of the scan signals (the output side in normal scan mode) in a double scan operation by using the DSOE signal. DSOE is input asynchronously to the clock, and the output is fixed to VEE2 in the period between the rise of DSOE and the rise of CLK. The DSOE signal is only enabled during a double scan operation.
CLK
OE
DS
DSOE
STV
O1
O2
O3
O4
O5
O6
O7
Data Sheet S15809EJ1V0DS
9
PD16704
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Logic Supply Voltage Driver Positive Supply Voltage Power Supply Voltage Internal Operation Negative Supply Voltage Driver Negative Supply Voltage Input Voltage Operating Ambient Temperature Storage Temperature VDD1 VDD2 VDD2 to VEE1, VEE2 VEE1 VEE2 VI TA Tstg Symbol Rating -0.5 to +7.0 -0.5 to +28 -0.5 to +42 -16 to + 0.5 VEE1 - 0.3 to VEE1 + 7.0 -0.5 to VDD1 + 0.5 -30 to +85 -55 to +125 Unit V V V V V V C C
Caution
Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = -30 to +85C, VSS = 0 V)
Parameter Logic Supply Voltage Driver Positive Supply Voltage Internal Operation Negative Supply Voltage Power Supply Voltage VDD1 VDD2 VEE1 VDD2 to VEE1 VEE2 to VEE1 Clock Frequency fCLK Symbol MIN. 3.0 15 -15 20 0 TYP. 3.3 23 -10 33 MAX. 3.6 25 -5.0 40 6.0 500 Unit V V V V V kHz
Electrical Characteristics (TA = -30 to +85C, VDD1 = 3.3 V 0.3 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V)
Parameter High-level Input Voltage Low-level Input Voltage LCD Driver Output ON Resistance Symbol VIH VIL RON VOUT = VEE2 + 1.0 V, or VDD2 - 1.0 V Input Leak Current Dynamic Current Dissipation IIL IDD1 VI = 0 V or 3.6 V, VDD1, fCLK = 50 kHz, fSTV = 60 Hz, No load IDD2 VDD2, fCLK = 50 kHz, fSTV = 60 Hz, No load IEE VEE1, fCLK = 50 kHz, fSTV = 60 Hz, No load -1000 100 1.0 1000 Condition CLK, STV, R,/L, OE MIN. 0.8 VDD1 VSS TYP. MAX. VDD1 0.2 VDD1 2.0 Unit V V k
A A A A
10
Data Sheet S15809EJ1V0DS
PD16704
Switching Characteristics (TA = -30 to +85C, VDD1 = 3.3 V 0.3 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V)
Parameter Driver Output Delay Time Symbol tPHL2 tPLH2 tPHL3 tPLH3 DSOE Output Rise Time Output Fall Time Input Capacitance tPHL4 tTLH tTHL CI TA = 25C CL = 300 pF CL = 300 pF, OE On Condition CL = 300 pF, CLK On MIN. TYP. MAX. 800 800 800 800 800 1500 1500 15 Unit ns ns ns ns ns ns ns pF
Timing Requirements (TA = -30 to +85C, VDD1 = 3.3 V 0.3 V, VDD2 = 23 V, VEE1 = VEE2 = -10 V, VSS = 0 V, tr = tf =20 ns (10 to 90%) )
Parameter Clock Pulse High Width Clock Pulse Low Width Enable Pulse Width Start Pulse Setup Time Start Pulse Hold Time Double Scan Setup Time Double Scan Hold Time Symbol PWCLK(H) PWCLK(L) PWOE tSETUP1 tHOLD1 tSETUP2 tHOLD2 OE STV CLK CLK STV DS CLK CLK DS Condition MIN. 500 500 1000 200 200 200 200 TYP. MAX. Unit ns ns ns ns ns ns ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1.
Data Sheet S15809EJ1V0DS
11
12
CLK STV 50% DS DSOE O1
Switching Characteristics Waveform (R,/L= H)
PWCLK(L) PWCLK 50% 1 tSETUP1 tHOLD1 2 3
PWCLK(H) 50% 4 5 6 7 90%
tr
tf
10%
tSETUP2 tHOLD2 50%
90%
tPLH2
tPHL2 90%
Data Sheet S15809EJ1V0DS
10% tPLH2 tPHL2 90% 10% tTLH tTLH
O2
O3
90% 10% tPLH2 tPHL4 90% 10% tPLH2
On
On + 1
10%
OE 50% O1-O240
PWOE
PD16704
tPLH3 90%
tPHL3
10%
PD16704
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15809EJ1V0DS
13
PD16704
Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E)
* The information in this document is current as of December, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics's willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11

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