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T6C25
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6C25
COLUMN AND ROW DRIVER FOR A DOT MATRIX LCD
The T6C25 is a 160-channel-output column and row driver for an STN dot matrix LCD. The T6C25 features a 42-V LCD drive voltage and an 8-MHz maximum operating frequency. The T6C25 is able to drive LCD panels with a duty ratio of up to 1 / 480.
FEATURES
l Display duty application l LCD drive signal l Data transfer l Operating frequency l LCD drive voltage l Power supply voltage l Operating temperature l Display-off function l Low power consumption l EI / LP input : to 1 / 480 : 160 : Column : 4 / 8-bit bidirectional Row : Single / Dual bidirectional : 8 MHz : 14 to 42 V : 2.7 to 5.5 V : -20 to 75C : When / DSPOF is L, all LCD drive outputs (O1 to O160) remain at the V5 level. : Cascade connection and auto enable transfer functions are available. : EI / LP Input enables LSI operation. Connect EIO 1 / 2 from the 1st LSI to L.
l LCD drive output resistance : 1.3 k (max) (20 V, 1 / 13 bias)
000707EBE1
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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T6C25
BLOCK DIAGRAM
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T6C25
PIN ASSIGNMENT
* : The above diagram shows the pin configuration of the LSI Chip, not that of the tape carrier package.
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T6C25
PIN FUNCTIONS
PIN NAME O1 to O160 EIO1, EIO4 I/O Output I/O Output for LCD drive signal Input / output for enable signal DIR selects In or Out. Connect EIO (IN) of 1st LSI to L. For a cascade connection, connect EIO (OUT) to EIO (IN) of next LSI. (Column mode) Input for data signal (Row mode) Fix to H or L (Direction) Input for data flow direction select, (Display Off) / DSPOF = L : Display-off mode, (O1 to O160) remain at the V5 level. / DSPOF = H : Display-on mode, (O1 to O160) are operational. (Column mode) Input for data bit select (Row mode) Fix to H or L (Column mode) Fix to H or L (Row mode) Input for dual / single select (Column mode) Display data is latched on falling edges of LP. LP When EIO (IN) = L, setting SCP *LP = H enables the 1st LSI. (Row mode) Input for shift clock pulse FR Input (Frame) Input for frame signal (Column mode) Input for shift clock pulse (Row mode) Fix to H or L (TEST) Fix to L Input for mode select : H = Column mode, L = Row mode Power supply for internal logic (+5.0 V) Power supply for internal logic (0 V) Power supply for LCD drive circuit Power supply for LCD drive circuit Power supply for LCD drive circuit Power supply for LCD drive circuit Power supply for LCD drive circuit VDD to VSS FUNCTIONS LEVEL V0 to V5
DI1 to DI8
Input
DIR
Input
/ DSPOF
Input
DF
Input
DUAL
Input
SCP
Input
TEST S/C VDD VSS V5L*R V3 / 4L*R V2 / 1L*R V0L*R VCCL*R
Input Input

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T6C25
RELATION BETWEEN FR, DATA INPUT AND OUTPUT LEVEL
FR L L H H * DATA INPUT (DI1 to DI8) L H L H * / DSPOF H H H H L OUTPUT LEVEL (CULUMN MODE) V3 V5 V2 V0 V5 OUTPUT LEVEL (ROW MODE) V4 V0 V1 V5 V5
*:
Don't Care
DATA INPUT FORMAT Column mode
DIR H L L 4-BIT IN OUT DF BIT MODE ENABLE PIN EIO1 EIO2 OUT IN (*1) L F L F L F L F DI1 O160 O4 O1 O157 O160 O8 O1 O153 INPUT DATA LINE AND OUTPUT BUFFERS DI2 DI3 DI4 DI5 DI6 DI7 O159 O3 O2 O158 O159 O7 O2 O154 O158 O2 O3 O159 O158 O6 O3 O155 O157 O1 O4 O160 O157 O5 O4 O156 DI8

O156 O4 O5 O157

O155 O3 O6 O158

O154 O2 O7 O159

O153 O1 O8 O160
H H L 8-BIT
OUT
IN
IN
OUT
*1 :
L: Last Data F: First Data
Row Mode
DUAL L L H DIR L H L DATA FLOW O160 O1 O1 O160 O160 O81 O80 O1 O1 O80 O81 O160 EIO1 OUT IN OUT DATA INPUT TERMINALS EIO2 EIO3 DIN IN OUT IN
IN
OUT
H
H
IN
OUT
IN
OUT
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TIMING DIAGRAM (Column mode)
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T6C25
T6C25
TIMING DIAGRAM (Row mode)
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T6C25
ABSOLUTE MAXIMUM RATINGS
(Ensure that the following conditions are maintained, VCCV0V2V3V5VSS)
ITEM Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Supply Voltage (4) Input Voltage Operating Temperature Storage Temperature SYMBOL VDD VCC V0, V2 V3, V5 VIN Topr Tstg PIN NAME VDD VCCL / R V0L / R, V2L / R V3L / R, V5L / R (*2) RATING -0.3 to 7.0 - 0.3 to 45.0 -0.3 to VCC + 0.3 -0.3 to 7.0 -0.3 to VDD + 0.3 - 20 to 75 - 40 to 125 UNIT V V V V V C C
*2 : SCP, FR, LP, DIR, DF, DUAL, S / C, EIO1 to 4, DI1 to 8, / DSPOF, TEST
ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS
TEST CIRCUIT
(Unless otherwise noted, VSS = 0V, VDD = 2.7 to 5.5V, Ta = -20 to 75C)
ITEM Supply Voltage 1 Supply Voltage 2 Input Voltage H Level L Level H Level L Level H Level Output Resistance M Level L Level SYMBOL VDD VCC VIH VIL VOH VOL ROH ROM ROL TEST CONDITION MIN 2.7 14 0.8 VDD (*2) IOH = -0.4 mA IOL = 0.4 mA VOUT = V0 - 0.5 V VOUT = V2 0.5 V VOUT = V3 0.5 V VOUT = V5 + 0.5 V (*3) (*3) (*3) (*3) 0 VDD -0.5 0 TYP. 5.0 0.6 0.6 0.6 0.6 MAX 5.5 42 VDD 0.2 VDD VDD 1.3 1.3 1.3 1.3 1.3 k O1 to O160 V UNIT VDD VCCL / R SCP, FR, LP, DIR, DF, DUAL S / C, EIO1 to 4, DI1 to 8, / DSPOF, TEST, EIO1, to 4 PIN NAME
Output Voltage
Current Consumption (*4)
IDD
VDD = 5.5 V VCC = 42 V fFR = 40 Hz fscp = 8.0 MHz Input Data : every bit inverted VIH = 5.5 V, VIL = 0 V
3.0
mA
VDD
*3 : VCC = 20 V, 1 / 13 bias *4 : Current consumption while the internal data receiver is operating.
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T6C25
AC ELECTRICAL CHARACTERISTICS (Column Mode)
TEST CONDITIONS (1) (VSS = 0 V, VDD = 4.5 to 5.5 V, VCC = 14 to 42 V, Ta = -20 to 75C)
ITEM Clock Cycle SCP Pulse Width Data Set-up Time Data Hold Time SCP Rise / Fall Time LP Rise Time LP Fall Time LP Pulse Width SCP-to-LP Delay Time LP-to-SCP Delay Time EIO-In Fall Time EIO-In Pulse Width SCP-to-EIO Delay Time EIO-Out Delay Time SYMBOL tC tCWH, tCWL tDSU tDHD tr, tf tLRP tLFP tLW tSL tLS tEIFP tEIW tSE tEOD TEST CONDITION (*6) MIN 125 50 50 50 50 50 45 40 40 40 40 20 MAX (*5) 80 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
*5 : tr, tf (tC - tCWH - tCWL) / 2 and tr, tf50 ns *6 : CL = 30 pF
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T6C25
TEST CONDITIONS (2) (VSS = 0 V, VDD = 2.7 to 4.5 V, VCC = 14 to 42 V, Ta = -20 to 75C)
ITEM Clock Cycle SCP Pulse Width Data Set-up Time Data Hold Time SCP Rise / Fall Time LP Rise Time LP Fall Time LP Pulse Width SCP-to-LP Delay Time LP-to-SCP Delay Time EIO-In Fall Time EIO-In Pulse Width SCP-to-EIO Delay Time EIO-Out Delay Time SYMBOL tC tCWH, tCWL tDSU tDHD tr, tf tLRP tLFP tLW tSL tLS tEIFP tEIW tSE tEOD TEST CONDITION (*6) MIN 500 240 240 240 240 240 240 50 100 240 240 50 MAX (*5) 260 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
*5 : tr, tf (tC - tCWH - tCWL) / 2 and tr, tf50 ns *6 : CL = 30 pF
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T6C25
AC ELECTRICAL CHARACTERISTICS (Row mode)
TEST CONDITIONS (1) (VSS = 0 V, VDD = 4.5 to 5.5 V, VCC = 14 to 42 V, Ta = -20 to 75C)
ITEM LP Pulse Width H LP Pulse Width L SCP Rise / Fall Time Data Set-up Time Data Hold Time EIO-Out Delay Time A (*7) EIO-Out Delay Time B (*7) SYMBOL tCWH tCWL tr , tf tDSU tDHD tpdA tpdB TEST CONDITION LP LP LP, FR, EIO1 to 4 EIO1 to 4 EIO1 to 4 EIO1 to 4 EIO1 to 4 MIN 30 195 80 0 5 MAX 20 150 UNIT ns ns ns ns ns ns ns
TEST CONDITIONS (2) (VSS = 0 V, VDD = 2.7 to 5.5 V, VCC = 14 to 42 V, Ta = -20 to 75C)
ITEM LP Pulse Width H LP Pulse Width L SCP Rise / Fall Time Data Set-up Time Data Hold Time EIO-Out Delay Time A (*7) EIO-Out Delay Time B (*7) SYMBOL tCWH tCWL tr , tf tDSU tDHD tpdA tpdB TEST CONDITION LP LP LP, FR, EIO1 to 4 EIO1 to 4 EIO1 to 4 EIO1 to 4 EIO1 to 4 MIN 100 400 130 0 5 MAX 20 400 UNIT ns ns ns ns ns ns ns
*7 :
CL = 30 pF
Note : Insert the bypass capacitor (0.1F) between VDD and VSS to decrease power supply noise. Place the bypass capacitor as close to the LSI as possible.
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