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ST72589BW, ST72389BW
8-BIT MCU WITH NESTED INTERRUPTS, DOT MATRIX LCD, ADC, TIMERS, PWM-BRM, SPI, SCI, IC, CAN INTERFACES
DATASHEET
s
s s s s s s
s
s s s
s s s s s s
16K ROM or 24 Kbytes EPROM/OTP/ FASTROM Master Reset and Power-on Reset Low consumption resonator main oscillator 4 Power saving modes Nested interrupt controller NMI dedicated non maskable interrupt pin 31 multifunctional bidirectional I/O lines with: - external interrupt capability (5 vectors) - 21 alternate function lines LCD driver with 60 segment outputs and 8 backplane outputs able to drive up to 60x8 (480) or 60x4 (240) LCD displays Real time base, Beep and Clock-out capabilities Software watchdog reset Two 16-bit timers with: - 2 input captures - 2 output compares - external clock input on one timer - PWM and Pulse generator modes 10-bit PWM (DAC) with 4 dedicated output pins SPI synchronous serial interface SCI asynchronous serial interface I2C multi master / slave interface CAN interface 8-bit ADC with 5 dedicated input pins
PQFP128 14 x 20
s s s s s
8-bit Data Manipulation 63 Basic Instructions 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Full hardware/software development package
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Device Summary
Features Program memory - bytes RAM (stack) - bytes Std. Peripherals Operating Supply CPU Frequency Temperature Range Packages Development device ST72589BW5 24K OTP/FASTROM 1024 (256) LCD 60x8, Watchdog, 16-bit Timers, PWM-BRM, SPI, SCI, I2C, CAN, ADC ST72389BW4 16K ROM 512 (256) LCD 60x8, Watchdog, 16-bit Timers, SPI, SCI, ADC
4.5V to 5.5V 4 to 8 MHz (with 8 to 16 MHz oscillator) -40C to +85C PQFP128 ST72E589BW5
Rev. 2.7
June 2003 1/158
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Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 MEMORIES AND PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 RESET MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 3.2 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1 I/O PORT INTERRUPT SENSITIVITY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 MISCELLANEOUS REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 LCD DRIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.4 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.6 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.7 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.8 CONTROLLER AREA NETWORK (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.9 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 158 9.3 TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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9.5 I/O PORTS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.7 MEMORY AND PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 154 11.1 ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . 154 11.2 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
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ST72589BW, ST72389BW
1 GENERAL DESCRIPTION
1.1 INTRODUCTION The ST72589W and ST72389W Microcontroller Units are members of the ST7 family of Microcontrollers dedicated to high-end applications with LCD driver capability. These devices are based on an industry-standard 8-bit core and feature an enhanced instruction set. Under software control, these microcontrollers may be placed in either WAIT, SLOW, ACTIVEFigure 1. Device Block Diagram HALT or HALT modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, these microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
VDD VSS RESET NMI
POWER SUPPLY
EPROM 24K
CONTROL 8-BIT CORE ALU
RAM 512 or 1K
PORT B OSC2 OSC1 MAIN OSC
ADDRESS AND DATA BUS
TIMER B CAN* PORT D SPI I2C*
PB0 -> PB6 (7-bit)
PORT C SCI PC0 -> PC7 (8-bit) BEEP TIMER A PA0 -> PA7 (8-bit) PORT A WATCHDOG PWM0 -> PWM3 (4-bit) AIN0 -> AIN4 (5-channel) VDDA VSSA PWM-BRM* 8-bit ADC
PD0 -> PD7 (8-bit)
LCD DRIVER + LCD RAM (60x8)
S1 -> S60 (60-segment) COM1 -> COM8 (60-common) VLCD, VLCD3/4, VLCD1/2, VLCD1/4 GLCD
*available on ST72589 version only
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1.2 PIN DESCRIPTION Figure 2. 128-Pin PQFP Package Pinout
S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 GLCD VLCD1/4 VLCD1/2 VLCD3/4 VLCD VDD_A AIN0 AIN1 AIN2 AIN3 AIN4 VSS_A PWM0* PWM1* PWM2* PWM3* RESET VPP VDD_1 OSC1 OSC2 VSS_1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VDD_3 VSS VSS VSS_3 PD7 PD6 PD5 PD4 PD3 PD2 / SDAI* / SCLI* / SS / SCK
EI5
EI5 EI1 39 40 41 EI2 EI3 EI4 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
PD1 / MOSI PD0 / MISO
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 NMI OCMP1_B / PB0 OCMP2_B / PB1 ICAP1_B / PB2 ICAP2_B / PB3 PB4 CAN_RX* / PB5 CAN_RX */ PB6 VDD_2 VSS_2 TDO / PC0 RDI / PC1 ICAP1_A / PC2 ICAP2_A / PC3 OCMP1_A / PC4 OCMP2_A / PC5 CLK_A / PC6 MCO / BEEP / PC7
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = input, O = output, S = supply, CK = Clock Output level: LCD = V LCD, VLCD3/4, VLCD1/2, VLCD1/4, or GLCD level. Input level: C = CMOS 0.3VDD/0.7VDD Port configuration capabilities: - Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog - Output: OD = open drain, T = true open drain, PP = push-pull Note: Reset configuration of each pin is bold. Table 1. Device Pin Description
Pin n PQFP128 Type Pin Name Level Output Input Port Input float wpu ana int Main func tion Output (after reset) OD PP
Alternate function
1 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
S45 ... S60 GLCD VLCD1/4 VLCD1/2 VLCD3/4 VLCD VDDA AIN0 AIN1 AIN2 AIN3 AIN4 VSSA PWM0* or NC PWM1*or NC PWM2* or NC PWM3* or NC RESET VPP VDD_1 OSC1 OSC2 VSS_1 PA0 PA1 PA2 PA3
O S S S S S S I I I I I S O O O O I/O I S CK CK S I/O I/O I/O I/O C C C C
LCD
LCD Segment Analog Outputs LCD Ground Reference Voltage
LCD Supply Reference Voltage
Analog Power Supply Voltage X X X X X ADC Analog Input 0 ADC Analog Input 1 ADC Analog Input 2 ADC Analog Input 3 ADC Analog Input 4 Analog Ground Voltage Pulse Width Modulator output 0* Pulse Width Modulator output 1* Pulse Width Modulator output 2* Pulse Width Modulator output 3* Top priority non maskable interrupt. Must be tied low in user mode. In the programming mode when available, this pin acts as the programming voltage input VPP. Digital Main Supply Voltage These pins connect a parallel-resonant crystal or an external source to the on-chip main oscillator. Digital Ground Voltage X X X X EI1 X X X X X X X X Port A0 Port A1 Port A2 Port A3
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Pin n PQFP128 Type Pin Name
Level Output Input
Port Input float wpu ana int
OD
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 to 84 85 to 128
PA4 PA5 PA6 PA7 NMI PB0/OCMP1_B PB1/OCMP2_B PB2/ICAP1_B PB3/ICAP2_B PB4 PB5/CANTX* PB6/CANRX* VDD_2 VSS_2 PC0/TDO PC1/RDI PC2/ICAP1_A PC3/ICAP2_A PC4/OCMP1_A PC5/OCMP2_A PC6/EXTCLK_A PC7/MCO/BEEP PD0/MISO PD1/MOSI PD2/SCK PD3/SS PD4/SCLI* PD5/SDAI* PD6 PD7 VSS_3 VSS VSS VDD_3 COM1 to COM8 S1 to S44
I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S S S O O
C C C C C C C C C C C
X X X X X X X X X X X EI3 EI2
X X X X X X X X X X X
X X X X X X X X X X X
PP
Main func tion Output (after reset) Port A4 Port A5 Port A6 Port A7
Alternate function
No maskable interrupt input pin (floating) Port B0 Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 CAN Transmit Data Output* CAN Receive Data Input* Timer B Output Compare 1 Timer B Output Compare 2 Timer B Input Capture 1 Timer B Input Capture 2
Digital Main Supply Voltage Digital Ground Voltage C C C C C C C C C C C C C C C C X X X X X X X X X X X X X X X X EI5 EI5 EI4 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Port C0 Port C1 Port B2 Port B3 Port B0 Port B1 Port C6 Port C7 Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7 Digital Ground Voltage Ground Voltage Ground Voltage Digital Main Supply Voltage C LCD LCD LCD Common (backplane) analog output LCD Segment Analog Outputs SCI Transmit Data Out SCI Receive Data In Timer A Input Capture 1 Timer A Input Capture 2 Timer A Output Compare 1 Timer A Output Compare 2 Timer A External Clock Main clock-out Beep signal SPI Master In / Slave Out Data SPI Master Out / Slave In Data SPI Serial Clock SPI Slave Select (active low) I2C Clock** I2C Data**
* available on ST72589 version only. ** available on ST72589 version only. Port D4 and D5 in open-drain output only for ST72589.
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1.3 REGISTER & MEMORY MAP As shown in the Figure 3, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, up to 1Kbyte of RAM, 60 Figure 3. Memory Map
0000h
bytes of LCD RAM and up to 24Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors.
HW Registers (see Table 3)
007Fh 0080h
0080h
Short Addressing RAM (zero page)
00FFh 0100h
512 Bytes RAM 1024 Bytes RAM LCD RAM (60 Bytes) Reserved
047Fh 0480h 04BBh 04BCh 9FFFh A000h BFFFh C000h FFDFh FFE0h FFFFh
01FFh 0200h
Stack Area 256 Bytes 16-bit Addressing RAM
027Fh or 047Fh
Program Memory 24 KBytes Program Memory 16 KBytes Interrupt & Reset Vectors (see Table 1)
Table 2. Interrupt Vector Map
Vector Address FFE0-FFE1h FFE2-FFE3h FFE4-FFE5h FFE6-FFE7h FFE8-FFE9h FFEA-FFEBh FFEC-FFEDh FFEE-FFEFh FFF0-FFF1h FFF2-FFF3h FFF4-FFF5h FFF6-FFF7h FFF8-FFF9h FFFA-FFFBh FFFC-FFFDh FFFE-FFFFh Description I2C interrupt vector* SCI interrupt vector TIMER B interrupt vector TIMER A interrupt vector SPI interrupt vector CAN interrupt vector* Not used MCC interrupt vector External interrupt vector (EI5: port D) External interrupt vector (EI4: port C) External interrupt vector (EI3: port B) External interrupt vector (EI2: port A7..4) External interrupt vector (EI1: port A3..0) Non maskable external interrupt vector (NMI) TRAP (software) interrupt vector RESET vector Remarks Internal Interrupt
External Interrupt
CPU Interrupt
* available on ST72589 version only.
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Table 3. Hardware Register Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh to 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR MCC MCCSR ISPR0 ISPR1 ISPR2 ISPR3 MISCR1 SPIDR SPICR SPISR WDGCR PDDR PDDDR PDOR PCDR PCDDR PCOR PBDR PBDDR PBOR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved Area (1 Byte) Port C Data Register Port C Data Direction Register Port C Option Register Reserved Area (1 Byte) Port D Data Register Port D Data Direction Register Port D Option Register 00h 00h 00h R/W R/W R/W 00h 00h 00h R/W R/W R/W 00h 00h 00h R/W R/W R/W. Reset Status 00h 00h 00h Remarks R/W R/W R/W
Port A
Port B
Port C
Port D
Reserved Area (13 Bytes)
ITC
Interrupt Software Interrupt Software Interrupt Software Interrupt Software
Priority Register 0 Priority Register 1 Priority Register 2 Priority Register 3
FFh FFh FFh FFh 00h xxh 0xh 00h 7Fh
R/W R/W R/W R/W R/W R/W R/W Read Only R/W
Miscellaneous Register 1 SPI Data I/O Register SPI Control Register SPI Status Register Watchdog Control Register Reserved Area (1 Byte) Main Clock Control / Status Register Reserved Area (1 Byte) I2C Control Register I2C Status Register 1 I2C Status Register 2 I2C Clock Control Register I2C Own Address Register 1 I2C Own Address Register 2 I2C Data Register
SPI
WATCHDOG
00h
R/W
I2C*
00h 00h 00h 00h 00h 00h 00h
R/W Read Only Read Only R/W R/W R/W R/W
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Address 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h
Block
Register Label
Register Name
Reset Status
Remarks
Reserved Area (2 Bytes) TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR MISCR2 TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR LCD LCDCR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer A Control Register 2 A Control Register 1 A Status Register A Input Capture 1 High Register A Input Capture 1 Low Register A Output Compare 1 High Register A Output Compare 1 Low Register A Counter High Register A Counter Low Register A Alternate Counter High Register A Alternate Counter Low Register A Input Capture 2 High Register A Input Capture 2 Low Register A Output Compare 2 High Register A Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h 00h 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h C0h xxh 00xx xxxx xxh 00h 00h --00h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W R/W R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W R/W R/W
TIMER A
Miscellaneous Register 2 Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer B Control Register 2 B Control Register 1 B Status Register B Input Capture 1 High Register B Input Capture 1 Low Register B Output Compare 1 High Register B Output Compare 1 Low Register B Counter High Register B Counter Low Register B Alternate Counter High Register B Alternate Counter Low Register B Input Capture 2 High Register B Input Capture 2 Low Register B Output Compare 2 High Register B Output Compare 2 Low Register
TIMER B
SCI
SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register LCD Control Register Reserved Area (1 Byte)
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Address 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h
Block
Register Label CANISR CANICR CANCSR CANBRPR CANBTR CANPSR
Register Name CAN Interrupt Status Register CAN Interrupt Control Register CAN Control / Status Register CAN Baud Rate Prescaler Register CAN Bit Timing Register CAN Page Selection Register First address to Last address of CAN page X Data Register Control/Status Register Reserved Area (2 Bytes)
Reset Status 00h 00h 00h 00h 23h 00h --
Remarks R/W R/W R/W R/W R/W R/W See CAN Description
CAN*
ADC
ADCDR ADCCSR
xxh 00h
Read Only R/W
PWMBRM*
PWM0 BRM10 PWM1 PWM2 BRM32 PWM3
10-bit PWM / BRM Registers
00h 00h 00h 00h 00h 00h
R/W R/W R/W R/W R/W R/W
* Note: available on ST72589 version only.
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1.4 MEMORIES AND PROGRAMMING MODES 1.4.1 EPROM Program Memory The program memory of the OTP and EPROM devices can be programmed with EPROM programming tools available from STMicroelectronics EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents.
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2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES
s s s
2.3 CPU REGISTERS The 6 CPU registers shown in Figure 4 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
s s s s s
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 4. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 5). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 5. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 5. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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3 SUPPLY, RESET AND CLOCK MANAGEMENT
This chapter describes the following generic features to guaranty the ST7 correct operation. An overview is shown in Figure 6. s RESET Manager s Low Consumption Crystal Oscillators s Main Clock controller (MCC)
Figure 6. Clock and RESET Management Overview
MCO fOSC/2 fCPU OSC1 OSC2
MAIN OSCILLATOR
fOSC
MAIN CLOCK CONTROLLER (MCC)
MCC INTERRUPT
RESET
RESET
FROM WATCHDOG PERIPHERAL
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3.1 RESET MANAGER 3.1.1 Introduction There are three sources of Reset: - RESET pin (external source) - Power-On Reset (internal source) - WATCHDOG (internal source) Figure 7. Reset Block Diagram
VDD fCPU
INTERNAL RESET
The Reset Service Routine vector is located at address FFFEh-FFFFh.
RON
RESET
COUNTER POR
FETCH VECTOR
WATCHDOG RESET
3.1.2 External Reset The RESET pin is both an input and an open-drain output with integrated R ON weak pull-up resistor (see Figure 7). This pull-up has not a fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. A RESET signal originating from an external source must have a duration of at least tPULSE in Figure 8. External RESET Sequences
order to be recognized. The RESET sequence associated to this RESET source is shown in Figure 8. When the RESET is generated by a internal source, during the two first phases of the RESET sequence, the device RESET pin acts as an output that is pulled low.
RESET RUN
DELAY tPULSE EXTERNAL RESET SOURCE INTERNAL RESET 4096 CLOCK CYCLES
RUN
RESET PIN
WATCHDOG RESET
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RESET MANAGER (Cont'd) 3.1.3 Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter underflow is reduced to 2 phases (see Figure 9). Figure 9. Watchdog RESET Sequence RESET RUN
INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
RUN
EXTERNAL RESET SOURCE
RESET PIN
WATCHDOG RESET
WATCHDOG UNDERFLOW
3.1.4 Reset Operation The duration of the Reset condition, which is also reflected on the output pin, is fixed at 4096 internal CPU Clock cycles. A Reset signal originating from an external source must have a duration of at least 1.5 internal CPU Clock cycles in order to be recognised. At the end of the Power-On Reset cycle, the MCU may be held in the Reset condition by an External Reset signal. The RESET pin may thus be used to ensure V DD has risen to a point where the MCU can operate correctly before the User program is run. Following a Reset event, or after exiting Halt mode, a 4096 CPU Clock cycle delay period is initiated in order to allow the oscillator to stabilise and to ensure that recovery has taken place from the Reset state. During the Reset cycle, the device Reset pin acts as an output that is pulsed low. In its high state, an internal pull-up resistor is connected to the Reset pin. This resistor can be pulled low by external circuitry to reset the device.
3.1.5 Power-on Reset This circuit detects the ramping up of VDD, and generates a pulse that is used to reset the application at VPOR supply voltage. Power-On Reset is designed exclusively to cope with power-up conditions, and should not be used in order to attempt to detect a drop in the power supply voltage. Caution: to re-initialize the Power-On Reset, the power supply voltage must fall below VTN, prior to rise above VPOR. If this condition is not respected, on subsequent power-up the Reset pulse may not be generated. An external Reset pulse may be required to correctly reactivate the circuit.
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3.2 LOW CONSUMPTION OSCILLATOR The oscillator of the ST72589 and ST72389 devices is a Crystal/Ceramic Resonator Oscillator. Its architecture is based on a constant current to minimize the consumption. It can be used either with an external resonator or an external source. This oscillator allows a high accuracy to supply the clock for the ST7 CPU and its internal peripherals. Using a Crystal/Ceramic Resonator The resonator and the load capacitances have to be connected as shown in Figure 10 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Figure 10. Main Crystal/Ceramic Resonator
ST7 OSC1 OSC2
Using an External Clock Source In this mode, a square clock signal with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground (see Figure 11). Figure 11. Main External Clock Source
ST7 OSC1 OSC2
EXTERNAL SOURCE
CL1
LOAD CAPACITANCES
CL2
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3.3 MAIN CLOCK CONTROLLER (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows to manage the power saving modes such as the SLOW and ACTIVE-HALT modes. The whole functionality is managed by the Main Clock Control/Status Register (MCCSR) and the Miscellaneous Register 2 (MISCR2). The MCC block described in Figure 12 consists of: - a programmable CPU clock prescaler - a time base counter with interrupt capability - a clock-out signal to supply external devices The prescaler allows to select the main clock frequency and is controlled with three bits of the MCCSR: CP1, CP0 and SMS. The counter allows to generate an interrupt based on a accurate real time clock. Four different time bases depending directly on fOSC are available. The whole functionality is controlled by four bits of the MCCSR register: TB1, TB0, OIE and OIF. The clock-out capability allows to configure a dedicated I/O port pin as an fOSC/2 clock out to drive external devices. It is controlled by a bit in the MISCR2 register: MCO.
Figure 12. Main Clock Controller (MCC) Block Diagram
MAIN OSCILLATOR OSC2 DIV 2
OSC1
fOSC
PROGRAMMABLE DIVIDER
DIV 2, 4, 8, 16
SMS CP1 CP0
0
TB1 TB0
OIE
OIF
MCCSR
MCC INTERRUPT
fCPU
CPU CLOCK TO CPU AND PERIPHERALS CAN PERIPHERAL
PORT MCO ALTERNATE FUNCTION MCO -
MISCR2
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MAIN CLOCK CONTROLLER (Cont'd) MISCELLANEOUS REGISTER 2 (MISCR2) See description in MISCELLANEOUS Register Section. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read /Write Reset Value: 0000 0000 (00h)
7
SMS CP1 CP0 0 TB1 TB0 OIE
Bit 3:2 = TB1-TB0 Time base control These bits select the programmable divider time base. They are set and cleared by software.
Counter Prescaler 32000 64000 160000 400000 Time Base fOSC=8MHz 4ms 8ms 20ms 50ms fOSC=16MHz 2ms 4ms 10ms 25ms TB1 0 0 1 1 TB0 0 1 0 1
0
OIF
A modification of the time base is taken into account at the end of the current period (previously set) to avoid unwanted time shift. This allows to use this time base as a real time clock. Bit 1 = OIE Oscillator interrupt enable This bit set and cleared by software. 0: Oscillator interrupt disable 1: Oscillator interrupt enable This interrupt allows to exit from ACTIVE-HALT mode. When this bit is set, calling the ST7 software HALT instruction accesses the ACTIVEHALT power saving mode. Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has measured the selected elapsed time (TB1:0). 0: timeout not reached 1: timeout reached Warning: BRES and BSET instructions must not be used on the MCCSR register to avoid unwanted clearing of OIF bit.
Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU is given by CP1, CP0 See low power consumption mode and MCC chapters for more details. Bit 2:1 = CP1-CP0 CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software
fCPU in SLOW mode fOSC / 4 fOSC / 8 fOSC / 16 fOSC / 32 CP1 0 0 1 1 CP0 0 1 0 1
Bit 4 = Reserved, always read as 0.
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MAIN CLOCK CONTROLLER (Cont'd)
Table 4. Main Clock Controller Register Map and Reset Values
Address (Hex.) 0026h Register Label MCCSR Reset Value 7 SMS 0 6 CP1 0 5 CP0 0 4 3 TB1 0 2 TB0 0 1 OIE 0 0 OIF 0
0
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4 INTERRUPTS & POWER SAVING MODES
4.1 INTERRUPTS 4.1.1 Introduction The ST7 enhanced interrupt management provides the following features: s Hardware interrupts s Software interrupt (TRAP) s Nested or concurrent interrupt management with flexible interrupt priority and level management: - Up to 4 software programmable nesting levels - Up to 16 interrupt vectors fixed by hardware - 3 non maskable events: NMI, RESET, TRAP This interrupt management is based on: - Bit 5 and bit 3 of the CPU CC register (I1:0), - Interrupt software priority registers (ISPRx), - Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller. 4.1.2 Interrupt Masking and Processing Flow The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 5). The processing flow is shown in Figure 13 Figure 13. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y NMI Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
When an interrupt request has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 5. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: - the highest software priority interrupt is serviced, - if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 14 describes this decision process. Figure 14. Priority Decision Process
PENDING INTERRUPTS
Same
SOFTWARE PRIORITY
Different
I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode. s NMI (Non Maskable Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated NMI pin. Its detailed specification is given in the Miscellaneous register chapter. s TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart on Figure 13 as an NMI. s RESET The RESET source has the highest priority in the ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details. Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. s External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the Miscellaneous registers (MISCRx). External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed. s Peripheral Interrupts Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and NMI are non maskable and they can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable type (RESET, NMI, TRAP) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 13). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and
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INTERRUPTS (Cont'd) 4.1.3 Interrupts and Low Power Modes All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 14 Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. 4.1.4 Concurrent and Nested Interrupt Management The following Figure 15 and Figure 16 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 16 The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, NMI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
Figure 15. Concurrent interrupt management
NMI SOFTWARE PRIORITY LEVEL IT2 IT1 IT4 IT3 IT0 I1 I0
HARDWARE PRIORITY
NMI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 16. Nested interrupt management
SOFTWARE PRIORITY LEVEL
NMI
IT2
IT1
IT4
IT3
IT0
I1
I0
HARDWARE PRIORITY
NMI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
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INTERRUPTS (Cont'd) 4.1.5 Interrupt Register Description CPU CC REGISTER INTERRUPT BITS Read /Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Values: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: NMI, TRAP and RESET events are non maskable sources and can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. - Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondence is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
- Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. - Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and NMI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the NMI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd) Table 6. Dedicated Interrupt Instruction Set
Instruction HALT IRET JRM JRNM POP CC RIM SIM TRAP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 1 1 1 H I0 0 1 1 0 N Z C Function/Example I1 1 I1 H H I0 0 I0 N Z C N Z C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine.
Table 7. Interrupt Mapping
N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CAN* SPI TIMER A TIMER B SCIP I2C* NMI EI1 EI2 EI3 EI4 EI5 MCC Reset N/A Software Interrupt External Non Maskable Interrupt External Interrupt Port A3..0 External Interrupt Port A7..4 External Interrupt Port B6..0 External Interrupt Port C7..0 External Interrupt Port D7..0 Main Oscillator Time Base Interrupt Not used CAN Peripheral Interrupts SPI Peripheral Interrupts TIMER A Peripheral Interrupts TIMER B Peripheral Interrupts SCI Peripheral Interrupts I2C Peripheral Interrupts CANISR SPISR TASR TBSR SCISR I2CSRx Lowest Priority no MCCSR N/A MISCR1 Description Register Priority Label Order Highest Priority Exit from HALT yes no yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
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INTERRUPTS (Cont'd) Table 8. Nested Interrupts Register Map and Reset Values
Address (Hex.) 001Ch Register Label 7 EI3 ISPR0 Reset Value I1_3 1 ACC 001Dh ISPR1 Reset Value I1_7 1 I0_7 1 I1_6 1 I0_3 1 I1_2 1 MCC I0_6 1 I1_5 1 SPI I1_9 1 I2C 001Fh ISPR3 Reset Value 1 1 1 1 I1_13 1 I0_13 1 I1_12 1 I0_9 1 I1_8 1 SCI I0_12 1 6 5 EI2 I0_2 1 I1_1 1 EI5 I0_5 1 I1_4 1 CAN I0_8 1 4 3 EI1 I0_1 1 1 EI4 I0_4 1 2 1 NMI 1 0
TIMER B 001Eh ISPR2 Reset Value I1_11 1 I0_11 1
TIMER A I1_10 1 I0_10 1
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4.2 POWER SAVING MODES 4.2.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.
Figure 17. Power saving mode consumption / transitions
HALT Low
ACTIVE-HALT
SLOW WAIT
WAIT
SLOW
RUN High
POWER CONSUMPTION
4.2.2 HALT Modes The HALT modes are the lowest power consumption modes of the MCU. They are entered by executing the ST7 HALT instruction (see Figure 19). Two different HALT modes can be distinguished: - HALT: main oscillator is turned off, - ACTIVE-HALT: only main oscillator is running. The decision to enter either in HALT or ACTIVEHALT mode is given by the main oscillator enable interrupt flag (OIE bit in CROSS-MCCSR register: see Table 9). When entering HALT modes, the I1 and I0 bits in the CC Register are forced to level 0 ("10") to enable interrupts. The MCU can exit HALT or ACTIVE-HALT modes on reception of either an external interrupt, an in-
terrupt with Exit from Halt Mode capability or a reset (see Table 2). A 4096 CPU clock cycles delay is performed before the CPU operation resumes (see Figure 18). After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up. Table 9. HALT Modes selection
MCCSR OIE flag 0 1 Power Saving Mode entered when HALT instruction is executed HALT (reset if watchdog enabled) ACTIVE-HALT (no reset if watchdog enabled)
Figure 18. HALT /ACTIVE-HALT Modes timing overview
RUN
HALT OR ACTIVE-HALT
4096 CPU CYCLE DELAY
RUN
HALT INSTRUCTION
RESET OR INTERRUPT
FETCH VECTOR
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POWER SAVING MODES (Cont'd) Standard HALT mode In this mode the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external oscillator). The HALT instruction when executed while the Watchdog system is enabled, generates a Watchdog RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. Specific ACTIVE-HALT mode As soon as the interrupt capability of the main oscillator is selected (OIE bit set), the HALT instruction will make the device enter a specific ACTIVEHALT power saving mode instead of the standard HALT one. This mode consists of having only the main oscillator and its associated counter running to keep a wake-up time base. All other peripherals are not clocked except the ones which get their clock supply from another clock generator (such as external oscillator). The safeguard against staying locked in this ACTIVE-HALT mode is insured by the oscillator interrupt. Note: As soon as the interrupt capability of the oscillators is selected (OIE bit set), entering in ACTIVE-HALT mode while the Watchdog is active does not generate a RESET. This means that the device cannot to spend more than a defined delay in this power saving mode.
Figure 19. HALT modes flow-chart
HALT INSTRUCTION
N HALT OSCILLATOR PERIPHERALS CPU I1 AND I0 BITS OFF OFF OFF 10
WATCHDOG ENABLE
Y
0
MAIN OSCILLATOR OIE BIT
1 ACTIVE-HALT OSCILLATOR PERIPHERALS CPU I1 AND I0 BITS ON OFF OFF 10
N
RESET Y
4096 clock cycles delay
N
EXTERNAL* INTERRUPT OSCILLATOR PERIPHERALS CPU ON OFF OFF
OSCILLATOR PERIPHERALS CPU
ON ON ON
Y
FETCH RESET VECTOR OR SERVICE INTERRUPT**
Notes:
* External interrupt or internal interrupts with Exit from Halt Mode capability ** Before servicing an interrupt, the CC register is pushed on the stack.
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POWER SAVING MODES (Cont'd) 4.2.3 WAIT Mode WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I1 and I0 bits of the CC register are forced to level 0 ("10"), to enable all interrupts. All other registers and memory remain unchanged. The MCU Figure 20. WAIT mode flow-chart remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 20.
WFI INSTRUCTION
OSCILLATOR PERIPHERALS CPU I1 AND I0 BITS
ON ON OFF 10
N RESET N INTERRUPT Y OSCILLATOR PERIPHERALS CPU ON ON ON Y if exit caused by a RESET, a 4096 CPU clock cycle delay is inserted.
OSCILLATOR PERIPHERALS CPU
ON OFF* OFF
FETCH RESET VECTOR OR SERVICE INTERRUPT**
Note:
* The peripheral clock is stopped only when exit caused by RESET and not by an interrupt. ** Before servicing an interrupt, the CC register is pushed on the stack.
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POWER SAVING MODES (Cont'd) 4.2.4 SLOW Mode This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by three bits in the main oscillator CSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals (except CAN, see Note) are clocked at this lower frequency. Note: Before entering SLOW mode and in order to guarantee low power operation, the CAN peripheral must be placed by software in STANDBY mode.
Figure 21. SLOW Mode: timing diagram for internal CPU clock transitions
NEW FREQUENCY ACTIVE WHEN OSC/4 & OSC/8 = 0
NORMAL MODE ACTIVE (OSC/4, OSC/8 STOPPED)
fOSC/4 fOSC/8
fCPU
CP1:0
00
01 MAIN OSILLATOR
SMS
1
0
CSR
NEW FREQUENCY REQUEST NORMAL MODE REQUEST
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5 I/O PORTS
5.1 INTRODUCTION The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 5.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 1 5.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 2). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 5.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS VDD Open-drain Vss Floating
5.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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I/O PORTS (Cont'd) Figure 22. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 VDD 0 ALTERNATE ENABLE DR
P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERNAL INTERRUPT SOURCE (eix)
Table 10. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS
Output
Legend: NI - not implemented Off - implemented not activated On - implemented and activated
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DATA BUS
DR SEL
1 0
ALTERNATE INPUT FROM OTHER BITS
POLARITY SELECTION
NI (see note)
Note: The diode to V DD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
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I/O PORTS (Cont'd) Table 11. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONFIGURATION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
EXTERNAL INTERRUPT SOURCE (eix)
OPEN-DRAIN OUTPUT 2)
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
PUSH-PULL OUTPUT 2)
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
VDD RPU
DR REGISTER ACCESS
PAD
DR REGISTER
R/W
DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 5.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 2 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
Figure 23. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
The I/O port register configurations are summarized as follows.
Standard Interrupt Ports PA7:0, PB6:0, PC7:0, PD7:6, PD3:0
MODE floating input floating interrupt open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1
Open Drain Ports PD5:4
MODE floating input open drain output DDR 0 1
Dedicated Configurations Table 12. Port Configuration
Input Port Port A Port B Port C Pin name OR = 0 PA7:PA0 PB6:PB0 floating PC7:PC0 PD3:PD0 Port D PD5:PD4 PD7:PD6 floating floating floating interrupt open-drain open drain push-pull floating interrupt open drain push-pull OR = 1 OR = 0 OR = 1 Output
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I/O PORTS (Cont'd) 5.3.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C or D. Read /Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B, C or D. Read /Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bit 7:0 = D[7:0] Data Register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C or D. Read /Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bit 7:0 = O[7:0] Option Register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the floating interrupt capability or the basic floating configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: floating input with interrupt Output mode: 0: output open drain (with P-Buffer unactivated) 1: output push-pull
Bit 7:0 = DD[7:0] Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 13. I/O Port Register Map and Reset Values
Address (Hex.) Register Label 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Reset Value of all IO port registers 0000h 0001h 0002h 0004h 0005h 0006h 0008h 0009h 000Ah 000Ch 000Dh 000Eh PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDDR PDDDR PDOR
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
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6 MISCELLANEOUS REGISTERS
The Miscellaneous registers allow control over several features such as external interrupts or the I/O alternate functions. 6.1 I/O Port Interrupt Sensitivity Description The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous registers (Figure 24). This control allows to have 2 fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four different events on the pin: s Falling edge s Rising edge s Falling and rising edge s Falling edge and low level To guaranty the functionality, a modification of the sensitivity in the MISCR registers can be done only when the I1 and I0 bits of the CC register are both set to 1 (level 3). See I/O port register and Miscellaneous register descriptions for more details on the programming. Figure 24. External Interrupt Sources vs MISCR
MISCR1 IS11 IS10 EI1 INTERRUPT SOURCE
6.2 I/O Port Alternate Functions The MISCR registers allow to manage three I/O port miscellaneous alternate functions: s A Beep signal output on PC7 (with three selectable audio frequencies) s A NMI management on a dedicated pin s A SPI SS pin internal control to use the PD3 I/O port function while the SPI is active. These functions are described in details in the Section 6.3 Miscellaneous Registers Description.
SENSITIVITY CONTROL EI2 INTERRUPT SOURCE EI3 INTERRUPT SOURCE
PA3 PA2 PA1 PA0 PB6
SOURCES
SOURCES PB0
SOURCES
PA7 PA6 PA5 PA4 PC7
SOURCES PC0
EI4 INTERRUPT SOURCE
EI5 INTERRUPT SOURCE
PD7 SOURCES PD0
MISCR1 IS20 IS21
SENSITIVITY CONTROL
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MISCELLANEOUS REGISTERS (Cont'd) 6.3 Miscellaneous Registers Description MISCELLANEOUS REGISTER 1 (MISCR1) Read /Write Reset Value: 0000 0000 (00h)
7 0
MISCELLANEOUS REGISTER 2 (MISCR2) Read /Write Reset Value: 0000 0000 (00h)
7 0
IS11
IS10
IS21
IS20
0
0
NMIS NMIE
0
MCO
BC1
BC0
0
0
SSM
SSI
Bit 7:6 = IS11-IS10 EI1,3, 5 Sensitivity
ISx1 0 0 1 1 ISx0 0 1 0 1 External Interrupt Sensitivity Falling edge and low level Falling edge only Rising edge only Rising and falling edge
Bit 7 = Reserved. Bit 6:4 = MCO Main clock-out control BC1-BC0 Beep Control These 3 bits select the PC7 pin configuration. They are set and cleared by software.
MCO 0 1 X X X BC1 0 0 0 1 1 BC0 0 0 1 0 1 PC7 Configuration Standard I/O fOSC/2 Clock out Output Beep signal w/ fOSC=16MHz ~500-Hz ~50% duty cycle ~1-KHz ~2-KHz
The selection issued from IS11,IS10 combination is applied to the following external interrupts: EI1 (port A3..0) EI3 (port B) and EI5 (port D). These 2 bits can be written only when the current interrupt software priority in the CC (Condition Code) register is set to level 3 (I1:0=11). Bit 5:4 = IS21-IS20 EI2,4 Sensitivity The selection issued from IS21,IS20 combination is applied to the following external interrupts: EI2 (port A7..4) and EI4 (port C). The functional description is equal to the IS1x one. Bit 3:2 = Reserved, always read as 0. Bit 1 = NMIS NMI Sensitivity This bit allows to toggle the NMI edge sensitivity. It can be set and cleared by software only when NMIE bit is cleared. 0: falling edge 1: rising edge Bit 0 = NMIE NMI Enable This bit allows to enable or disable the NMI capability on the dedicated pin. It is set and cleared by software. 0: NMI disable 1: NMI enable
Note: the clock out and beep capabilities are not available in HALT modes. Bit 3:2 = Reserved, always read as 0. Bit 1 = SSM SS mode selection It is set and cleared by software. 0: Normal mode - SS uses information coming from the SS pin of the SPI. 1: I/O mode, the SPI uses the information stored into bit SSI. Bit 0 = SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software.
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MISCELLANEOUS REGISTERS (Cont'd) Table 14. Miscellaneous Register Map and Reset Values
Address (Hex.) 0020h 0040h Register Label MISCR1 Reset Value MISCR2 Reset Value 0 7 IS11 0 6 IS10 0 MCO 0 5 IS21 0 BC1 0 4 IS20 0 BC0 0 3 2 1 NMIS 0 SSM 0 0 NMI 0 SSI 0
0 0
0 0
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7 ON-CHIP PERIPHERALS
7.1 LCD DRIVER 7.1.1 Introduction The LCD driver controls up to 60 segments and 8 backplanes to drive up to 60x8 (480) or 60x4(240) LCD segments. Two programmable display modes (1/4 and 1/8 duty cycle) with 4 LCD drive frequencies can be selected by software. The parameters to display are stored in a 60-byte LCD dual port RAM. Four different main oscillator clocks can be selected as clock for the peripheral. - 8, 4, 2, 1 MHz fCPU software selectable. The peripheral can be switched off by software to reduce the power consumption while it is not used.
Figure 25. LCD Frequency Generator Block Diagram
fLCDin 16KHz MAIN OSCILLATOR
fCPU
CLOCK DIVIDER
CR DCS
0
CD1
CD0 LCDE
0
FS1
FS0
fFR
BACKPLANE MUX
fLCD 0.5...2KHz (SEG, COM)
DIV 8,16,24,32
7.1.2 Voltage references The display voltage levels are supplied by an external resistor chain as shown in Figure 26 This LCD driver needs 5 external voltage references through 5 pins (GLCD, 1/4VLCD, 1/2VLCD, 3/4VLCD, VLCD). The resistors used must have good tolerance matching within 1% to avoid DC voltage levels on the liquid crystal device. DC levels trigger electrode reactions in the liquid crystal cell, causing a rapid deterioration of the display quality. Note: To avoid damaging the device, VLCD supply voltages must always be supplied with more than VDD or they have to be left unconnected.
Figure 26. LCD External Supply Network EXTERNAL VLCD VLCD
CLCD1 CLCD2 CLCD3 RLCD1
3/4VLCD
RLCD2
1/2VLCD
RLCD3
1/4VLCD
RLCD4
GLCD
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LCD DRIVER (Cont'd) 7.1.3 Segment and Common Output signals Each dot of the LCD dot matrix panel is turned on when the differential voltage between the segment signal and the common signal increases over a certain threshold, it is turned off when the voltage is below the threshold voltage. The common signals determine the select timing within a frame cycle (see Figure 27). The common signals have similar waveforms to the segments, but different phases. Figure 27. Waveforms on LCD Outputs
VLCD 3/4 1/2 1/4 GND VLCD 3/4 1/2 1/4 GND
Each common signal shows a high signal amplitude (VLCD-VSS) only at the corresponding section of a frame time. At the other sections of the frame, the signal amplitude is low (3/4VLCD-1/ 4VLCD). A dot can be turned-on only at phases with high signal amplitude. In 1/8 duty cycle mode, one frame is divided into 8 sections, and each section is divided into two phases, phase 0 and 1. In 1/4 duty cycle mode, the number of sections is reduced to 4. This means the waveform pattern repeats faster in 1/4 duty cycle mode than 1/8 mode and the average voltage and the ON/OFF duty cycle on a selected pin is higher than in 1/8 mode. This results in a better contrast of the display. Note: The LCD must be disabled before entering HALT mode or ACTIVE HALT mode.
0101 Common selected
0101 Common off
VLCD 3/4 1/2 1/4 GND
0101 Segment selected
VLCD 3/4 1/2 1/4 GND
0101 Segment off
Figure 28. LCD outputs with 1/8 Multiplex
VLCD 3/4 1/2 1/4 GND VLCD 3/4 1/2 COM7 1/4 GND VLCD 3/4 1/2 SEG1 1/4 GND VLCD 3/4 1/2 SEG2 1/4 GND COM8
COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 01010101 010101
8
7
6
5
2
1
8
ONE FRAME PERIOD
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LCD DRIVER (Cont'd) 7.1.4 Register Description LCD CONTROL REGISTER (CR) Read /Write Reset Value: 0000 0000 (00h)
7 DCS 0 CD1 CD0 LCDE 0 FS1 0 FS0
Bit 2 = Reserved, must be kept cleared. Bit 1:0 = FS1,FS0 fFR Frame Frequency selection These two bits allow to select the LCD frame frequency based on the fLCDin frequency and the selected duty cycle. These bits are set and cleared by software. The following table gives the possible LCD segment frequency (fLCD) and LCD frame frequency (fFR) according to the selected duty cycle. With fLCDin=15625Hz (main oscillator)
fLCDin Ratio 1/8 1/16 1/24 1/32 fFR fLCD 1/4 d.c. 1953-Hz 977-Hz 651-Hz 488-Hz 488-Hz 244-Hz 163-Hz 122-Hz 1/8 d.c. 244-Hz 122-Hz 81-Hz 61-Hz 0 0 1 1 0 1 0 1 FS1 FS0
Bit 7 = DCS Duty cycle selection This bit is set and cleared by software. 0: 1/4 duty cycle selected 1: 1/8 duty cycle selected Bit 6 = Reserved, always read as 0. Bit 5:4 = CD1,CD0 Clock divider These bits allow to tune the fLCDin frequency to ~16KHz based on the selected fCPU. These bits are set and cleared by software.
fLCDin fCPU 8-MHz 4-MHz 15625Hz 2-MHz 1-MHz 1/128 1/64 1 0 0 1 Divider 1/512 1/256 CD1 0 1 CD0 0 1
Bit 3 = LCDE LCD enable This bit is set and cleared by software. 0: LCD disable 1: LCD enable While the LCD is disabled (LCDE bit cleared), GLCD is applied to all Segment and Common pins.
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LCD DRIVER (Cont'd) LCD RAM DESCRIPTION The LCD RAM is located in the data space in one page of 60 bytes. Each bit of the LCD RAM is mapped to one dot of the LCD matrix. If a bit is set,
the corresponding LCD dot is switched on, else the dot is switched off. After reset, the LCD RAM is not initialized and contains arbitrary information.
5 4 COM5 3 COM4 2 COM3 1 COM2 0 COM1
LCD RAM Bit position LCD Common
7 COM8
6 COM7
COM6
The bit position of the selected bit in the LCD RAM byte gives the common data. The segment data is given by the LCD RAM relative address.
LCD RAM Relative address LCD Segment 00h S1 01h S2 02h ................... S3 S58 S59 S60 39h 3Ah 3Bh
Table 15. LCD Driver Register Map and Reset Values
Address (Hex.) 0058h 0480h to 04BBh Register Label LCDCR Reset Value LCDRAM Reset Value 7 DCS 0 Seg X Com8 X 6 5 CD1 0 Seg X Com6 X 4 CD0 0 Seg X Com5 X 3 LCDE 0 Seg X Com4 X 2 1 FS1 0 Seg X Com2 X 0 FS0 0 Seg X Com1 X
0 Seg X Com7 X
0 Seg X Com3 X
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7.2 WATCHDOG TIMER (WDG) 7.2.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. Figure 29. Watchdog Block Diagram 7.2.2 Main Features Programmable timer (64 increments of 12288 CPU cycles) s Programmable reset s Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero
s
RESET
WATCHDOG CONTROL REGISTER (CR) WDGA T6
T5
T4
T3
T2
T1
T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER /12288
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WATCHDOG TIMER (Cont'd) 7.2.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 12,288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 16 . Watchdog Timing (fCPU = 8 MHz)): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 16. Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 98.304 1.536
7.2.4 Low Power Modes Mode WAIT HALT Description No effect on Watchdog. Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set).
7.2.5 Interrupts None. 7.2.6 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset.
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WATCHDOG TIMER (Cond't) Table 17. Watchdog Timer Register Map and Reset Values
Address (Hex.) 0024h Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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7.3 16-BIT TIMER 7.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 7.3.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s Output compare functions with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Input capture functions with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Pulse Width Modulation mode (PWM) s One Pulse mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 30. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 7.3.3 Functional Description 7.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 18 Clock Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 30. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE
8 high
8 low
8-bit buffer
8 high low
8 high
8 low
8 high
8 low
8 high
8 low
8
EXEDG
16
1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2
16
16
16
CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
EDGE DETECT CIRCUIT1
ICAP1 pin
6
EDGE DETECT CIRCUIT2
ICAP2 pin
LATCH1
ICF1 OCF1 TOF ICF2 OCF2 0
OCMP1 pin OCMP2 pin
0
0 LATCH2
(Status Register) SR
ICIE OCIE TOIE FOLV2 FOLV1OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
CC1
CC0 IEDG2 EXEDG
(Control Register 1) CR1
(Control Register 2) CR2
(See note) TIMER INTERRUPT
Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register).
Beginning of the sequence
At t0 Read MS Byte Other instructions Read At t0 +t LS Byte
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 7.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont'd) Figure 31. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 32. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 33. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
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16-BIT TIMER (Cont'd) 7.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see figure 5).
ICiR MS Byte ICiHR LS Byte ICiLR
The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available).
When an input capture occurs: - The ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 35). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh).
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16-BIT TIMER (Cont'd) Figure 34. Input Capture Block Diagram
ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1
ICIE
(Control Register 1) CR1
IEDG1
(Status Register) SR IC2R Register IC1R Register
ICF1 ICF2 0 0 0
16-BIT
(Control Register 2) CR2
CC1 CC0 IEDG2
16-BIT FREE RUNNING
COUNTER
Figure 35. Input Capture Timing Diagram
TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03
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16-BIT TIMER (Cont'd) 7.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCiE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
fCPU
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 18 Clock Control Bits)
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
If the timer clock is an external clock, the formula is:
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 37). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 38). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 36. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in either One-Pulse mode or PWM mode.
16 BIT FREE RUNNING COUNTER
OC1E OC2E
CC1
CC0
16-bit
OUTPUT COMPARE CIRCUIT
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
16-bit
16-bit
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 37. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 38. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 7.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 18 Clock Control Bits).
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 18 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 39). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.
One Pulse mode cycle
When event occurs on ICAP1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
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16-BIT TIMER (Cont'd) Figure 39. One Pulse Mode Timing Example
COUNTER ICAP1 OCMP1
FFFC FFFD FFFE
2ED0 2ED1 2ED2 2ED3
FFFC FFFD
OLVL2
OLVL1
OLVL2
compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
Figure 40. Pulse Width Modulation Mode Timing Example
COUNTER 34E2 FFFC FFFD FFFE OCMP1
2ED0 2ED1 2ED2
34E2
FFFC
OLVL2
OLVL1
OLVL2
compare2
compare1
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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16-BIT TIMER (Cont'd) 7.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value =
t * fCPU
PRESC
-5
Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 18 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 40) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.
Pulse Width Modulation cycle
When Counter = OC1R
OCMP1 = OLVL1
When Counter = OC2R
OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set
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16-BIT TIMER (Cont'd) 7.3.4 Low Power Modes
Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
7.3.5 Interrupts
Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 7.3.6 Summary of Timer modes
MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM Mode
1) 2)
Input Capture 1 Yes Yes No No
AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes No Partially 2) Not Recommended1) Not Recommended3) No No
See note 4 in Section 7.3.3.5 One Pulse Mode See note 5 in Section 7.3.3.5 One Pulse Mode 3) See note 4 in Section 7.3.3.6 Pulse Width Modulation Mode
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16-BIT TIMER (Cont'd) 7.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h)
7 0
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 18. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 ICF1 OCF1 TOF ICF2 OCF2 0 0 0 0
INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 MSB 0 LSB
OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 0 LSB
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event).
7 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 MSB 0 LSB
MSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 19. 16-Bit Timer Register Map and Reset Values
Address (Hex.) Register Label 7 ICIE 0 OC1E 0 ICF1 0 MSB MSB MSB MSB MSB MSB MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB 6 OCIE 0 OC2E 0 OCF1 0 5 TOIE 0 OPM 0 TOF 0 4 FOLV2 0 PWM 0 ICF2 0 3 FOLV1 0 CC1 0 OCF2 0 2 OLVL2 0 CC0 0 0 1 IEDG1 0 IEDG2 0 0 0 OLVL1 0 EXEDG 0 0 LSB LSB LSB LSB LSB LSB LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB -
Timer A: 32 CR1 Timer B: 42 Reset Value Timer A: 31 CR2 Timer B: 41 Reset Value Timer A: 33 SR Timer B: 43 Reset Value Timer A: 34 ICHR1 Timer B: 44 Reset Value Timer A: 35 ICLR1 Timer B: 45 Reset Value Timer A: 36 OCHR1 Timer B: 46 Reset Value Timer A: 37 OCLR1 Timer B: 47 Reset Value Timer A: 3E OCHR2 Timer B: 4E Reset Value Timer A: 3F OCLR2 Timer B: 4F Reset Value Timer A: 38 CHR Timer B: 48 Reset Value Timer A: 39 CLR Timer B: 49 Reset Value Timer A: 3A ACHR Timer B: 4A Reset Value Timer A: 3B ACLR Timer B: 4B Reset Value Timer A: 3C ICHR2 Timer B: 4C Reset Value Timer A: 3D ICLR2 Timer B: 4D Reset Value
1 1 1 1 -
1 1 1 1 -
1 1 1 1 -
1 1 1 1 -
1 1 1 1 -
1 0 1 0 -
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7.4 PWM/BRM GENERATOR (DAC) 7.4.1 Introduction This PWM/BRM peripheral includes a 6-bit Pulse Width Modulator (PWM) and a 4-bit Binary Rate Multiplier (BRM) Generator. It allows the digital to analog conversion (DAC) when used with external filtering. Note: The number of PWM and BRM channels available depends on the device. Refer to the device pin description and register map. 7.4.2 Main Features s Fixed frequency: fCPU/64 s Resolution: TCPU 10 (5mV if V =5V) s Steps of VDD/2 DD 7.4.3 Functional Description The 10 bits of the 10-bit PWM/BRM are distributed as 6 PWM bits and 4 BRM bits. The generator consists of a 10-bit counter (common for all channels), a comparator and the PWM/BRM generation logic. PWM Generation The counter increments continuously, clocked at internal CPU clock. Whenever the 6 least significant bits of the counter (defined as the PWM counter) overflow, the output level for all active channels is set. The state of the PWM counter is continuously compared to the PWM binary weight for each channel, as defined in the relevant PWM register, and when a match occurs the output level for that channel is reset. This Pulse Width modulated signal must be filtered, using an external RC network placed as close as possible to the associated pin. This provides an analog voltage proportional to the average charge passed to the external capacitor. Thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. The external components of the RC network should be selected for the filtering level required for control of the system variable. Each output may individually have its polarity inverted by software, and can also be used as a logical output.
Figure 41. PWM Generation
COUNTER 63 COMPARE VALUE OVERFLOW OVERFLOW OVERFLOW
000
t
PWM OUTPUT
t
TCPU x 64
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PWM/BRM GENERATOR (Cont'd) PWM/BRM Outputs The PWM/BRM outputs are assigned to dedicated pins. In these pins, the PWM/BRM outputs are connected to a serial resistor which must be taken into account to calculate the RC filter (see Figure 42). In any case, the RC filter time must be higher than TCPUx64. Figure 42. Typical PWM Output Filter
Table 20. 6-Bit PWM Ripple After Filtering
Cext (F) 0.128 1.28 12.8 V RIPPLE (mV) 78 7.8 0.78
OUTPUT STAGE
1K (max) Rint Rext
OUTPUT VOLTAGE Cext
With RC filter (R=1K), fCPU = 8 MHz VDD = 5V PWM Duty Cycle 50% R=Rint+R ext (Rext is optional). Note: after a reset these pins are tied low by default and are not in a high impedance state.
Figure 43. PWM Simplified Voltage Output After Filtering
V DD PWMOUT 0V V DD OUTPUT VOLTAGE Vripple (mV) V OUTAVG
0V "CHARGE" "DISCHARGE" "CHARGE" "DISCHARGE"
V
DD
PWMOUT 0V V DD V ripple (mV) OUTPUT VOLTAGE 0V "CHARGE" "DISCHARGE" "CHARGE" "DISCHARGE"
V OUTAVG
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PWM/BRM GENERATOR (Cont'd) BRM Generation The BRM bits allow the addition of a pulse to widen a standard PWM pulse for specific PWM cycles. This has the effect of "fine-tuning" the PWM Duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. The incremental pulses (with duration of T CPU) are added to the beginning of the original PWM pulse. The PWM intervals which are added to are specified in the 4-bit BRM register and are encoded as shown in the following table. The BRM values shown may be combined together to provide a summation of the incremental pulse intervals specified. The pulse increment corresponds to the PWM resolution. For example,if - Data 18h is written to the PWM register - Data 06h (00000110b) is written to the BRM register - with a 8MHz internal clock (125ns resolution) Then 3.0 s-long pulse will be output at 8 s intervals, except for cycles numbered 2,4,6,10,12,14, where the pulse is broadened to 3.125 s. Figure 44. BRM pulse addition (PWM > 0)
Note. If 00h is written to both PWM and BRM registers, the generator output will remain at "0". Conversely, if both registers hold data 3Fh and 0Fh, respectively, the output will remain at "1" for all intervals 1 to 15, but it will return to zero at interval 0 for an amount of time corresponding to the PWM resolution (TCPU). An output can be set to a continuous "1" level by clearing the PWM and BRM values and setting POL = "1" (inverted polarity) in the PWM register. This allows a PWM/BRM channel to be used as an additional I/O pin if the DAC function is not required.
Table 21. Bit BRM Added Pulse Intervals (Interval #0 not selected).
BRM 4 - Bit Data 0000 0001 0010 0100 1000 Incremental Pulse Intervals none i=8 i = 4,12 i = 2,6,10,14 i = 1,3,5,7,9,11,13,15
m=0 TCPU x 64
m=1 TCPU x 64
m=2 TCPU x 64
m = 15 TCPU x 64
TCPU x 64 increment
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PWM/BRM GENERATOR (Cont'd) Figure 45. Simplified Filtered Voltage Output Schematic with BRM Added
= VDD PWMOUT 0V VDD BRM = 1
OUTPUT VOLTAGE
=
BRM = 0
0V
TCPU
BRM EXTENDED PULSE
Figure 46. Graphical Representation of 4-Bit BRM Added Pulse Positions
BRM VALUE 0 1 2 3 4
PWM Pulse Number (0-15) 5 6 7 8 9 10 11 12 13 14 15
0001 bit0=1 0010 bit1=1 0100 bit2=1 1000 bit3=1 Examples 0110 1111
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PWM/BRM GENERATOR (Cont'd) Figure 47. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)
7.4.4 Register Description On a channel basis, the 10 bits are separated into two data registers: Note: The number of PWM and BRM channels available depends on the device. Refer to the device pin description and register map. PULSE BINARY WEIGHT REGISTERS (PWMi) Read / Write Reset Value 1000 0000 (80h)
7 1 POL P5 P4 P3 P2 P1 0 P0
BRM REGISTERS Read / Write Reset Value: 0000 0000 (00h)
7 B7 B6 B5 B4 B3 B2 B1 0 B0
These registers define the intervals where an incremental pulse is added to the beginning of the original PWM pulse. Two BRM channel values share the same register. Bit 7:4 = B[7:4] BRM Bits (channel i+1). Bit 3:0 = B[3:0] BRM Bits (channel i) Note: From the programmer's point of view, the PWM and BRM registers can be regarded as being combined to give one data value.
Bit 7 = Reserved (Forced by hardware to "1") Bit 6 = POL Polarity Bit for channel i. 0: The channel i outputs a "1" level during the binary pulse and a "0" level after. 1: The channel i outputs a "0" level during the binary pulse and a "1" level after. Bit 5:0 = P[5:0] PWM Pulse Binary Weight for channel i. This register contains the binary value of the pulse. For example :
1 POL P P P P P
P
+
B
B
B
B
Effective (with external RC filtering) DAC value
1 POL P P P P P P B B B B
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PWM/BRM GENERATOR (Cond't) Table 22. PWM Register Map and Reset Values
Address (Hex.) 74 75 76 77 78 79 Register Name PWM0 Reset Value BRM10 Reset Value PWM1 Reset Value PWM2 Reset Value BRM32 Reset Value PWM3 Reset Value 7 6 POL 0 B6 0 POL 0 POL 0 B6 0 POL 0 5 P5 0 B5 0 P5 0 P5 0 B5 0 P5 0 4 P4 0 B4 0 P4 0 P4 0 B4 0 P4 0 3 P3 0 B3 0 P3 0 P3 0 B3 0 P3 0 2 P2 0 B2 0 P2 0 P2 0 B2 0 P2 0 1 P1 0 B1 0 P1 0 P1 0 B1 0 P1 0 0 P0 0 B0 0 P0 0 P0 0 B0 0 P0 0
1 B7 0 1 1 B7 0 1
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7.5 SERIAL PERIPHERAL INTERFACE (SPI) 7.5.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller. Refer to the Pin Description chapter for the devicespecific pin-out. 7.5.2 Main Features s Full duplex, three-wire synchronous transfers s Master or slave operation s Four master mode frequencies s Maximum slave mode frequency = fCPU/4. s Four programmable master bit rates s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision flag protection s Master mode fault protection capability. 7.5.3 General description The SPI is connected to external devices through 4 alternate pins: - MISO: Master In Slave Out pin - MOSI: Master Out Slave In pin - SCK: Serial Clock pin - SS: Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 48. The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete. Four possible data/clock timing relationships may be chosen (see Figure 51) but master and slave must be programmed with the same timing mode.
Figure 48. Serial Peripheral Interface Master/Slave
MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK
SCK +5V
SS
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 49. Serial Peripheral Interface Block Diagram
Internal Bus Read Read Buffer
DR IT request
MOSI MISO
8-Bit Shift Register
SPIF WCOL - MODF -
SR
-
Write SPI STATE CONTROL
SCK SS
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL
SERIAL CLOCK GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4 Functional Description Figure 48 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: - A Control Register (CR) - A Status Register (SR) - A Data Register (DR) Refer to the CR, SR and DR registers in Section 7.5.7for the bit definitions. 7.5.4.1 Master Configuration In a master configuration, the serial clock is generated on the SCK pin. Procedure - Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register). - Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 51). - The SS pin must be connected to a high level signal during the complete byte transmit sequence. - The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a high level signal).
In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is written the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure - For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 51. - The SS pin must be connected to a low level signal during the complete byte transmit sequence. - Clear the MSTR bit and set the SPE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2.A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 7.5.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 7.5.4.4).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer. Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes. The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge. Figure 51, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. The SS pin is the slave device select input and can be driven by the master device.
The master device applies data to its MOSI pinclock edge before the capture clock edge. CPHA bit is set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition. No write collision should occur even if the SS pin stays low during a transfer of several bytes (see Figure 50). CPHA bit is reset The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition. The SS pin must be toggled high and low between each byte transmitted (see Figure 50). To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision.
Figure 50. CPHA / SS Timing Diagram
MOSI/MISO Master SS Slave SS (CPHA=0) Slave SS (CPHA=1)
Byte 1
Byte 2
Byte 3
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 51. Data Clock Timing Diagram
CPHA =1
SCLK (with CPOL = 1) SCLK (with CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
CPOL = 1
CPOL = 0
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
VR02131B
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. In Slave mode When the CPHA bit is set: The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the external MISO pin of the slave device. The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.
When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low. For this reason, the SS pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision. In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer. The SS pin signal must be always high on the master device. WCOL bit The WCOL bit in the SR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 52).
Figure 52. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SR OR
THEN
Read SR
THEN
2nd Step
Read DR
SPIF =0 WCOL=0
Write DR
SPIF =0 WCOL=0 if no transfer has started WCOL=1 if a transfer has started
before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SR
THEN
2nd Step
Read DR
WCOL=0
Note: Writing to the DR register instead of reading in it does not reset the WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: - The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. 7.5.4.6 Overrun Condition An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripheral.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.4.7 Single Master and Multimaster Configurations For more security, the slave device may respond There are two types of SPI systems: to the master with the received data byte. Then the - Single Master System master will receive the previous byte back from the - Multimaster System slave device if all MISO and MOSI pins are connected and the slave has not written its DR register. Single Master System Other transmission security methods can use A typical single master system may be configured, ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as mand fields. slaves (see Figure 53). Multi-master System The master device selects the individual slave deA multi-master system may also be configured by vices by using four pins of a parallel port to control the user. Transfer of master control could be imthe four SS pins of the slave devices. plemented using a handshake method through the The SS pins are pulled high during reset since the I/O ports or by an exchange of code messages master device ports will be forced to be inputs at through the serial peripheral interface system. that time, thus disabling the slave devices. The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit Note: To prevent a bus conflict on the MISO line in the SR register. the master allows only one active slave device during a transmission. Figure 53. Single Master Configuration
SS SCK Slave MCU MOSI MISO SCK Slave MCU
SS SCK Slave MCU
SS SCK Slave MCU
SS
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO SCK Master MCU 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.5 Low Power Modes
Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
7.5.6 Interrupts
Interrupt Event SPI End of Transfer Event Master Mode Fault Event Event Flag SPIF MODF Enable Control Bit SPIE Exit from Wait Yes Yes Exit from Halt No No
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 7.5.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh)
7
SPIE SPE SPR2 MSTR CPOL CPHA SPR1
0
SPR0
Bit 3 = CPOL Clock polarity. This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Bit 1:0 = SPR[1:0] Serial peripheral rate. These bits are set and cleared by software.Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. These 2 bits have no effect in slave mode. Table 23. Serial Peripheral Baud Rate
Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1
Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register Bit 6 = SPE Serial peripheral output enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 7.5.4.5 Master Mode Fault). 0: I/O port connected to pins 1: SPI alternate functions connected to pins The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 23. 0: Divider by 2 enabled 1: Divider by 2 disabled Bit 4 = MSTR Master. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 7.5.4.5 Master Mode Fault). 0: Slave mode is selected 1: Master mode is selected, the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
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SERIAL PERIPHERAL INTERFACE (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h)
7 SPIF WCOL MODF 0 -
DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been approved by a clearing sequence. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 52). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 7.5.4.5 Master Mode Fault). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused.
The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A read to the the DR register returns the value located in the buffer and not the contents of the shift register (See Figure 49 ).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table 24. SPI Register Map and Reset Values
Address (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPISR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x 0
x SPE 0 WCOL 0
x SPR2 0 0
x MSTR 0 MODF 0
x CPOL x 0
x CPHA x 0
x SPR1 x 0
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7.6 SERIAL COMMUNICATIONS INTERFACE (SCI) 7.6.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 7.6.2 Main Features s Full duplex, asynchronous communications s NRZ standard format (Mark/Space) s Dual baud rate generator systems s Independently programmable transmit and receive baud rates up to 250K baud using conventional baud rate generator and up to 500K baud using the extended baud rate generator. s Programmable data word length (8 or 9 bits) s Receive buffer full, Transmit buffer empty and End of Transmission flags s Two receiver wake-up modes: - Address bit (MSB) - Idle line s Muting function for multiprocessor configurations s LIN compatible (if MCU clock frequency tolerance 2%) s Separate enable bits for Transmitter and Receiver s Three error detection flags: - Overrun error - Noise error - Frame error s Five interrupt sources with flags: - Transmit data register empty - Transmission complete - Receive data register full - Idle line received - Overrun error detected 7.6.3 General Description The interface is externally connected to another device by two pins (see Figure 2.): - TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level. - RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Through this pins, serial data is transmitted and received as frames comprising: - An Idle Line prior to transmission or reception - A start bit - A data word (8 or 9 bits) least significant bit first - A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: - A conventional type for commonly-used baud rates, - An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies. 7.6.4 LIN Protocol support For LIN applications where resynchronization is not required (application clock tolerance less than or equal to 2%) the LIN protocol can be efficiently implemented with this standard SCI.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 54. SCI Block Diagram
Write
Read
(DATA REGISTER) DR
Transmit Data Register (TDR) TDO Transmit Shift Register RDI
Received Data Register (RDR)
Received Shift Register
CR1
R8 T8 M
WAKE
-
-
-
TRANSMIT CONTROL
WAKE UP UNIT
RECEIVER CONTROL
RECEIVER CLOCK
CR2
TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE
SR
-
SCI INTERRUPT CONTROL TRANSMITTER CLOCK TRANSMITTER RATE
fCPU
CONTROL
/16
/2
/PR BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.6.5 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1.. It contains 6 dedicated registers: - Two control registers (CR1 & CR2) - A status register (SR) - A baud rate register (BRR) - An extended prescaler receiver register (ERPR) - An extended prescaler transmitter register (ETPR) Refer to the register descriptions in Section 0.1.8 for the definitions of each bit.
7.6.5.1 Serial Data Format Word length may be selected as being either 8 or 9 bits by programming the M bit in the CR1 register (see Figure 1.). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of "1"s followed by the start bit of the next frame which contains data. A Break character is interpreted on receiving "0"s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra "1" bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator.
Figure 55. Word length programming 9-bit Word length (M bit is set) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Possible Parity Bit Bit8
Next Data Frame
Next Stop Start Bit Bit Start Bit
Idle Frame
Break Frame
Extra '1'
Start Bit
8-bit Word length (M bit is reset) Data Frame
Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible Parity Bit Bit7 Stop Bit
Next Data Frame
Next Start Bit Start Bit Extra Start Bit '1'
Idle Frame Break Frame
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.6.5.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the CR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 1.). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the BRR and the ETPR registers. - Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission. - Access the SR register and write the data to send in the DR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SR register 2. A write to the DR register The TDRE bit is set by hardware and it indicates: - The TDR register is empty. - The data transfer is beginning. - The next data can be written in the DR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write instruction to the DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. When no transmission is taking place, a write instruction to the DR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SR register 2. A write to the DR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 2.). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the DR.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.6.5.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, DR register consists in a buffer (RDR) between the internal bus and the received shift register (see Figure 1.). Procedure - Select the M bit to define the word length. - Select the desired baud rate using the BRR and the ERPR registers. - Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: - The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. - The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SR register 2. A read to the DR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SCI handles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
Overrun Error An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared. When a overrun error occurs: - The OR bit is set. - The RDR content will not be lost. - The shift register will be overwritten. - An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SR register followed by a DR register read operation. Noise Error Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. When noise is detected in a frame: - The NF is set at the rising edge of the RDRF bit. - Data is transferred from the Shift register to the DR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF bit is reset by a SR register read operation followed by a DR register read operation. Framing Error A framing error is detected when: - The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. - A break is received. When the framing error is detected: - the FE bit is set by hardware - Data is transferred from the Shift register to the DR register. - No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SR register read operation followed by a DR register read operation.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Figure 56. SCI Baud Rate and Extended Prescaler Block Diagram
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER
fCPU
TRANSMITTER RATE CONTROL
TRANSMITTER CLOCK
/16
/2
/PR BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 RECEIVER CLOCK RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.6.5.4 Conventional Baud Rate Generation than zero. The baud rates are calculated as follows: The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as fCPU fCPU follows: Rx = Tx = fCPU fCPU 16*ERPR 16*ETPR Rx = Tx = (32*PR)*RR (32*PR)*TR with: with: ETPR = 1,..,255 (see ETPR register) PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) ERPR = 1,.. 255 (see ERPR register) TR = 1, 2, 4, 8, 16, 32, 64,128 7.6.5.6 Receiver Muting and Wake-up Feature (see SCT0, SCT1 & SCT2 bits) In multiprocessor configurations it is often desirable that only the intended message recipient RR = 1, 2, 4, 8, 16, 32, 64,128 should actively receive the full message contents, (see SCR0,SCR1 & SCR2 bits) thus reducing redundant SCI service overhead for All this bits are in the BRR register. all non addressed receivers. Example: If fCPU is 8 MHz (normal mode) and if The non addressed devices may be placed in PR=13 and TR=RR=1, the transmit and receive sleep mode by means of the muting function. baud rates are 19200 baud. Setting the RWU bit by software puts the SCI in Caution: The baud rate register (SCIBRR) MUST sleep mode: NOT be written to (changed or refreshed) while the All the reception status bits can not be set. transmitter or the receiver is enabled. All the receive interrupt are inhibited. 7.6.5.5 Extended Baud Rate Generation A muted receiver may be awakened by one of the The extended prescaler option gives a very fine following two ways: tuning on the baud rate, using a 255 value prescal- by Idle Line detection if the WAKE bit is reset, er, whereas the conventional Baud Rate Generator retains industry standard software compatibili- by Address Mark detection if the WAKE bit is set. ty. Receiver wakes-up by Idle Line detection when The extended baud rate generator block diagram the Receive line has recognised an Idle Frame. is described in the Figure 3.. Then the RWU bit is reset by hardware but the IDLE bit is not set. The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider Receiver wakes-up by Address Mark detection divided by a factor ranging from 1 to 255 set in the when it received a "1" as the most significant bit of ERPR or the ETPR register. a word, thus indicating that the message is an address. The reception of this particular word wakes Note: the extended prescaler is activated by setup the receiver, resets the RWU bit and sets the ting the ETPR or ERPR register to a value other RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.6.6 Low Power Modes Mode WAIT HALT Description No effect on SCI. SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
7.6.7 Interrupts
Interrupt Event Transmit Data Register Empty Transmission Complete Received Data Ready to be Read Overrrun Error Detected Idle Line Detected Event Flag Enable Control Bit TDRE TIE TC TCIE RDRF RIE OR IDLE ILIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No
The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) 7.6.8 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h)
7
TDRE TC RDRF IDLE OR NF FE
Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line occurs). This bit is not set by an idle line when the receiver wakes up from wake-up mode. Bit 3 = OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten. Bit 2 = NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. Bit 1 = FE Framing error. This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Unused.
0 -
Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: data will not be transferred to the shift register as long as the TDRE bit is not reset. Bit 6 = TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register). 0: Transmission is not complete 1: Transmission is complete Bit 5 = RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: Data is not received 1: Received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Idle Line is detected 1: Idle Line is detected
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) CONTROL REGISTER 1 (CR1) 1: An SCI interrupt is generated whenever TC=1 in the SR register Read/Write Reset Value: Undefined Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 7 0 0: interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 R8 T8 M WAKE or RDRF=1 in the SR register Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00 h)
7
TIE TCIE RIE ILIE TE RE RWU
Bit 4 = ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SR register. Bit 3 = TE Transmitter enable. This bit enables the transmitter and assigns the TDO pin to the alternate function. It is set and cleared by software. 0: Transmitter is disabled, the TDO pin is back to the I/O port configuration. 1: Transmitter is enabled Note: during transmission, a "0" pulse on the TE bit ("0" followed by "1") sends a preamble after the current word. Bit 2 = RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled. 1: Receiver is enabled and begins searching for a start bit. Bit 1 = RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode 1: Receiver in mute mode Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to "1" and then to "0", the transmitter will send a BREAK word at the end of the current word.
0 SBK
Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SR register. Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software. 0: interrupt is inhibited
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to.
7
DR7 DR6 DR5 DR4 DR3 DR2 DR1
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
TR dividing factor 1 2 4 8 16 32 64 128 SCT2 0 0 0 0 1 1 1 1 SCT1 0 0 1 1 0 0 1 1 SCT0 0 1 0 1 0 1 0 1
0
DR0
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 1.). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 1.). BAUD RATE REGISTER (BRR) Read/Write Reset Value: 00xx xxxx (XXh)
7
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2
0
SCR1 SCR0
Note: this TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR is replaced by the ETPR dividing factor. Bit 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode.
RR dividing factor 1 2 4 8 16 32 64 128 SCR2 0 0 0 0 1 1 1 1 SCR1 0 0 1 1 0 0 1 1 SCR0 0 1 0 1 0 1 0 1
Bit 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges:
PR Prescaling factor 1 3 4 13 SCP1 0 0 1 1 SCP0 0 1 0 1
Note: this RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the ERPR dividing factor.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate division factor for the receive circuit.
7 0
EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (ETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate division factor for the transmit circuit.
7
ETPR 7 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2
0
ETPR ETPR 1 0
ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR 7 6 5 4 3 2 1 0
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ERPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset.
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ETPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset.
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SERIAL COMMUNICATIONS INTERFACE (Cont'd) Table 25. SCI Register Map and Reset Values
Address (Hex.) 50 51 52 53 54 55 57 Register Label SCISR Reset Value SCIDR Reset Value SCIBRR Reset Value SCICR1 Reset Value SCICR2 Reset Value SCIPBRR Reset Value SCIPBRT Reset Value 7 TDRE 1 MSB x SCP1 0 R8 x TIE 0 MSB 0 MSB 0 6 TC 1 x SCP0 0 T8 x TCIE 0 0 0 5 RDRF 0 x SCT2 x 0 RIE 0 0 0 4 IDLE 0 x SCT1 x M x ILIE 0 0 0 3 OR 0 x SCT0 x WAKE x TE 0 0 0 2 NF 0 x SCR2 x 0 RE 0 0 0 1 FE 0 x SCR1 x 0 RWU 0 0 0 0
0 LSB x SCR0 x 0 SBK 0 LSB 0 LSB 0
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7.7 I2C BUS INTERFACE (I2C) 7.7.1 Introduction The I 2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It provides both multimaster and slave functions, and controls all I 2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C mode (400kHz). 7.7.2 Main Features 2 s Parallel-bus/I C protocol converter s Multi-master capability s 7-bit/10-bit Addressing s Transmitter/Receiver flag s End-of-byte transmission flag s Transfer problem detection I2C Master Features: s Clock generation 2 s I C bus busy flag s Arbitration Lost Flag s End of byte transmission flag s Transmitter/Receiver Flag s Start bit detection flag s Start and Stop generation I2C Slave Features: s Stop bit detection 2 s I C bus busy flag s Detection of misplaced start or stop condition 2 s Programmable I C Address detection s Transfer problem detection s End-of-byte transmission flag s Transmitter/Receiver flag 7.7.3 General Description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled Figure 57. I2C BUS Protocol SDA MSB SCL 1 START CONDITION 2 8 9 STOP CONDITION
VR02119B
handshake. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a Fast I2C bus. This selection is made by software. Mode Selection The interface can operate in the four following modes: - Slave transmitter/receiver - Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability. Communication Flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 57.
ACK
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I2C BUS INTERFACE (Cont'd) Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call address can be selected by software. The speed of the I2C interface may be selected between Standard (0-100KHz) and Fast I 2C (100400KHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. Figure 58. I2C Interface Block Diagram
The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
DATA REGISTER (DR)
SDA or SDAI
DATA CONTROL DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1) OWN ADDRESS REGISTER 2 (OAR2)
SCL or SCLI
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) STATUS REGISTER 2 (SR2) CONTROL LOGIC
INTERRUPT
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I2C BUS INTERFACE (Cont'd) 7.7.4 Functional Description Refer to the CR, SR1 and SR2 registers in Section 7.7.7. for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register. 7.7.4.1 Slave Mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). Note: In 10-bit addressing mode, the comparision includes the header sequence (11110xx0) and the two most significant bits of the address. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set. Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: - Acknowledge pulse if the ACK bit is set. - EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 59 Transfer sequencing EV1). Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode. In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1) . Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: - Acknowledge pulse if the ACK bit is set
- EVF and BTF bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV2). Slave Transmitter Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV3). When the acknowledge pulse is received: - The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: - EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 59 Transfer sequencing EV4). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. Note: In both cases, SCL line is not held low; however, SDA line can remain low due to possible 0 bits transmitted last. It is then necessary to release both lines by software.
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I2C BUS INTERFACE (Cont'd) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. 7.7.4.2 Master Mode To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent: - The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see Figure 59 Transfer sequencing EV5). Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the following event: - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV9). Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set): - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 59 Transfer sequencing EV6). Next the master must enter Receiver or Transmitter mode. Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). Master Receiver Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: - Acknowledge pulse if if the ACK bit is set - EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV7). To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.
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I2C BUS INTERFACE (Cont'd) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: - EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Error Cases - BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and
BERR bits are set by hardware with an interrupt if ITE is set. - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit. - ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible 0 bits transmitted last. It is then necessary to release both lines by software.
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I2C BUS INTERFACE (Cont'd) Figure 59. Transfer Sequencing 7-bit Slave receiver:
S Address A EV1 Data1 A EV2 Data2 A EV2 ..... DataN A EV2 P EV4
7-bit Slave transmitter:
S Address A EV1 EV3 Data1 A EV3 Data2 A EV3 ..... DataN NA EV3-1 P EV4
7-bit Master receiver:
S EV5 Address A EV6 Data1 A EV7 Data2 A EV7 ..... DataN NA EV7 P
7-bit Master transmitter:
S EV5 Address A EV6 EV8 Data1 A EV8 Data2 A EV8 ..... DataN A EV8 P
10-bit Slave receiver:
S Header A Address A EV1 Data1 A EV2 ..... DataN A EV2 P EV4
10-bit Slave transmitter:
Sr Header A EV1 EV3 Data1 A .... DataN EV3 . A EV3-1 P EV4
10-bit Master transmitter
S EV5 Header A EV9 Address A EV6 EV8 Data1 A EV8 ..... DataN A EV8 P
10-bit Master receiver:
Sr EV5 Header A EV6 Data1 A EV7 ..... DataN A EV7 P
Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt if ITE=1) EV1: EVF=1, ADSL=1, cleared by reading SR1 register. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
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I2C BUS INTERFACE (Cont'd) 7.7.5 Low Power Modes
Mode
2
Description No effect on I C interface. I2C interrupts cause the device to exit from WAIT mode. I2C registers are frozen. In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
WAIT HALT
7.7.6 Interrupts Figure 60. Event Flags and Interrupt Generation
ADD10 BTF ADSL SB AF STOPF ARLO BERR ITE INTERRUPT
EVF
* * EVF can also be set by EV6 or an error from the SR2 register.
Event Flag ADD10 BTF ADSEL SB AF STOPF ARLO BERR Enable Control Bit Exit from Wait Yes Yes Yes Yes Yes Yes Yes Yes Exit from Halt No No No No No No No No
Interrupt Event 10-bit Address Sent Event (Master mode) End of Byte Transfer Event Address Matched Event (Slave mode) Start Bit Generation Event (Master mode) Acknowledge Failure Event Stop Detection Event (Slave mode) Arbitration Lost Event (Multimaster configuration) Bus Error Event
ITE
Note: The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).
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I2C BUS INTERFACE (Cont'd) 7.7.7 Register Description I2C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 PE ENGC START ACK STOP 0 ITE
Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). - In master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. - In slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 60 for the relationship between the events and the interrupt. SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 59) is detected.
Bit 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: - When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 - When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. - To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4 = ENGC Enable General Call. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). - In master mode: 0: No start generation 1: Repeated start generation - In slave mode: 0: No start generation 1: Start generation when the bus is free
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I2C BUS INTERFACE (Cont'd) I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h)
7 EVF ADD10 TRA BUSY BTF ADSL M/SL 0 SB
arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4 = BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. This information is still updated when the interface is disabled (PE=0). 0: No communication on the bus 1: Communication ongoing on the bus Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). - Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 59). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. - Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched
Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 59. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: - BTF=1 (Byte received or transmitted) - ADSL=1 (Address matched in Slave mode while ACK=1) - SB=1 (Start condition generated in Master mode) - AF=1 (No acknowledge received after byte transmission) - STOPF=1 (Stop condition detected in Slave mode) - ARLO=1 (Arbitration lost in Master mode) - BERR=1 (Bus error, misplaced Start or Stop condition detected) - ADD10=1 (Master has sent header byte) - Address byte successfully transmitted in Master mode. Bit 6 = ADD10 10-bit addressing in Master mode. This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0). 0: No ADD10 event occurred. 1: Master has sent first address byte (header) Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus
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I2C BUS INTERFACE (Cont'd) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated I2C STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h)
7 0 0 0 AF 0 STOPF ARLO BERR GCAL
Bit 2 = ARLO Arbitration lost. This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Bit 1 = BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Bit 0 = GCAL General Call (Slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus
Bit 7:5 = Reserved. Forced to 0 by hardware. Bit 4 = AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1. 0: No acknowledge failure 1: Acknowledge failure Bit 3 = STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected
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I2C BUS INTERFACE (Cont'd) I2C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h)
7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 0 CC0
I2C DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = FM/SM Fast/Standard I2C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I2C mode 1: Fast I2C mode Bit 6:0 = CC[6:0] 7-bit clock divider. These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not cleared when the interface is disabled (PE=0). - Standard mode (FM/SM=0): FSCL <= 100kHz FSCL = FCPU/(2x([CC6..CC0]+2)) - Fast mode (FM/SM=1): FSCL > 100kHz FSCL = FCPU/(3x([CC6..CC0]+2)) Note: The programmed FSCL assumes no load on SCL and SDA lines.
Bit 7:0 = D[7:0] 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. - Transmitter mode: Byte transmission start automatically when the software writes in the DR register. - Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register.
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I2C BUS INTERFACE (Cont'd) I2C OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h)
7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 0 ADD0
I2C OWN ADDRESS REGISTER (OAR2) Read / Write Reset Value: 0100 0000 (40h)
7 FR1 FR0 0 0 0 ADD9 ADD8 0 0
7-bit Addressing Mode Bit 7:1 = ADD[7:1] Interface address. These bits define the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 0 = ADD0 Address direction bit. This bit is don't care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. 10-bit Addressing Mode Bit 7:0 = ADD[7:0] Interface address. These are the least significant bits of the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0).
Bit 7:6 = FR[1:0] Frequency bits. These bits are set by software only when the interface is disabled (PE=0). To configure the interface to I2C specifed delays select the value corresponding to the microcontroller frequency FCPU.
fCPU < 6 MHz 6 to 8 MHz FR1 0 0 FR0 0 1
Bit 5:3 = Reserved Bit 2:1 = ADD[9:8] Interface address. These are the most significant bits of the I2C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0). Bit 0 = Reserved.
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I2C BUS INTERFACE (Cont'd) Table 26. I2C Register Map and Reset Values
Address (Hex.) 28 29 2A 2B 2C 2D 2E Register Label I2CCR Reset Value I2CSR1 Reset Value I2CSR2 Reset Value I2CCCR Reset Value I2COAR1 Reset Value I2COAR2 Reset Value I2CDR Reset Value 7 6 5 PE 0 TRA 0 0 CC5 0 ADD5 0 0 0 4 ENGC 0 BUSY 0 AF 0 CC4 0 ADD4 0 0 0 3 START 0 BTF 0 STOPF 0 CC3 0 ADD3 0 0 0 2 ACK 0 ADSL 0 ARLO 0 CC2 0 ADD2 0 ADD9 0 0 1 STOP 0 M/SL 0 BERR 0 CC1 0 ADD1 0 ADD8 0 0 0 ITE 0 SB 0 GCAL 0 CC0 0 ADD0 0 0 LSB 0
0 EVF 0 0 FM/SM 0 ADD7 0 FR1 0 MSB 0
0 ADD10 0 0 CC6 0 ADD6 0 FR0 1 0
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7.8 CONTROLLER AREA NETWORK (CAN) 7.8.1 Introduction This peripheral is designed to support serial data exchanges using a multi-master contention based priority scheme as described in CAN specification Rev. 2.0 part A. It can also be connected to a 2.0 B network without problems, since extended frames Figure 61. CAN Block Diagram
ST7 Internal Bus
are checked for correctness and acknowledged accordingly although such frames cannot be transmitted nor received. The same applies to overload frames which are recognized but never initiated.
ST7 Interface
TX/RX Buffer 1 10 Bytes
TX/RX Buffer 2 10 Bytes
TX/RX Buffer 3 10 Bytes
ID Filter 0 4 Bytes
ID Filter 1 4 Bytes
PSR
BRPR
BTR
RX
BTL
BCDL
SHREG
ICR
ISR TX EML CRC CSR
CAN 2.0B passive Core
TECR
RECR
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CONTROLLER AREA NETWORK (Cont'd) 7.8.2 Main Features - Support of CAN specification 2.0A and 2.0B passive - Three prioritized 10-byte Transmit/Receive message buffers - Two programmable global 12-bit message acceptance filters - Programmable baud rates up to 1 MBit/s - Buffer flip-flopping capability in transmission - Maskable interrupts for transmit, receive (one per buffer), error and wake-up - Automatic low-power mode after 20 recessive bits or on demand (standby mode) - Interrupt-driven wake-up from standby mode upon reception of dominant pulse - Optional dominant pulse transmission on leaving standby mode - Automatic message queuing for transmission upon writing of data byte 7 - Programmable loop-back mode for self-test operation - Advanced error detection and diagnosis functions - Software-efficient buffer mapping at a unique address space - Scalable architecture. 7.8.3 Functional Description 7.8.3.1 Frame Formats A summary of all the CAN frame formats is given in Figure 62 for reference. It covers only the standard frame format since the extended one is only acknowledged. A message begins with a start bit called Start Of Frame (SOF). This bit is followed by the arbitration field which contains the 11-bit identifier (ID) and the Remote Transmission Request bit (RTR). The RTR bit indicates whether it is a data frame or a remote request frame. A remote request frame does not have any data byte. The control field contains the Identifier Extension bit (IDE), which indicates standard or extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes (DLC). The data field ranges from zero to eight bytes and is followed by the Cyclic Redundancy Check (CRC) used as a frame integrity check for detecting bit errors. The acknowledgement (ACK) field comprises the ACK slot and the ACK delimiter. The bit in the ACK slot is placed on the bus by the transmitter as a recessive bit (logical 1). It is overwritten as a dominant bit (logical 0) by those receivers which have at this time received the data correctly. In this way, the transmitting node can be assured that at least one receiver has correctly received its message. Note that messages are acknowledged by the receivers regardless of the outcome of the acceptance test. The end of the message is indicated by the End Of Frame (EOF). The intermission field defines the minimum number of bit periods separating consecutive messages. If there is no subsequent bus access by any station, the bus remains idle. 7.8.3.2 Hardware Blocks The CAN controller contains the following functional blocks (refer to Figure 61): - ST7 Interface: buffering of the ST7 internal bus and address decoding of the CAN registers. - TX/RX Buffers: three 10-byte buffers for transmission and reception of maximum length messages. - ID Filters: two 12-bit compare and don't care masks for message acceptance filtering. - PSR: page selection register (see memory map). - BRPR: clock divider for different data rates. - BTR: bit timing register. - ICR: interrupt control register. - ISR: interrupt status register. - CSR: general purpose control/status register. - TECR: transmit error counter register. - RECR: receive error counter register. - BTL: bit timing logic providing programmable bit sampling and bit clock generation for synchronization of the controller. - BCDL: bit coding logic generating a NRZ-coded datastream with stuff bits. - SHREG: 8-bit shift register for serialization of data to be transmitted and parallelisation of received data. - CRC: 15-bit CRC calculator and checker. - EML: error detection and management logic. - CAN Core: CAN 2.0B passive protocol controller.
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CONTROLLER AREA NETWORK (Cont'd) Figure 62. CAN Frames
Inter-Frame Space or Overload Frame
Inter-Frame Space
Data Frame 44 + 8 * N
Arbitration Field Control Field Data Field 12 ID RTR IDE r0 SOF 6 DLC 8*N
CRC Field 16 CRC
Ack Field 2
7 EOF
Inter-Frame Space
Remote Frame 44
Arbitration Field Control Field 12 ID RTR IDE r0 SOF 6 DLC
CRC Field 16 CRC
Ack Field 2
End Of Frame 7
Data Frame or Remote Frame
Error Frame
Inter-Frame Space or Overload Frame
Error Flag Flag Echo Error Delimiter 6 6 8
Any Frame
Inter-Frame Space Bus Idle
Data Frame or Remote Frame
Notes: *0 <= N <= 8 * SOF = Start Of Frame
Suspend Intermission Transmission 3 8
* ID = Identifier * RTR = Remote Transmission Request * IDE = Identifier Extension Bit * r0 = Reserved Bit * DLC = Data Length Code
End Of Frame or Error Delimiter or Overload Delimiter
Overload Frame
Inter-Frame Space or Error Frame
* CRC = Cyclic Redundancy Code * Error flag: 6 dominant bits if node is error active else 6 recessive bits. * Suspend transmission: applies to error passive nodes only. * EOF = End of Frame * ACK = Acknowledge bit
Overload Flag Overload Delimiter 6 8
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ACK
ACK Inter-Frame Space or Overload Frame
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CONTROLLER AREA NETWORK (Cont'd) 7.8.3.3 Modes of Operation The CAN Core unit assumes one of the seven states described below: - STANDBY. Standby mode is entered either on a chip reset or on resetting the RUN bit in the Control/Status Register (CSR). Any on-going transmission or reception operation is not interrupted and completes normally before the Bit Time Logic and the clock prescaler are turned off for minimum power consumption. This state is signalled by the RUN bit being read-back as 0. Once in standby, the only event monitored is the reception of a dominant bit which causes a wakeup interrupt if the SCIE bit of the Interrupt Control Figure 63. CAN Controller State Diagram
ARESET
Register (ICR) is set. The STANDBY mode is left by setting the RUN bit. If the WKPS bit is set in the CSR register, then the controller passes through WAKE-UP otherwise it enters RESYNC directly. It is important to note that the wake-up mechanism is software-driven and therefore carries a significant time overhead. All messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored. - WAKE-UP. The CAN bus line is forced to dominant for one bit time signalling the wake-up condition to all other bus members.
RUN & WKPS STANDBY
RUN
RUN & WKPS
WAKE-UP
RESYNC
FSYN & BOFF & 11 Recessive bits | (FSYN | BOFF) & 128 * 11 Recessive bits
RUN IDLE Write to DATA7 | TX Error & NRTX TX OK RX OK Start Of Frame
Arbitration lost TRANSMISSION RECEPTION
TX Error
RX Error BOFF ERROR BOFF
n
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CONTROLLER AREA NETWORK (Cont'd) - RESYNC. The resynchronization mode is used to find the correct entry point for starting transmission or reception after the node has gone asynchronous either by going into the STANDBY or bus-off states. Resynchronization is achieved when 128 sequences of 11 recessive bits have been monitored unless the node is not bus-off and the FSYN bit in the CSR register is set in which case a single sequence of 11 recessive bits needs to be monitored. - IDLE. The CAN controller looks for one of the following events: the RUN bit is reset, a Start Of Frame appears on the CAN bus or the DATA7 register of the currently active page is written to. - TRANSMISSION. Once the LOCK bit of a Buffer Control/Status Register (BCSRx) has been set and read back as such, a transmit job can be submitted by writing to the DATA7 register. The message with the highest priority will be transmitted as soon as the CAN bus becomes idle. Among those messages with a pending transmission request, the highest priority is given to Buffer 3 then 2 and 1. If the transmission fails due to a lost arbitration or to an error while the NRTX bit of the CSR register is reset, then a new transmission attempt is performed . This goes on until the transmission ends successfully or until the job is cancelled by unlocking the buffer, by setting the NRTX bit or if the node ever enters busoff or if a higher priority message becomes pending. The RDY bit in the BCSRx register, which was set since the job was submitted, gets reset. When a transmission is in progress, the BUSY bit in the BCSRx register is set. If it ends successfully then the TXIF bit in the Interrupt Status Register (ISR) is set, else the TEIF bit is set. An interrupt is generated in either case provided the TXIE and TEIE bits of the ICR register are set. The ETX bit in the same register is used to get an early transmit interrupt and to automatically unlock the transmitting buffer upon successful completion of its job. This enables the CPU to get a new transmit job pending by the end of the current transmission while always leaving two buffers available for reception. An uninterrupted stream of messages may be transmitted in this way at no overrun risk. Note 1: Setting the SRTE bit of the CSR register allows transmitted messages to be simultaneously received when they pass the acceptance filtering. This is particularly useful for checking the integrity of the communication path. Note 2: When the ETX bit is reset, the buffer with the highest priority and with a pending transmission request is always transmitted. When the ETX bit is set, once a buffer participates in the arbitration phase, it is sent until it wins the arbitration even if another transmission is requested from a buffer with a higher priority. - RECEPTION. Once the CAN controller has synchronized itself onto the bus activity, it is ready for reception of new messages. Every incoming message gets its identifier compared to the acceptance filters. If the bitwise comparison of the selected bits ends up with a match for at least one of the filters then that message is elected for reception and a target buffer is searched for. This buffer will be the first one - order is 1 to 3 - that has the LOCK and RDY bits of its BCSRx register reset. - When no such buffer exists then an overrun interrupt is generated if the ORIE bit of the ICR register has been set. In this case the identifier of the last message is made available in the Last Identifier Register (LIDHR and LIDLR) at least until it gets overwritten by a new identifier picked-up from the bus. - When a buffer does exist, the accepted message gets written into it, the ACC bit in the BCSRx register gets the number of the matching filter, the RDY and RXIF bits get set and an interrupt is generated if the RXIE bit in the ISR register is set. Up to three messages can be automatically received without intervention from the CPU because each buffer has its own set of status bits, greatly reducing the reactiveness requirements in the processing of the receive interrupts.
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CONTROLLER AREA NETWORK (Cont'd) - ERROR. The error management as described in the CAN protocol is completely handled by hardware using 2 error counters which get incremented or decremented according to the error condition. Both of them may be read by the appliFigure 64. CAN Error State Diagram
When TECR or RECR > 127, the EPSV bit gets set
cation to determine the stability of the network. Moreover, as one of the node status bits (EPSV or BOFF of the CSR register) changes, an interrupt is generated if the SCIE bit is set in the ICR Register. Refer to Figure 64.
ERROR ACTIVE
ERROR PASSIVE
When TECR and RECR < 128, the EPSV bit gets cleared When 128 * 11 recessive bits occur: - the BOFF bit gets cleared - the TECR register gets cleared - the RECR register gets cleared When TECR > 255 the BOFF bit gets set and the EPSV bit gets cleared
BUS OFF
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CONTROLLER AREA NETWORK (Cont'd) 7.8.3.4 Bit Timing Logic The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and resynchronizing on following edges. Its operation may be explained simply when the nominal bit time is divided into three segments as follows: - Synchronisation segment (SYNC_SEG): a bit change is expected to lie within this time segment. It has a fixed length of one time quanta (1 x tCAN). - Bit segment 1 (BS1): defines the location of the sample point. It includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network. - Bit segment 2 (BS2): defines the location of the transmit point. It represents the PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8 time quanta but may also be Figure 65. Bit Timing automatically shortened to compensate for negative phase drifts. - Resynchronization Jump Width (RJW): defines an upper bound to the amount of lengthening or shortening of the bit segments. It is programmable between 1 and 4 time quanta. To guarantee the correct behaviour of the CAN controller, SYNC_SEG + BS1 + BS2 must be greater than or equal to 5 time quanta. For a detailed description of the CAN resynchronization mechanism and other bit timing configuration constraints, please refer to the Bosch CAN standard 2.0. As a safeguard against programming errors, the configuration of the Bit Timing Register (BTR) is only possible while the device is in STANDBY mode.
NOMINAL BIT TIME SYNC_SEG BIT SEGMENT 1 (BS1) BIT SEGMENT 2 (BS2)
1 x tCAN
tBS1
tBS2
SAMPLE POINT
TRANSMIT POINT
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CONTROLLER AREA NETWORK (Cont'd) 7.8.4 Register Description The CAN registers are organized as 6 general purpose registers plus 5 pages of 16 registers spanning the same address space and primarily used for message and filter storage. The page actually selected is defined by the content of the Page Selection Register. Refer to Figure 66. 7.8.4.1 General Purpose Registers INTERRUPT STATUS REGISTER (ISR) Read/Write Reset Value: 00h
7 RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF 0 EPND
- Read/Clear
Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3
Set by hardware to signal that a new error-free message is available in buffer 3. Cleared by software to release buffer 3. Also cleared by resetting bit RDY of BCSR3. Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2 - Read/Clear Set by hardware to signal that a new error-free message is available in buffer 2. Cleared by software to release buffer 2. Also cleared by resetting bit RDY of BCSR2. Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1 - Read/Clear Set by hardware to signal that a new error-free message is available in buffer 1. Cleared by software to release buffer 1. Also cleared by resetting bit RDY of BCSR1.
Bit 4 = TXIF Transmit Interrupt Flag - Read/Clear Set by hardware to signal that the highest priority message queued for transmission has been successfully transmitted (ETX = 0) or that it has passed successfully the arbitration (ETX = 1). Cleared by software. Bit 3 = SCIF Status Change Interrupt Flag - Read/Clear Set by hardware to signal the reception of a dominant bit while in standby or a change from error active to error passive and bus-off while in run. Also signals any receive error when ESCI = 1. Cleared by software. Bit 2 = ORIF Overrun Interrupt Flag - Read/Clear Set by hardware to signal that a message could not be stored because no receive buffer was available. Cleared by software. Bit 1 = TEIF Transmit Error Interrupt Flag - Read/Clear Set by hardware to signal that an error occurred during the transmission of the highest priority message queued for transmission. Cleared by software. Bit 0 = EPND Error Interrupt Pending - Read Only Set by hardware when at least one of the three error interrupt flags SCIF, ORIF or TEIF is set. Reset by hardware when all error interrupt flags have been cleared. Caution; Interrupt flags are reset by writing a "0" to the corresponding bit position. The appropriate way consists in writing an immediate mask or the one's complement of the register content initially read by the interrupt handler. Bit manipulation instruction BRES should never be used due to its read-modifywrite nature.
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CONTROLLER AREA NETWORK (Cont'd) INTERRUPT CONTROL REGISTER (ICR) Read/Write Reset Value: 00h
7 0 ESCI RXIE TXIE SCIE ORIE TEIE 0 ETX
Bit 6 = ESCI Extended Status Change Interrupt - Read/Set/Clear Set by software to specify that SCIF is to be set on receive errors also. Cleared by software to set SCIF only on status changes and wake-up but not on all receive errors. Bit 5 = RXIE Receive Interrupt Enable - Read/Set/Clear Set by software to enable an interrupt request whenever a message has been received free of errors. Cleared by software to disable receive interrupt requests. Bit 4 = TXIE Transmit Interrupt Enable - Read/Set/Clear Set by software to enable an interrupt request whenever a message has been successfully transmitted. Cleared by software to disable transmit interrupt requests.
Bit 3 = SCIE Status Change Interrupt Enable - Read/Set/Clear Set by software to enable an interrupt request whenever the node's status changes in run mode or whenever a dominant pulse is received in standby mode. Cleared by software to disable status change interrupt requests. Bit 2 = ORIE Overrun Interrupt Enable - Read/Set/Clear Set by software to enable an interrupt request whenever a message should be stored and no receive buffer is avalaible. Cleared by software to disable overrun interrupt requests. Bit 1 = TEIE Transmit Error Interrupt Enable - Read/Set/Clear Set by software to enable an interrupt whenever an error has been detected during transmission of a message. Cleared by software to disable transmit error interrupts. Bit 0 = ETX Early Transmit Interrupt - Read/Set/Clear Set by software to request the transmit interrupt to occur as soon as the arbitration phase has been passed successfully. Cleared by software to request the transmit interrupt to occur at the completion of the transfer.
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CONTROLLER AREA NETWORK (Cont'd) CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 00h
7 0 BOFF EPSV SRTE NRTX FSYN WKPS 0 RUN
Bit 6 = BOFF Bus-Off State - Read Only Set by hardware to indicate that the node is in busoff state, i.e. the Transmit Error Counter exceeds 255. Reset by hardware to indicate that the node is involved in bus activities. Bit 5 = EPSV Error Passive State - Read Only Set by hardware to indicate that the node is error passive. Reset by hardware to indicate that the node is either error active (BOFF = 0) or bus-off. Bit 4 = SRTE Simultaneous Receive/Transmit Enable - Read/Set/Clear Set by software to enable simultaneous transmission and reception of a message passing the acceptance filtering. Allows to check the integrity of the communication path. Reset by software to discard all messages transmitted by the node. Allows remote and data frames to share the same identifier.
Set by software to disable the retransmission of unsuccessful messages. Cleared by software to enable retransmission of messages until success is met. Bit 2 = FSYN Fast Synchronization - Read/Set/Clear Set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for only 11 recessive bits in a row. Cleared by software to enable the standard resynchronization when leaving standby mode, i.e. wait for 128 sequences of 11 recessive bits. Bit 1 = WKPS Wake-up Pulse - Read/Set/Clear Set by software to generate a dominant pulse when leaving standby mode. Cleared by software for no dominant wake-up pulse. Bit 0 = RUN CAN Enable - Read/Set/Clear Set by software to leave standby mode after 128 sequences of 11 recessive bits or just 11 recessive bits if FSYN is set. Cleared by software to request a switch to the standby or low-power mode as soon as any on-going transfer is complete. Read-back as 1 in the meantime to enable proper signalling of the standby state. The CPU clock may therefore be safely switched OFF whenever RUN is read as 0.
- Read/Set/Clear
Bit 3 = NRTX No Retransmission
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CONTROLLER AREA NETWORK (Cont'd) BAUD RATE PRESCALER REGISTER (BRPR) Read/Write in Standby mode Reset Value: 00h
7 RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 0 BRP0
BIT TIMING REGISTER (BTR) Read/Write in Standby mode Reset Value: 23h
7 0 BS22 BS21 BS20 BS13 BS12 BS11 0 BS10
RJW[1:0] determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization. tRJW = t CAN * (RJW + 1) BRP[5:0] determine the CAN system clock cycle time or time quanta which is used to build up the individual bit timing. tCAN = tCPU * (BRP + 1) Where tCPU = time period of the CPU clock. The resulting baud rate can be computed by the formula:
BS2[2:0] determine the length of Bit Segment 2. tBS2 = tCAN * (BS2 + 1) BS1[3:0] determine the length of Bit Segment 1. tBS1 = tCAN * (BS1 + 1) Note: Writing to this register is allowed only in Standby mode to prevent any accidental CAN protocol violation through programming errors. PAGE SELECTION REGISTER (PSR) Read/Write Reset Value: 00h
7 0 PAGE PAGE PAGE 2 1 0
1 BR = --------------------------------------------------------------------------------------------t CPU x ( BRP + 1 ) x ( BS1 + BS2 + 3 )
0
0
0
0
0
PAGE[2:0] determine which buffer or filter page is mapped at addresses 0010h to 001Fh. Note: Writing to this register is allowed only in Standby mode to prevent any accidental CAN protocol violation through programming errors.
PAGE2 0 0 0 0 1 1 1 1 PAGE1 0 0 1 1 0 0 1 1 PAGE0 0 1 0 1 0 1 0 1 Page Title Diagnosis Buffer 1 Buffer 2 Buffer 3 Filters Reserved Reserved Reserved
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CONTROLLER AREA NETWORK (Cont'd) 7.8.4.2 Paged Registers LAST IDENTIFIER HIGH REGISTER (LIDHR) Read/Write Reset Value: Undefined
7 LID10 LID9 LID8 LID7 LID6 LID5 LID4 0 LID3
TRANSMIT ERROR COUNTER REG. (TECR) Read Only Reset Value: 00h
7 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 0 TEC0
LID[10:3] are the most significant 8 bits of the last Identifier read on the CAN bus. LAST IDENTIFIER LOW REGISTER (LIDLR) Read/Write Reset Value: Undefined
7 LDLC 3 LDLC 2 LDLC 1 0 LDLC 0
TEC[7:0] is the least significant byte of the 9-bit Transmit Error Counter implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during transmission, this counter is incremented by 8. It is decremented by 1 after every successful transmission. When the counter value exceeds 127, the CAN controller enters the error passive state. When a value of 256 is reached, the CAN controller is disconnected from the bus. RECEIVE ERROR COUNTER REG. (RECR) Page: 00h -- Read Only Reset Value: 00h
7 0 REC6 REC5 REC4 REC3 REC2 REC1 REC0
LID2
LID1
LID0
LRTR
LID[2:0] are the least significant 3 bits of the last Identifier read on the CAN bus. LRTR is the last Remote Transmission Request bit read on the CAN bus. LDLC[3:0] is the last Data Length Code read on the CAN bus.
REC7
REC[7:0] is the Receive Error Counter implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard. After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state. IDENTIFIER HIGH REGISTERS (IDHRx) Read/Write Reset Value: Undefined
7 ID10 ID9 ID8 ID7 ID6 ID5 ID4 0 ID3
ID[10:3] are the most significant 8 bits of the 11-bit message identifier.The identifier acts as the message's name, used for bus access arbitration and acceptance filtering.
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CONTROLLER AREA NETWORK (Cont'd) IDENTIFIER LOW REGISTERS (IDLRx) Read/Write Reset Value: Undefined
7 ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 0 DLC0
BUFFER CONTROL/STATUS REGs. (BCSRx) Read/Write Reset Value: 00h
7 0 0 0 0 ACC RDY 0 BUSY LOCK
ID[2:0] are the least significant 3 bits of the 11-bit message identifier. RTR is the Remote Transmission Request bit. It is set to indicate a remote frame and reset to indicate a data frame. DLC[3:0] is the Data Length Code. It gives the number of bytes in the data field of the message.The valid range is 0 to 8. DATA REGISTERS (DATA0-7x) Read/Write Reset Value: Undefined
7 DATA 7 DATA 6 DATA 5 DATA 4 DATA 3 DATA 2 DATA 1 0 DATA 0
DATA[7:0] is a message data byte. Up to eight such bytes may be part of a message. Writing to byte DATA7 initiates a transmit request and should always be done even when DATA7 is not part of the message.
Set by hardware with the id of the highest priority filter which accepted the message stored in the buffer. ACC = 0: Match for Filter/Mask0. Possible match for Filter/Mask1. ACC = 1: No match for Filter/Mask0 and match for Filter/Mask1. Reset by hardware when either RDY or RXIF gets reset. Bit 2 = RDY Message Ready - Read/Clear Set by hardware to signal that a new error-free message is available (LOCK = 0) or that a transmission request is pending (LOCK = 1). Cleared by software when LOCK = 0 to release the buffer and to clear the corresponding RXIF bit in the Interrupt Status Register. Cleared by hardware when LOCK = 1 to indicate that the transmission request has been serviced or cancelled. Bit 1 = BUSY Busy Buffer - Read Only Set by hardware when the buffer is being filled (LOCK = 0) or emptied (LOCK = 1). Reset by hardware when the buffer is not accessed by the CAN core for transmission nor reception purposes. Bit 0 = LOCK Lock Buffer - Read/Set/Clear Set by software to lock a buffer. No more message can be received into the buffer thus preserving its content and making it available for transmission. Cleared by software to make the buffer available for reception. Cancels any pending transmission request. Cleared by hardware once a message has been successfully transmitted provided the early transmit interrupt mode is on. Left untouched otherwise. Note that in order to prevent any message corruption or loss of context, LOCK cannot be set nor reset while BUSY is set. Trying to do so will result in LOCK not changing state.
- Read Only
Bit 3 = ACC Acceptance Code
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CONTROLLER AREA NETWORK (Cont'd) FILTER HIGH REGISTERS (FHRx) Read/Write Reset Value: Undefined
7 FIL11 FIL10 FIL9 FIL8 FIL7 FIL6 FIL5 0 FlL4
MASK HIGH REGISTERS (MHRx) Read/Write Reset Value: Undefined
7 0
MSK1 MSK1 MSK9 MSK8 MSK7 MSK6 MSK5 MSK4 1 0
FIL[11:3] are the most significant 8 bits of a 12-bit message filter. The acceptance filter is compared bit by bit with the identifier and the RTR bit of the incoming message. If there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer. FILTER LOW REGISTERS (FLRx) Read/Write Reset Value: Undefined
7 FIL3 FIL2 FIL1 FIL0 0 0 0 0 0
MSK[11:3] are the most significant 8 bits of a 12bit message mask. The acceptance mask defines which bits of the acceptance filter should match the identifier and the RTR bit of the incoming message. MSKi = 0: don't care. MSKi = 1: match required. MASK LOW REGISTERS (MLRx) Read/Write Reset Value: Undefined
7 MSK3 MSK2 MSK1 MSK0 0 0 0 0 0
FIL[3:0] are the least significant 4 bits of a 12-bit message filter. MSK[3:0] are the least significant 4 bits of a 12-bit message mask.
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CONTROLLER AREA NETWORK (Cont'd) Figure 66. CAN Register Map
5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h
Interrupt Status Interrupt Control Control/Status Baud Rate Prescaler Bit Timing Page Selection
6Fh
Paged Reg1 Paged Reg1 Paged Reg0 Paged Reg1 Paged Reg2 Paged Reg1 Paged Reg2 Paged Reg1 Paged Reg2 Paged Reg3 Paged Reg2 Paged Reg3 Paged Reg2 Paged Reg3 Paged Reg4 Paged Reg3 Paged Reg4 Paged Reg3 Paged Reg4 Paged Reg5 Paged Reg4 Paged Reg5 Paged Reg4 Paged Reg5 Paged Reg6 Paged Reg5 Paged Reg6 Paged Reg5 Paged Reg6 Paged Reg7 Paged Reg6 Paged Reg7 Paged Reg6 Paged Reg7 Paged Reg8 Paged Reg7 Paged Reg8 Paged Reg7 Paged Reg8 Paged Reg9 Paged Reg8 Paged Reg9 Paged Paged Reg9 Paged Reg10 Reg8 Paged Reg9 Paged Reg10 Paged Paged Reg10 Paged Reg11 Reg9 Paged Reg10 Paged Reg11 Paged Paged Reg11 Paged Reg12 Reg10 Paged Reg11 Paged Reg12 Paged Paged Reg12 Paged Reg13 Reg11 Paged Reg12 Paged Reg13 Paged Paged Reg13 Paged Reg14 Reg12 Paged Reg13 Paged Reg14 Paged Paged Reg14 Paged Reg15 Reg13 Paged Reg14 Paged Reg15 Paged Reg14 Paged Reg15 Paged Reg15 Paged Reg15
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CONTROLLER AREA NETWORK (Cont'd) Figure 67. Page Maps
PAGE 0 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh Reserved LIDHR LIDLR
PAGE 1 IDHR1 IDLR1 DATA01 DATA11 DATA21 DATA31 DATA41 DATA51 DATA61 DATA71
PAGE 2 IDHR2 IDLR2 DATA02 DATA12 DATA22 DATA32 DATA42 DATA52 DATA62 DATA72
PAGE 3 IDHR3 IDLR3 DATA03 DATA13 DATA23 DATA33 DATA43 DATA53 DATA63 DATA73
PAGE 4 FHR0 FLR0 MHR0 MLR0 FHR1 FLR1 MHR1 MLR1
Reserved 6Ch 6Dh 6Eh 6Fh TSTR TECR RECR Diagnosis BCSR1 Buffer 1 BCSR2 Buffer 2 BCSR3 Buffer 3 Acceptance Filters Reserved Reserved Reserved
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CONTROLLER AREA NETWORK (Cont'd) Table 27. CAN Register Map and Reset Values
Address (Hex.) 5A 5B 5C 5D 5E 5F 0 60 1 to 3 60, 64 4 0 61 1 to 3 61, 65 62 to 69 62, 66 63, 67 6E 4 Page Register Label CANISR Reset Value CANICR Reset Value CANCSR Reset Value CANBRPR Reset Value CANBTR Reset Value CANPSR Reset Value CANLIDHR Reset Value CANIDHRx Reset Value CANFHRx Reset Value CANLIDLR Reset Value CANIDLRx Reset Value CANFLRx Reset Value 7 RXIF3 0 0 0 RJW1 0 0 0 LID10 x ID10 x FIL11 x LID2 x ID2 x FIL3 x MSB x MSK11 x MSK3 x MSB 0 MSB 0 0 6 RXIF2 0 ESCI 0 BOFF 0 RJW0 0 BS22 0 0 LID9 x ID9 x FIL10 x LID1 x ID1 x FIL2 x x MSK10 x MSK2 x 0 0 0 5 RXIF1 0 RXIE 0 EPSV 0 BRP5 0 BS21 1 0 LID8 x ID8 x FIL9 x LID0 x ID0 x FIL1 x x MSK9 x MSK1 x 0 0 0 4 TXIF 0 TXIE 0 SRTE 0 BRP4 0 BS20 0 0 LID7 x ID7 x FIL8 x LRTR x RTR x FIL0 x x MSK8 x MSK0 x 0 0 0 3 SCIF 0 SCIE 0 NRTX 0 BRP3 0 BS13 0 0 LID6 x ID6 x FIL7 x LDLC3 x DLC3 x 0 x MSK7 x 0 0 0 ACC 0 2 ORIF 0 ORIE 0 FSYN 0 BRP2 0 BS12 0 PAGE2 0 LID5 x ID5 x FIL6 x LDLC2 x DLC2 x 0 x MSK6 x 0 0 0 RDY 0 1 TEIF 0 TEIE 0 WKPS 0 BRP1 0 BS11 1 PAGE1 0 LID4 x ID4 x FIL5 x LDLC1 x DLC1 x 0 x MSK5 x 0 0 0 BUSY 0 0 EPND 0 ETX 0 RUN 0 BRP0 0 BS10 1 PAGE0 0 LID3 x ID3 x FIL4 x LDLC0 x DLC0 x 0 LSB x MSK4 x 0 LSB 0 LSB 0 LOCK 0
CANDRx 1 to 3 Reset Value 4 4 0 CANMHRx Reset Value CANMLRx Reset Value CANTECR Reset Value CANRECR Reset Value 1 to 3 CANBCSRx Reset Value
6F
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7.9 8-BIT A/D CONVERTER (ADC) 7.9.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 7.9.2 Main Features 8-bit conversion s Up to 8 channels with multiplexed input s Linear successive approximation s Data register (DR) which contains the results s Conversion complete status flag s On/Off bit (to reduce consumption)
s
The block diagram is shown in Figure 68.
Figure 68. ADC Block Diagram
COCO
-
ADON
0
-
CH2
CH1
CH0
(Control Status Register) CSR AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
ANALOG MUX
SAMPLE & HOLD
ANALOG TO DIGITAL CONVERTER
fCPU
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
(Data Register) DR
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8-BIT A/D CONVERTER (ADC) (Cont'd) 7.9.3 Functional Description The high level reference voltage VDDA must be connected externally to the V DD pin. The low level reference voltage V SSA must be connected externally to the VSS pin. In some devices (refer to device pin out description) high and low level reference voltages are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. Figure 69. Recommended Ext. Connections
VDD
0.1F
VDDA VSSA
ST7
RAIN VAIN Px.x/AINx
Characteristics: The conversion is monotonic, meaning the result never decreases if the analog input does not and never increases if the analog input does not. If input voltage is greater than or equal to VDD (voltage reference high) then results = FFh (full scale) without overflow indication. If input voltage VSS (voltage reference low) then the results = 00h. The conversion time is 64 CPU clock cycles including a sampling time of 31.5 CPU clock cycles. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. The A/D converter is linear and the digital result of the conversion is given by the formula: Digital result = 255 x Input Voltage Reference Voltage
The accuracy of the conversion is described in the Electrical Characteristics Section. Procedure: Refer to the CSR and DR register description section for the bit definitions. Each analog input pin must be configured as input, no pull-up, no interrupt. Refer to the "I/O Ports" chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: - Select the CH2 to CH0 bits to assign the analog channel to convert. Refer to Table 28 Channel Selection. - Set the ADON bit. Then the A/D converter is enabled after a stabilization time (typically 30 s). It then performs a continuous conversion of the selected channel. When a conversion is complete - The COCO bit is set by hardware. - No interrupt is generated. - The result is in the DR register. A write to the CSR register aborts the current conversion, resets the COCO bit and starts a new conversion. 7.9.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed. Mode WAIT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
HALT
7.9.5 Interrupts None.
Where Reference Voltage is VDD - VSS.
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8-BIT A/D CONVERTER (ADC) (Cont'd) 7.9.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h)
7 COCO ADON 0 CH2 CH1 0 CH0
These bits are set and cleared by software. They select the analog input to convert. Table 28. Channel Selection Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1
Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete. 1: Conversion can be read from the DR register. Bit 6 = Reserved. Must always be cleared. Bit 5 = ADON A/D converter On This bit is set and cleared by software. 0: A/D converter is switched off. 1: A/D converter is switched on. Note: A typical 30 s delay time is necessary for the ADC to stabilize when the ADON bit is set. Bit 4 = Reserved. Forced by hardware to 0. Bit 3 = Reserved. Must always be cleared. Bits 2:0: CH[2:0] Channel Selection
*IMPORTANT NOTE: The number of pins AND the channel selection vary according to the device. REFER TO THE DEVICE PINOUT).
DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h)
7 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 AD0
Bit 7:0 = AD[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Reading this register resets the COCO flag.
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8-BIT A/D CONVERTER (ADC) (Cont'd) Table 29. ADC Register Map and Reset Values
Address (Hex.) 0070h 0071h Register Label ADCDR Reset Value ADCCSR Reset Value 7 MSB 0 COCO 0 6 5 4 3 2 1 0 LSB 0 CH0 0
0 0
0 ADON 0
0 0
0 0
0 CH2 0
0 CH1 0
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8 INSTRUCTION SET
8.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do Table 30. CPU Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip btjt [$10],#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination
Pointer Address (Hex.)
Pointer Size (Hex.)
Length (Bytes) +0 +1
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word
+1 +2 +0 +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
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INSTRUCTION SET OVERVIEW (Cont'd) 8.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask (level 3) Reset Interrupt Mask (level 0) Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
8.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 8.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 8.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
8.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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INSTRUCTION SET OVERVIEW (Cont'd) 8.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 31. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function
8.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.
Available Relative Direct/Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset is following the opcode. Relative (Indirect) The offset is defined in memory, which address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear
Function
Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine
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INSTRUCTION SET OVERVIEW (Cont'd) 8.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if Port B INT pin = 1 Jump if Port B INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I1:0 = 11 Jump if I1:0 <> 11 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) jrf * (no Port B Interrupts) (Port B interrupt) H=1? H=0? I1:0 = 11 ? I1:0 <> 11 ? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > Pop CC, A, X, PC inc X jp [TBL.w] reg, M tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 1 I1 H 0 I0 N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst Src M M M M I1 H H H I0 N N N N N Z Z Z Z Z C C C
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Substract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Substraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I1:0 = 10 (level 0) C <= A <= C C => A => C S = Max allowed A=A-M-C C=1 I1:0 = 11 (level 3) C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A=A-M A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt 1 1 1 0 N Z reg, M reg, M reg, M reg, M A reg, M M 1 1 N N 0 N N N N Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 1 0 N N Z Z C C A=A+M pop reg pop CC push Y C=0 A reg CC M M M M reg, CC 0 I1 H I0 N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src I1 H I0 N Z C
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9 ELECTRICAL CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that VI and VO be higher than V SS and lower than V DD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD or V SS).
Symbol VDD - VSS VDDA - VSSA VLCD |VDD_i - VDD_j| |VDD_i - VDDA| |VSS_i - VSS_j| |VSS_i - VSSA| |GLCD - VSS_i| VIN VOUT ESD IVDD_i IVSS_i IINJ Input Voltage Output Voltage ESD susceptibility Total current into VDD_i (source) Total current out of VSS_i (sink) Total injected current VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 2000 80 80 +/- 5 mA V V V Max. variations (Ground Line) 50 mV Supply Voltage Analog Reference Voltage VDDA > VSS Max. Display Voltage Max. variations (Power Line) Ratings
Power Considerations. The average chip-junction temperature, TJ, in Celsius can be obtained from: TJ = TA + PD x RthJA Where: TA = Ambient Temperature. RthJA =Package thermal resistance (junction-to ambient). PD = PINT + P PORT. PINT = IDD x VDD (chip internal power). PPORT =Port power dissipation determined by the user)
Value 6.5 6.5 10.5 50 Unit V V V mV
Note: Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. General Warning: Direct connection to VDD or VSS of the RESET and I/O pins could damage the device in case of unwanted internal reset generation or program counter corruption (due to unwanted change of the I/O configuration). To guarantee safe conditions, this connection has to be done through a typical 10K pull-up or pull-down resistor.
Thermal Characteristics
Symbol RthJA TJmax TSTG PD Ratings Package thermal resistance Max. Junction Temperature Storage Temperature Range Power Dissipation PQFP128 EQFP128 Value 42 na 150 -65 to +150 500 Unit C/W C C mW
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9.2 RECOMMENDED OPERATING CONDITIONS
GENERAL Symbol VDD fOSC TA Parameter Supply Voltage Oscillator frequency Ambient Temperature Range 4.5V < VDD < 5.5V Conditions fOSC = 16MHz Min 4.5 8 -40 Typ 5.0 Max 5.5 16 +85 Unit V MHz C
CURRENT INJECTION ON I/O PORT AND CONTROL PINS Symbol IINJ+ IINJParameter Total positive injected current (1) Total negative injected current (2) Conditions VEXTERNAL > VDD VEXTERNAL < VSS Digital pins Analog pins 1.6 0.8 mA Min Typ Max 5 Unit mA
Note 1: Positive injection The Iinj+ is done through protection diodes insulated from the substrate of the die. The pins which have a high voltage capability like true open-drain do not accept positive injection. In this case the maximum voltage rating must be followed. Note 2: ADC accuracy reduced by negative injection The Iinj- is done through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small leakage (few A) induced inside the die when a negative injection is performed. This leakage is tolerated by the digital structure, but it acts on the analog line according to the impedance versus a leakage current of few A (if the MCU has an AD converter). The effect depends on the pin which is submitted to the injection. Of course, external digital signals applied to the component must have a maximum impedance close to 50K. Location of the negative current injection: - The pins with analog input capability are the more sensitive. I inj- maximum is 0.8 mA (assuming that the impedance of the analog voltage is lower than 25K) - The pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible from the analog input pins. General Note: When several inputs are submitted to a current injection, the maximum Iinj is the sum of the positive and negative currents respectively (instantaneous values).
9.3 TIMING CHARACTERISTICS (Operating conditions TA = -40 to +85C unless otherwise specified)
Symbol fOSC tDOG tINST tIRT Parameter External Oscillator Frequency Watchdog Time-out Instruction Time Interrupt Reaction Time tIRT = tINST + 10* Conditions VDD = 4.5V fCPU = 8MHz Min 8 12,288 1.54 2 10 Typ Max 16 786,432 98.3 12 22 Unit MHz tCPU ms tCPU tCPU
* tINST is the number of tCPU to finish the current instruction execution.
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9.4 ELECTRICAL CHARACTERISTICS (TA=-40 to +85oC, VDD-VSS=5V unless otherwise specified) ST72E/T589BW5
Symbol VDD Parameter Operating Supply Voltage Supply Current in RUN mode 1) Supply Current in SLOW mode 1) Supply Current in WAIT mode 2) IDD Supply Current in SLOW WAIT mode 3) Supply Current in ACTIVE-HALT mode 4) Supply Current in HALT mode 4) VRM Data Retention Mode TA<25C 25C(TA=-40 to +85oC, VDD-VSS=5V unless otherwise specified) ROM devices
Symbol VDD Parameter Operating Supply Voltage Supply Current in RUN mode 1) Supply Current in SLOW mode 1) IDD Supply Current in WAIT mode 2) Supply Current in SLOW WAIT mode 3) Supply Current in ACTIVE-HALT mode 4) Supply Current in HALT mode VRM Data Retention Mode
4)
Conditions fOSC=16MHz, fCPU=8MHz fOSC=16MHz fCPU=8MHz fOSC=16MHz fCPU=500KHz fOSC=16MHz fCPU=8MHz fOSC=16MHz fCPU=500KHz
Min 4.5
Typ.
Max 5.5 15
Unit V
1 5 2 0.7 1
3 8 2.5 mA
10
A V
HALT mode
2
Notes: 1) CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS; clock input (OSC1) driven by external square wave. 2) All I/O pins in input mode with a static value at VDD or VSS; clock input (OSC1) driven by external square wave. 3) WAIT Mode with SLOW Mode selected. Based on characterisation results, not tested. 4) All I/O pins in input mode with a static value at VDD or VSS.
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9.5 I/O PORTS CHARACTERISTICS (TA=-40 to +85oC, voltages are referred to VSS unless otherwise specified)
I/O PORT PINS (ST72E/T589BW5) Symbol VIL VIH VHYS VOL Parameter Input Low Level Voltage Input High Level Voltage Schmitt Trigger Voltage Hysteresis I=-5mA Output Low Level Voltage I=-2mA I=5mA VOH IL ISV RPU tohl tolh titext Output High Level Voltage I=2mA Input Leakage Current Static Current Consumption Pull-up Equivalent Resistance Output H-L Fall Time Output L-H Rise Time External Interrupt Pulse Time VSSNote: * Based on characterization results. Not tested. (TA=-40 to +85oC, voltages are referred to VSS unless otherwise specified)
I/O PORT PINS (ROM devices) Symbol VIL VIH VOL Parameter Input Low Level Voltage Input High Level Voltage I=-5mA Output Low Level Voltage I=-2mA I=5mA VOH IL ISV RPU tohl tolh titext Output High Level Voltage Input Leakage Current Static Current Consumption Pull-up Equivalent Resistance Output H-L Fall Time Output L-H Rise Time External Interrupt Pulse Time I=2mA VSS142/158
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9.6 SUPPLY, RESET and CLOCK CHARACTERISTICS The values given in the specifications are generalThe values below substitute the corresponding ly not applicable for all chips. Therefore, only the values in the specifications of dedicated functions. limits listed below are valid for the product. (TA=-40 to +85oC, VDD-VSS=5V unless otherwise specified)
RESET Symbol RON tPULSE Parameter Reset weak pull-up resistance External RESET pin Pulse time Conditions VIN > VIH VIN < VIL Min 20 60 1.5 Typ 40 120 Max 80 240 Unit K tCPU
POWER ON RESET Symbol VTN VPOR Parameter Re-initialization level * Reset generation level ** 2.0 Conditions Min Typ 0.8 2.6 3.4 Max Unit V V
Notes: * VDD has to fall down to VTN to re-arm the POR function ** POR function reset the device through a pulse generation at VPOR. MAIN EXTERNAL CLOCK SOURCE Symbol fOSC VOSC Parameter Main oscillator frequency OSC1 pin voltage Conditions Square signal with 50% Duty Cycle Min Typ Max 16 VDD Unit MHz V
MAIN OSCILLATOR Symbol fOSC CLi tSTART Parameter Main oscillator frequency Load Capacitances Oscillator start-up time RSmax=100 Conditions Min 8 10 Typ Max 16 20 Unit MHz pF
Depends on resonator quality. A typical value is 10ms
Note: RSmax is the equivalent serial resistance of the crystal or ceramic resonator.
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9.7 MEMORY AND PERIPHERAL CHARACTERISTICS (TA=-40 to +85oC, VDD-VSS=5V unless otherwise specified)
EPROM Symbol WERASE UV lamp Parameter Conditions Lamp wavelength 2537A UV lamp is placed 1 inch from the device window without any interposed filters Min Typ 15 Max Unit Wattsec/cm2 20 min
tERASE
Erase Time
15
LCD DRIVER Symbol fFR VDCRC VCOH VCOL VSOH VSOL VLCD RLCDi Parameter Frame frequency DC Residual Component COM high level, Output voltage COM low level, Output voltage SEG high level, Output voltage SEG low level, Output voltage Display voltage Voltage divider resistances Voltage divider coupling capacitances LCD dot load 1% accuracy Conditions fLCD=16384Hz VLCD=VDD no load I=50A, VLCD=5V I=100A, VLCD=10V I=100A, VLCD=5..10V I=25A, VLCD=5V I=25A, VLCD=10V I=25A, VLCD=5..10V 3 10 100 50 4.5 9.5 0.5 10 4.5 9.5 0.5 V Min 64 100 Typ Max 512 Unit Hz mV
K
nF pF
CLCDi
CLOAD
Notes: If VLCD=VLCDnominal and VDD<4.5V then VLCD DC level is applied on SEG and COM outputs.
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MEMORY AND PERIPHERAL CHARACTERISTICS - SCI, CAN
SCI Serial Communication Interface Symbol Parameter Conditions Standard Mode TR (resp.RR)=64, PR=13 TR (resp.RR)=16, PR=13 TR (resp.RR)= 8, PR=13 TR (resp.RR)= 4, PR=13 TR (resp.RR)= 2, PR=13 TR (resp.RR)= 8, PR= 3 TR (resp.RR)= 1, PR=13 Extended Mode ETPR (resp.ERPR) = 13 See "STANDARD I/O PORT PINS" description for more details. Typ ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230,77 ~38461.54 Unit
fTx or fRx
Communication frequency (precision vs. standard ~0.16%)
fCPU=8MHz
Hz
CAN Controller Area Network Symbol fCPU Parameter Frequency of Operation Conditions VDD = 4.5V Min DC Typ Max 8 Unit MHz
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MEMORY AND PERIPHERAL CHARACTERISTICS - SPI
SPI Serial Peripheral Interface Value Ref. Symbol Parameter Master Slave Master Slave Slave Slave Master Slave Master Slave Master Slave Master Slave Condition Min. fSPI 1 2 3 4 5 6 7 8 9 10 11 12 13 tSPI tLead tLag tSPI_H tSPI_L tSU tH tA tDis tV tHold tRise tFall SPI frequency SPI clock period Enable lead time Enable lag time Clock (SCK) high time Clock (SCK) low time Data set-up time Data hold time (inputs) Access time (time to data active from high impedance state) Disable time (hold time to high impedance state) Data valid Data hold time (outputs) 1/128 dc 4 2 120 120 100 90 100 90 100 100 100 100 0 Slave 240 Master (before capture edge) Slave (after enable edge) Master (before capture edge) Slave (after enable edge) 0.25 120 0.25 0 100 100 100 100 ns tCPU ns tCPU ns ns s ns s 120 Max. 1/4 1/2 fCPU tCPU ns ns ns ns ns ns ns Unit
Rise time Outputs: SCK,MOSI,MISO (20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS Fall time Outputs: SCK,MOSI,MISO (70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS
Measurement points are V OL, VOH, VIL and VIH in the SPI Timing Diagram Figure 70. SPI Master Timing Diagram CPHA=0, CPOL=0
SS (INPUT) SCK (OUTPUT) 4 MISO (INPUT) MOSI (OUTPUT) 6 10 D7-IN 7 D7-OUT 11 1
13
12
5 D6-IN D6-OUT D0-IN D0-OUT VR000109
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MEMORY AND PERIPHERAL CHARACTERISTICS- SPI (Cont'd) Measurement points are V OL, VOH, VIL and VIH in the SPI Timing Diagram Figure 71. SPI Master Timing Diagram CPHA=0, CPOL=1
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 13 5 6 10 D7-IN 7 D7-OUT 11 4 D6-IN D6-OUT D0-IN D0-OUT VR000110 12
Figure 72. SPI Master Timing Diagram CPHA=1, CPOL=0
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 13 4 6 10 7 D7-IN 11 D6-IN D0-IN VR000107 5 D7-OUT D6-OUT D0-OUT 12
Figure 73. SPI Master Timing Diagram CPHA=1, CPOL=1
SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 12 5 6 10 4 D7-IN 7 D7-OUT 11 D6-IN D6-OUT D0-IN D0-OUT VR000108 13
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MEMORY AND PERIPHERAL CHARACTERISTICS - SPI (Cont'd) Measurement points are V OL, VOH, VIL and VIH in the SPI Timing Diagram Figure 74. SPI Slave Timing Diagram CPHA=0, CPOL=0
SS (INPUT) SCK (INPUT) MISO HIGH-Z (OUTPUT) 8 MOSI (INPUT) 6 2 1 13 4 D7-OUT 10 D7-IN 7 VR000113 D6-IN 5 D6-OUT 11 D0-IN D0-OUT 9 12 3
Figure 75. SPI Slave Timing Diagram CPHA=0, CPOL=1
SS (INPUT) SCK (INPUT) HIGH-Z MISO (OUTPUT) 8 MOSI (INPUT) 6 2 1 12 5 D7-OUT 10 D7-IN 7 VR000114 D6-IN 4 D6-OUT 11 D0-IN D0-OUT 9
13
3
Figure 76. SPI Slave Timing Diagram CPHA=1, CPOL=0
SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) MOSI (INPUT) 8 D7-IN 6 7 VR000111 4 5 D7-OUT 10 D6-IN D6-OUT 11 D0-IN D0-OUT 9 1 13 12 3
Figure 77. SPI Slave Timing Diagram CPHA=1, CPOL=1
SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) MOSI (INPUT) 8 D7-IN 6 7 VR000112 5 4 D7-OUT 10 D6-IN D6-OUT 11 D0-IN D0-OUT 9 1 12 13 3
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MEMORY AND PERIPHERAL CHARACTERISTICS - I2C (SDAI and SCLI). The ST7 I2C interface meets the Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified. requirements of the Standard I2C communication protocol described in the following table. Refer to I/O port characteristics for more details on the input/output alternate function characteristics
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) Cb SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 Parameter Standard mode I2C Min 1) 4.7 4.0 250 0 3) 1000 300 Max 1) Fast mode I2C Min 1) 1.3 0.6 100 0 2) 20+0.1Cb 20+0.1Cb 0.6 0.6 0.6 1.3 400 900 3) 300 300 s ns ms pF ns Max 1) Unit s
tw(STO:STA) STOP to START condition time (bus free)
Figure 78. Typical Application with I2C Bus and Timing Diagram 4)
VDD 4.7k I2C BUS 4.7k VDD 100 100 SDAI SCLI
ST72XXX
REPEATED START START
tsu(STA)
SDA
tw(STO:STA)
START
tf(SDA)
SCK
tr(SDA)
tsu(SDA)
th(SDA)
STOP
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
Notes: 1. Data based on standard I2C protocol requirement, not tested in production. 2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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MEMORY AND PERIPHERAL CHARACTERISTICS - ADC WARNING ON ADC: The ST72E/T589BW5 EPROM devices have their ADC which differs from the ROM devices in term of accuracy (less precision), timing (slower stabilization and conversion time) and external components. Care must be taken at software and hardware application levels when transferring a code from the EPROM device to the ROM device.
Digital Result ADCDR 255 254 253 1LSB i deal V -V DDA SSA = ---------------------------------------256 (2) 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSB (ideal) Vin (LSBideal) 5 6 7 253 254 255 256 VDDA OE ILE DLE TUE (3) (1) GE (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
TUE=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. OE=Offset Error: deviation between the first actual transition and the first ideal one. GE=Gain Error: deviation between the last ideal transition and the last actual one. DLE=Differential Linearity Error: maximum deviation between actual steps and the ideal one. ILE=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
ADC Analog to Digital Converter (8-bit) for ST72E/T589BW5 devices Symbol |TUE| OE GE |DLE| |ILE| VAIN IADC tSTAB tLOAD tCONV RAIN RADC Parameter Total unadjusted error* Offset error* Gain Error* Differential linearity error* Integral linearity error* Conversion range voltage A/D conversion supply current Stabilization time after enable ADC Sample capacitor loading time Hold conversion timeval External input resistor Internal input resistor fADC=fCPU=4MHz VDD=VDDA=5V 8 32 8 32 20 18 22 VSSA 1 30 fADC=fCPU=4MHz VDD=VDDA=5V -1 -2 Conditions Min Typ Max 2 1 2 1 2 VDDA V mA s s 1/fADC s 1/fADC pF LSB Unit
CSAMPLE Sample capacitor
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MEMORY AND PERIPHERAL CHARACTERISTICS - ADC (Cont'd)
ADC Analog to Digital Converter (8-bit) for ROM devices Symbol fADC |TUE| OE GE |DLE| |ILE| VAIN IADC tSTAB tLOAD tCONV RAIN RADC Parameter Analog control frequency Total unadjusted error* Offset error* Gain Error* Differential linearity error* Integral linearity error* Conversion range voltage A/D conversion supply current Stabilization time after enable ADC Sample capacitor loading time Hold conversion time External input resistor Internal input resistor 1.5 6 fCPU=8MHz, fADC=4MHz VDD=VDDA=5V 1 4 2 8 15 VSSA 1 1 fCPU=8MHz, fADC=4MHz VDD=VDDA=5V -1 -0.6 Conditions fADC = fCPU/2 Min Typ Max 4 1.5 1 0.6 1 1.2 VDDA V mA s s 1/fADC s 1/fADC pF LSB Unit MHz
CSAMPLE Sample capacitor
*Note: ADC Accuracy vs. Negative Injection Current: For Iinj-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB by 10K increase of the external analog source impedance. These measurements results and recommendations are done in the worst condition of injection: - negative injection - injection to an Input with analog capability,adjacent to the enabled Analog Input - at 5V VDD supply, and worse temperature case.
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10 PACKAGE CHARACTERISTICS
10.1 PACKAGE MECHANICAL DATA Figure 79. 128-Pin Plastic Quad Flat Package
Dim.
D D1 D2 A A2 A1
mm Min 0.25 2.57 0.13 0.13 23.20 20.00 18.50 17.20 14.00 12.50 0.50 0 0.73 1.60 128 7 0 Typ 0.33 Max Min 3.04 3.40
inches Typ Max 0.120 0.134 0.010 0.013 0.28 0.005 0.23 0.005 0.913 0.787 0.728 0.677 0.551 0.492 0.020 7 0.063 0.011 0.009
A A1 A2 B C D
2.71 2.87 0.101 0.107 0.113
b
e
D1 D3 E E1 E3 e K
L
E2 E1 E
1.60 mm
c 0x- 7x
L L1 N
0.88 1.03 0.029 0.035 0.041 Number of Pins
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PACKAGE MECHANICAL DATA (Cont'd) Figure 80. 128-Pin Economic Quad Flat Package
Dim A A1 B D E e G EQFP128 G1 G2 L L1 On OP N mm Min Typ Max 2.40 Min inches Typ Max 0.094
0.03 0.001 0.17 0.22 0.27 0.007 0.009 0.011 23.00 23.20 23.40 0.906 0.913 0.921 17.00 17.20 17.40 0.669 0.677 0.685 0.50 13.60 19.60 1.80 1.40 1.60 0.35 1.10 Number of Pins 128 (ND=38 / NE=26) 0.055 0.063 0.014 0.043 0.020 0.535 0.772 0.071
D1 18.57 18.72 18.97 0.731 0.737 0.747 E1 12.57 12.72 12.97 0.495 0.501 0.511
REFLOW SOLDERING ONLY
Note: "QUALIFICATION OR VOLUME PRODUCTION OF DEVICES USING EPOXY PACKAGES (ESO/EDIL/EQFP) IS NOT AUTHORIZED It is expressly specified that qualification and/or volume production of devices using the package E.... in any applications is not authorized. Usage in any application is strictly restricted to development purpose. Similar devices are available in plastic package mechanically compatible to the epoxy package for qualification and volume production." Figure 81. Recommended Reflow Oven Profile (MID JEDEC) 250 200 Temp. [C] 150 100 50 0 100 200 300 400
ramp up 2C/sec for 50sec 150 sec above 183C 90 sec at 125C Tmax=220+/-5C for 25 sec
ramp down natural 2C/sec max
Time [sec]
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11 DEVICE CONFIGURATION AND ORDERING INFORMATION
11.1 ORDERING
INFORMATION AND TRANSFER OF CUSTOMER CODE
The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. See page 155. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
Customer code is made up of the FASTROM or ROM contents and the list of the selected options (if any). The FASTROM or ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19 format generated by the development tool. All unused bytes must be set to FFh. Table 32. Ordering Information
Sales Type 1) ST72389BW4/xxx ST72P589BW5/xxx ST72T589BW5 Program Memory (bytes) 16K ROM 24K FASTROM 24K OTP
RAM (bytes) 512 1024
Package
PQFP128
Note 1. /xxx stands for the ROM or FASTROM code name assigned by STMicroelectronics.
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MICROCONTROLLER OPTION LIST
Customer: Address:
..................................................................... ..................................................................... ..................................................................... Contact: ..................................................................... Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference/ROM or FASTROM code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *The ROM or FASTROM code name is assigned by STMicroelectronics. ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. STMicroelectronics references: Device: [ ] ST72P589B (24 KB) [ ] ST72389B (16 KB) Temperature Range: [ ] 0 C to +70 C [ ] -40 C to +85 C Package: Marking: [ ] PQFP128: [ ] Tape & Reel [ ] Tray
[ ] Standard marking: [ ] Special marking (ROM only): PQFP128 (14 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, `.', `-', `/' and spaces only. Please consult your local STMicroelectronics sales office for other marking details if required. Comments: Notes: Date: Signature: ..................................................................... ..................................................................... .....................................................................
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11.2 ST7 APPLICATION NOTES
IDENTIFICATION DESCRIPTION EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 IC COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR IC SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF IC BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PERMANENT MAGNET DC MOTOR DRIVE. AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS AN1130 WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264 PRODUCT OPTIMIZATION
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DESCRIPTION USING ST7 WITH CERAMIC RESONATOR HOW TO MINIMIZE THE ST7 POWER CONSUMPTION SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES ST7 CHECKSUM SELF-CHECKING CAPABILITY CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS EMULATED DATA EEPROM WITH XFLASH MEMORY EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILAN1530 LATOR PROGRAMMING AND TOOLS AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROAN1179 GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IDENTIFICATION AN 982 AN1014 AN1015 AN1040 AN1070 AN1324 AN1477 AN1502 AN1529
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12 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Rev. Main changes Date
Changed output configuration for PD4 and PD5 in Table 1, "Device Pin Description," on page 6 2.7 Removed references to 32-kHz auxiliary oscillator Added notes: "I2C, PWM-BRM and CAN available on ST72589 version only" Added VHYS in section 9.5 on page 142
June 03
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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