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SPT7868
10-BIT, 80 MSPS A/D CONVERTER PRELIMINARY INFORMATION
FEATURES
* 80 MSPS maximum sample rate * 9.2 effective number of bits at IN = 15 MHz and S = 80 MSPS * 2 VP-P full-scale input range * Differential input 2.5 V common mode * Internal or external voltage reference * Common-mode voltage reference output * +3.3 V / +5 V digital output logic compatibility * +5 V analog power supply
APPLICATIONS
* High-speed applications where low power dissipation is required * Video imaging * Medical imaging * Radar receivers * IR imaging * Digital communications
GENERAL DESCRIPTION
The SPT7868 is a 10-bit, 80 MSPS analog-to-digital converter with low power dissipation at only 627 mW typical at 80 MSPS with a power supply of +5.0 V. The digital outputs are +3 V or +5 V, and are user selectable. The SPT7868 has incorporated proprietary circuit design and CMOS
processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The SPT7868 is available in a 28-lead SSOP package over the industrial temperature range.
BLOCK DIAGRAM
VDD GND Sleep VCM
Bandgap Reference
EXT/INT REFH REFL VIN VIN
Bias Cell
THA
10-BIT 80 MSPS ADC 2
CLK, CLK
10
Data Output Latches & Buffers
1 10
OR D0D9
GND
OVDD
Signal Processing Technologies, Inc.
Phone: 719-528-2300 4755 Forge Road, Colorado Springs, Colorado 80907, USA Fax: 719-528-2370 Web Site: http://www.spt.com e-mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages VDD ....................................................................... TBD OVDD ..................................................................... TBD Input Voltages Analog Input .......................................................... TBD CLK Input .............................................................. TBD Output Digital Outputs ....................................................... TBD Temperature Operating Temperature ........................... -40 to +85 C Storage Temperature ............................ -65 to +150 C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, S=80 MSPS, VRHS=3.0 V, VRLS=2.0 V, unless otherwise specified.
PARAMETERS Resolution DC Accuracy Differential Linearity Error (DLE) Integral Linearity Error (ILE) No Missing Codes Analog Input Input Voltage Range (Differential) Input Common Mode Input Capacitance Common Mode Rejection Ratio (CMRR) Timing Characteristics Conversion Rate Pipeline Delay (Latency) Output Delay (tD) Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits (ENOB) IN = 15 MHz, CLK = 80 MSPS Signal-to-Noise Ratio (SNR) IN = 15 MHz, CLK = 80 MSPS Total Harmonic Distortion (THD) IN = 15 MHz, CLK = 80 MSPS Signal-to-Noise and Distortion (SINAD) IN = 15 MHz, CLK = 80 MSPS Spurious Free Dynamic Range (SFDR) IN = 15 MHz, CLK = 80 MSPS
TEST CONDITIONS
TEST LEVEL
MIN 10
SPT7868 TYP
MAX
UNITS Bits
@ +25 C full temperature @ +25 C full temperature
V V VI V V V
0.5 0.75 0.8 1.0 Guaranteed 1 2.5 2 TBD 80 TBD 7 TBD TBD TBD TBD
LSB LSB LSB LSB
V V pF
VI IV IV V V
MSPS clocks ns ns ps (rms)
25 C -40 C to +85 C 25 C -40 C to +85 C 25 C -40 C to +85 C 25 C -40 C to +85 C 25 C -40 C to +85 C
I IV I IV I IV I IV I IV
9.0 8.8 57 TBD
9.2 9.0 57 TBD -69 TBD -66 TBD
Bits Bits dB dB dB dB dB dB dB dB
56 TBD 69 TBD
57 TBD 72 TBD
SPT
SPT7868 2
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ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, S=80 MSPS, VRHS=3.0 V, VRLS=2.0 V, unless otherwise specified.
PARAMETERS Power Supply Requirements VDD Voltage (Analog Supply) OVDD Voltage (Output Supply) VDD Current OVDD Current Power Dissipation External Voltage Reference Internal Voltage Reference Sleep Mode Power Dissipation External Voltage Reference Internal Voltage Reference Power Supply Rejection Ratio (PSRR)
TEST CONDITIONS
TEST LEVEL IV IV VI VI VI VI VI VI V VI V V VI VI VI IV IV VI VI VI VI VI VI VI VI
MIN 4.75 2.7
SPT7868 TYP 5.0 3.3/5.0 125 14 619 627 TBD TBD TBD
MAX 5.25 5.25 131 16 643 651 TBD TBD
UNITS V V mA mA mW mW mW mW mV/V V ppm/C k A V V V V V V V V A A V V
Internal References Common Mode Voltage Reference (VCM) IO = -1 A Common Mode Voltage Tempco Output Impedance Current Capability (EXT/INT) = 0 Reference Low Output Voltage (VREFL) Reference High Output Voltage (VREFH) (EXT/INT) = 0 External References Reference Low Input Voltage Range Reference High Input Voltage Range Digital Outputs Output Voltage High Output Voltage Low Digital Inputs Input High Voltage Input Low Voltage Input High Current Input Low Current Clock Inputs Clock Inputs High Voltage Clock Inputs Low Voltage (EXT/INT) = 1 (EXT/INT) = 1 IO = -2 mA IO = 2 mA
TBD
1.95 2.95 1.7 2.7 85% OVDD
2.5 100 TBD TBD 2.0 3.0 2.0 3.0 90% OVDD 0.2
TBD
2.05 3.05 2.3 3.3 OVDD 0.4
80% VDD 20% VDD 10 10 2 5 0.4
TEST LEVEL CODES
TEST LEVEL
I II III IV V VI
TEST PROCEDURE
100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
SPT
SPT7868 3
8/15/00
Figure 1 - Driving Differential Inputs with a Differential Configuration
Figure 2 - Driving Differential Inputs with a SingleEnded Configuration
VIHD VICM VILD
VID
VIH VICM VIL
PACKAGE OUTLINE
28-Lead SSOP
INCHES
28
MILLIMETERS MIN 10.07 0.05 0.25 0.09 1.68 0.63 7.65 5.20 MAX 10.33 0.21 0.65 typ 0.38 0.20 1.78 0.95 7.90 5.38
SYMBOL A
IH
MIN 0.397 0.002 0.010 0.004 0.066 0.025 0.301 0.205
MAX 0.407 0.008 0.0256 typ 0.015 0.008 0.070 0.037 0.311 0.212
B C D
1
E F G
A F
H I
B C H D
G E
SPT
SPT7868 4
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PIN ASSIGNMENTS
PIN FUNCTIONS
Name Function GND Analog ground VDD Analog +5 V OGND Output ground OVDD Supply voltage for digital outputs +5 V or +3.3 V REFL Reference pin low, input for external reference, bypass with capacitor (100 nF) when internal reference is selected. REFH Reference pin high, input for external reference, bypass with capacitor (100 nF) when internal voltage is selected. VCM 2.5 V common mode voltage reference output VIN Non-inverted analog input VIN Inverted analog input CLK Clock input pin CLK Complement of clock input pin, internally biased to 1.5 V; if single-ended clock is used, bypass to GND with 100 nF D0-D9 Digital outputs; D0 = LSB; 3.3 V/5 V compatible OR Overrange bit; 3.3 V/5 V compatible EXT/INT EXT/INT = 1, external reference used; internal reference powered down EXT/INT = 0, internal reference used; internally pulled down Sleep Sleep = 1, normal operation; internally pulled up Sleep = 0, powered-down mode
GND VDD REFL REFH EXT/INT VCM GND VDD VIN
1 2 3 4 5 6 7 8 9
28 27 26 25 24 23
D0 D1 D2 D3 D4 OGND OVDD OGND OVDD D5 D6 D7 D8 D9 (MSB)
SPT7868 28L SSOP
22 21 20 19 18 17 16 15
VIN 10 Sleep 11 CLK 12 CLK 13 OR 14
ORDERING INFORMATION
PART NUMBER SPT7868SIR TEMPERATURE RANGE -40 to +85 C PACKAGE TYPE 28L SSOP
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT
SPT7868 5
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