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SP6138
TM
Synchronous Buck Controller
UV IN BST
13 12 GH 11 10 9
VCC
Now Available in Lead Free Packaging DESCRIPTION The SP638 is a synchronous step-down switching regulator controller optimized for small footprint. The part is designed to be especially attractive for single supply step down conversion from 5V to 24V. The SP638 is designed to drive a pair of external NFETs using a fixed 2.5 MHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown, output short circuit protection, and overcurrent protection with auto restart. The device also features a PWRGD output and an enable input. The SP638 is available in a space saving 6-pin QFN and offers excellent thermal performance. TYPICAL APPLICATION CIRCUIT
VIN
C5 0.1uF DBST CVCC 4.7uF SD101AWS VIN VCC R3 10K POWERGOOD NC ENABLE PWRGD UVIN EN GND BST GH SWN RS1 1K GL RS3 4.99K ISP CSP ISN COMP CP1 6 pF VFB SS CSS 47nF CZ3 47pF CF1 18pF CZ2 100pF RZ2 54.9K RZ3 1K 6.8nF CS 0.1uF R1 68.1K, 1% RS2 1K C2 22uF CBST 0.1uF MT/MB, Si7214DN 47 m, 30V (Co-Packaged FETs) C1 4.7uF
12V
GND
COOPER, SD25-2R2 2.2uH, 2.8A, 31m
VOUT
SP6138
3.3V 0-2A
PGND
GND
R2 21.5K, 1%
Note: Die-attach paddle is connected to GND
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PWRGD
FEATURES 5V to 24V Input step down converter Up to 3A output in a small form factor GL Highly integrated design, minimal components PGND UVLO Detects Both VCC and VIN Overcurrent circuit protection with auto-restart GND Power Good Output, ENABLE Input Maximum Controllable Duty Cycle Ratio up to 92% VFB Wide BW amp allows Type II or III compensation Programmable Soft Start Fast Transient Response Available in 6-Pin QFN package External Driver Enable/Disable U.S. Patent #6,922,04
16 1 2 3 4
15
14
SP6138
16 Pin QFN 3mm x 3mm
VIN
SW N ISP ISN
5
6
7
8
COMP
EN
SS
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VCC .................................................................................................. 6V VIN .............................................................................................. 24.5V BST................................................................................................ 30V BST-SWN ........................................................................................ 7V SWN ....................................................................................-2V to 24V GH ..........................................................................-0.3V to BST+0.3V GH-SWN.......................................................................................... 6V All other pins ............................................................-0.3V to VCC+0.3V Peak Output Current < 10s GH,GL ............................................................................................. 2A Storage Temperature ................................................... -65C to 150C Power Dissipation ........................................................................... W ESD Rating ........................................................................... 2kV HBM Thermal Resistance.............................................................. 41.9C/W
Unless otherwise specified: -40C < TAMB < 85C, 4.5V < VCC < 5.5V, BST=VCC, SWN = GND = PGND = 0.0V, UVIN = 3.0V, CVCC = 0F, CCOMP = 0.F, CGH = CGL = 3.3nF, CSS = 50nF, RPWRGD = 0K.
ELECTRICAL SPECIFICATIONS
PARAMETER
QUIESCENT CURRENT
VIN Supply Current VCC Supply Current BST Supply Current
MIN
TYP
.5 .5 0.2
MAX UNITS CONDITIONS
3.0 3.0 0.4 4.5 250 2.65 400 0.0 mA mA mA V mV V mV V mV A 0.808 0.82 230 -70 00 3.2 3.8 V V A A nA V V VFB = 0.7V Apply voltage to UVIN pin Apply voltage to UVIN pin UVIN Floating UVIN Floating Apply voltage to EN pin 2X Gain Config. VFB = V (no switching) VFB = V (no switching) VFB = V (no switching)
PROTECTION: UVLO
VCC UVLO Start Threshold VCC UVLO Hysteresis UVIN Start Threshold UVIN Hysteresis VIN Start Threshold VIN Hysteresis Enable Pullup Current 4.00 50 2.35 200 9.0 4.25 200 2.50 300 9.5 300 0.4 0.792 0.788 70 -230 .9 3.2 0.800 0.800 50 -50 50 3.0 3.5
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference Error Amplifier Reference Over Line and Temperature COMP Sink Current COMP Source Current VFB Input Bias Current COMP Common Mode Output Range COMP Pin Clamp Voltage
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Unless otherwise specified: -40C < TAMB < +85C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = PGND = 0.0V, UVIN = 3.0V, CVCC = 0.F, CCOMP = 0.F, CGH = CGL = 3.3nF, CSS = 50nF.
ELECTRICAL SPECIFICATIONS
PARAMETER
Ramp Offset Ramp Amplitude GH Minimum Pulse Width Maximum Controllable Duty Ratio Maximum Duty Ratio Internal Oscillator Frequency
MIN
.7 0.80 92 00 2.2 -6 .0
TYP
2.0 .0 30
MAX UNITS CONDITIONS
2.3 .20 70 V V ns % % Guaranteed by design TA = 25C
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
2.5 -0 2.0
2.8 -4 3.0
MHZ A mA Fault Present VIN = 6 to 23V, ILOAD = 0mA to 30mA IVCC = 30mA
TIMERS: SOFTSTART
SS Charge Current SS Discharge Current
VCC LINEAR REGULATOR
VCC Output Voltage Dropout Voltage 4.6 250 -0 5.0 500 -7.5 2.0 .0 5.4 750 -5 4.0 0 V mV % % mA VFB = 0.7V, VPWRGD = 0.2V Measured VREF (0.8V) - VFB Measured ISP - ISN
POWER GOOD OUTPUT
Power Good Threshold Power Good Hysteresis Power Good Sink Current
PROTECTION: SHORT CIRCUIT & THERMAL
Short Circuit Threshold Voltage Overcurrent Threshold Voltage ISP, ISN Common Mode Range Hiccup Timeout Thermal Shutdown Temperature Thermal Hysteresis 0.2 54 0 20 35 30 45 0 0.25 60 0.3 66 3.3 40 55 3.3 V mV V ms C C
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Unless otherwise specified: -40C < TAMB < +85C, 4.5V < VCC < 5.5V, BST=VCC,SWN = PGND = GND = 0.0V, UVIN = 3.0V, CVCC = 0.F, CCOMP = 0.F, CGH = CGL = 3.3nF, CSS = 50nF.
ELECTRICAL SPECIFICATIONS
PARAMETER
GH & GL Rise Times GH & GL Fall Times GL to GH Non Overlap Time SWN to GL Non Overlap Time GH & GL Pull Down Resistance Driver Pull Down Resistance Driver Pull Up Resistance
MIN
TYP MAX UNITS
35 30 45 25 50 40 70 40 85 .9 3.9 ns ns ns ns K
CONDITIONS
Measured 0% to 90% Measured 90% to 0% GH & GL Measured at 2.0V Measured SWN = 00mV to GL = 2.0V
OUTPUT: NFET GATE DRIVERS
5
50 .5 2.5
BLOCk DIAGRAM
VCC NON SYNC. STARTUP COMPARATOR GL HOLD OFF 13 BST
5
COMP SS
VFBINT 4 VCC VCC 10 uA SOFTSTART INPUT SS 8 0.1V Gm ERROR AMPLIFIER Gm FAULT
1.6 V
VFB
PW M LOOP
RESET DOMINANT R Q FAULT S QPWM
12 GH
VPOS POS REF
SYNCHRONOUS DRIVER
11 SWN 1 GL
FAULT RAMP = 1V
2.5 MHZ 2 CLK CLOCK PULSE GENERATOR 2.8 V 1.3 V VCC REF OK 1 uA EN 6 1.7V ON 1.0V OFF POWER FAULT 4.25 V ON 4.05 V OFF VCC UVLO THERMAL SHUTDOWN 145C ON 135C OFF SET DOMINANT S Q 0.25V VPOS SHORT CIRCUIT DETECTION R HICCUP FAULT 3 GND ENABLE COMPARATOR PGND
VCC
16
REFERENCE CORE
0.8V
FAULT
5V LINEAR REGULATOR
VIN
14
VFBINT 140K 100ms Delay OVER CURRENT DETECTION COUNTER CLR 2.50 V ON 2.20 V OFF 50K VIN UVLO 10 ISP 9 ISN 60 mV REF OK VFB 0.74 V ON 0.72 V OFF Power Good 7 PWRGD CLK
UVIN
15
UVLO CO MPARATORS
THERMAL AND OVER CURRENT PRO TECTION
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PIN DESCRIPTION PIN PIN # NAME 2 3 4 GL PGND GND VFB DESCRIPTION
High current driver output for the low side NFET switch. It is always low if GH is high or during a fault. Resistor pull down ensures low state at low voltage. Ground Pin. The power circuitry is referenced to this pin. Return separately from other ground traces to the (-) terminal of Cout. Ground pin. The control circuitry of the IC is referenced to this pin. Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error Amplifier and serves as the output voltage feedback point for the Buck Converter. The output voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters hiccup mode. Output of the Error Amplifier. It is internally connected to the non-inverting input of the PWM comparator. An optimal filter combination is chosen and connected to this pin and either ground or VFB to stabilize the voltage mode loop. Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is internally pulled to VCC with a A current source. Power Good Output. This open drain output is pulled low when VOUT is outside of the regulation. Connect an external resistor to pull high. Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft start rate based on the 0A source current. The SS pin is held low via a mA (min) current during all fault conditions. Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE and NSENSE. Offset accuracy +0%. Positive Input for the Inductor Current Sense. Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFET transistors. High current driver output for the high side NFET switch. It is always low if GL is high or during a fault. High side driver supply pin. Connect BST to the external boost diode and capacitor as shown in the Application Schematic of page . High side driver is connected between BST pin and SWN pin. Supply Input. Provides power to the internal LDO. Under Voltage lock-out for VIN voltage. Internally has a resistor divider from VIN to ground. Can be overridden with external resistors. Output of the Internal LDO. If VIN is less than 5V then Vcc should be powered from an external 5V supply.
5 6 7 8 9 0 2 3 4 5 6
COMP EN PWRGD SS ISN ISP SWN GH BST VIN UVIN VCC
Note: Die-attach paddle is internally connected to GND
General Overview
THEORY OF OPERATION
The SP6138 is a fixed frequency, voltage mode, synchronous PWM controller optimized for high efficiency. The part has been designed to be especially attractive for single supply input voltages ranging between 5V and 24V. The heart of the SP638 is a wide bandwidth transconductance amplifier designed to accommodate Type II and Type III compensaOct 24-06 Rev J
tion schemes. A precision 0.8V reference present on the positive terminal of the error amplifier permits the programming of the output voltage down to 0.8V via the VFB pin. The output of the error amplifier, COMP, compared to a V peak-to-peak ramp is responsible for trailing edge PWM control. This voltage ramp and PWM control logic are governed by the internal oscillator that accurately sets the PWM frequency to 2.5 MHz.
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SP638 Synchronous Buck Controller
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THEORY OF OPERATION The SP6138 contains two unique control features that are very powerful in distributed applications. First, non-synchronous driver control is enabled during start up to prohibit the low side NFET from pulling down the output until the high side NFET has attempted to turn on. Second, a 00% duty cycle timeout ensures that the low side NFET is periodically enhanced during extended periods at 00% duty cycle. This guarantees the synchronized refreshing of the BST capacitor during very large duty ratios. The SP638 also contains a number of valuable protection features. A programmable input UVLO allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internal VCC UVLO ensures that the controller itself has enough voltage to properly operate. Other protection features include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or UVLO fault is detected, the SP638 is forced into an idle state where the output drivers are held off for a finite period before a re-start is attempted.
Soft Start
the excess current source can be redefined as: IVIN, X = COUT * VOUT *
Hiccup
0A (CSS * 0.8V)
Upon the detection of a power, thermal, or short-circuit fault, the SP638 is forced into an idle state for a minimum of 30ms. The SS and COMP pins are immediately pulled low, and the gate drivers are held off for the duration of the timeout period. Power and thermal faults have to be removed before a restart may be attempted, whereas, a short-circuit fault is internally cleared shortly after the fault latch is set. Therefore, a restart attempt is guaranteed every 30ms (typical) as long as the short-circuit condition persists. A short-circuit detection comparator has also been included in the SP638 to protect against the accidental short or severe build up of current at the output of the power converter. This comparator constantly monitors the inputs to theerror amplifier, and if the VFB pin ever falls more than 250mV (typical) below the reference voltage, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP638 is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation.
Error Amplifier & Voltage Loop
"Soft Start" is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source current. In a modern step down converter, ramping up the non-inverting input of the error amplifier controls soft start. As a result, excess source current can be defined as the current required to charge the output capacitor IVIN, X = Cout * Vout TSoft-start
The SP638 provides the user with the option to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 0A pull up current present at the SS pin and the 0.8V reference voltage. Therefore,
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As stated before, the heart of the SP638 voltage error loop is a high performance, wide bandwidth transconductance amplifier. Because of the amplifier's current limited (+00A) transconductance, there are many ways to compensate the voltage loop or to control the COMP pin externally. If a simple, single pole, single zero response is required, then compensation can be as simple as an RC circuit to ground. If a more complex compensation is required, then the amplifier has enough bandwidthto run Type III compensation schemes with adequate gain and phase margins at crossover frequencies greater than 200 kHz.
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SP638 Synchronous Buck Controller
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THEORY OF OPERATION The common mode output of the error amplifier (COMP) is 0.9V to 2.2V. Therefore, the PWM voltage ramp has been set between .0V and 2.0V to ensure proper 0% to 00% duty cycle capability. The voltage loop also includes two other very important features. One is an non-synchronous start up mode. Basically, the GL driver cannot turn on unless the GH driver has attempted to turn on or the SS pin has exceeded .7V. This feature prevents the controller from "dragging down" the output voltage during startup or in fault modes. The second feature is a 00% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that the GH driver is on for 20 continuous clock cycles, a reset is given to the PWM flip flop half way through the 20th cycle. This forces GL to rise for the remainder of the cycle, in turn refreshing the BST capacitor.
Gate Drivers Over-Current Protection
Over-current is detected by monitoring a differential voltage across the output inductor as shown in figure 1. Inputs to an overcurrent detection comparator, set to trigger at 60 mV nominal, are connected to the inductor as shown. Since the average voltage sensed by the comparator is equal to the product of inductor current and inductor DC resistance (DCR) then Imax = 60mV / DCR. Solving this equation for the specific inductor in circuit , Imax = 4.6A. When Imax is reached, a 220 ms time-out is initiated, during which top and bottom drivers are turned off. Following the time-out, a restart is attempted. If the fault condition persists, then the timeout is repeated (referred to as hiccup).
SP613X
SWN L = 2.7uH, DCR = 4.mOhm
Vout
The SP638 contains a pair of powerful 2.5 pull-up and .5 pull-down drivers. These state-of-the-art drivers are designed to drive an external NFET capable of handling up to 30A. Rise, fall, and non-overlap times have all been minimized to achieve maximum efficiency. All drive pins GH, GL, & SWN are monitored continuously to ensure that only one external NFET is ever on at any given time.
Thermal & Short-Circuit Protection
RS 5.K
RS2 5.K
ISP ISN CSP 6.8nF CS 0.uF
Figure 1: Over-current detection circuit
Because the SP638 is designed to drive large NFETs running at high current, there is a chance that either the controller or power converter will become too hot. Therefore, an internal thermal shutdown (145C) has been included to prevent the IC from malfunctioning at extreme temperatures.
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APPLICATION INFORMATION
Increasing the Current Limit
If it is desired to set Imax > {60mV / DCR} (in this case larger than 4.6A), then a resistor RS3 should be added as shown in figure 2. RS3 forms a resistor divider and reduces the voltage seen by the comparator. Since: 60mV = RS3
Combining the above equations and solving for RS3: RS3 = RS2 * [Vout - 60mV + (IMAX*DCR)].........(2b) 60mV - (IMAX * DCR) As an example: for Imax of 2A and Vout of 3.3V, calculated RS3 is .5M (232K standard).
SP613X
L = 2.7uH, DCR = 4.mOhm
{RS + RS2 + RS3}
.........(2a)
( Imax * DCR )
Solving for RS3 we get: RS3 =
[(Imax * DCR) - 60mV]
[60mV * (RS + RS2)]
SWN
Vout
RS 5.K
RS2 5.K
As an example: if desired Imax is 7A, then RS3 = 63.4K.
SP613X
SWN L = 2.7uH, DCR = 4.mOhm
ISP ISN CSP 6.8nF CS 0.uF RS3 .5MOhm
Vout
RS 5.K RS3 63.4K CSP 6.8nF CS 0.uF
RS2 5.K
Figure 3- Over-current detection circuit for Imax < {60mV / DCR}
Power MOSFET Selection
ISP ISN
Figure 2- Over-current detection circuit for Imax > 60mV / DCR
Decreasing the Current Limit
There are four main criterion in selecting Power MOSFETs for buck conversion: Voltage rating BVdss On resistance Rds(on) Gate-to-drain charge Qgd Package type

If it is required to set Imax < {60mV / DCR}, a resistor is added as shown in figure 3. RS3 increases the net voltage detected by the current-sense comparator. Voltage at the positive and negative terminal of comparator is given by: VSP = Vout + (Imax * DCR) VSN = Vout x {RS3 / (RS2 +RS3)} Since the comparator is triggered at 60mV: VSP-VSN = 60 mV
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In order to better illustrate the MOSFET selection process, the following buck converter design example will be used: Vin = 2V, Vout = 3.3V, Iout = 0A, f = 2000KHz, DCR = 4.5m (inductor DC resistance), efficiency = 94% and Ta = 40C. Select the voltage rating based on maximum input voltage of the converter. A commonly used practice is to specify BVdss at least twice the maximum converter input voltage. This is done to safeguard against switching transients that may break down the MOSFET. For converters with Vin of less than 0V, a
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APPLICATION INFORMATION 20V rated MOSFET is sufficient. For converters with 0-5Vin, as in the above example, select a 30V MOSFET. The calculation of Rds(on) for Top and Bottom MOSFETs is interrelated and can be done using the following procedure: ) Calculate the maximum permissible power dissipation P(dissipation) based on required efficiency. The converter in the above example should deliver an output power Pout = 3.3Vx0A = 33W. For a target efficiency of 94%, input power Pin is given by Pin = Pout/0.94 = 35.W. Maximum allowable power dissipation is then: P(dissipation) = Pin - Pout = 2. W 2) Calculate the total power dissipation in top and bottom MOSFETs P(mosFEt) by subtracting inductor losses from P(dissipation) calculated in step . To simplify, disregard core losses; then PL = I2rms x DCR x .4, where .4 accounts for the increase in DCR at operating temperature. For the above example PL = 0.63W. Then: P(MOSFET) = 2.W - 0.63W = .47W. 3) Calculate Rds(on) of the bottom MOSFET by allocating 40% of calculated losses to it. 40% dissipation allocation reflects the fact that the the top MOSFET has essentially no switching loss. Then P(bottom) = 0.4x.47W = 0.59W. Rds(on) = P/(I2rms x .5) where Irms = Iout x {-(Vout/Vin)}0.5 and .5 accounts for the increase in Rds(on) at the operating temperature. Then: Rds(on) = = 5.4 m. 4) Allocate 60% of the calculated losses to the top MOSFET, P(top) = 0.6x.47 = 0.88W. Assume conduction losses equal to switching losses, then P = 0.5x0.88W = 0.44W. Since it operates at the duty cycle of D=Vin/Vout; then:
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Rds(on) = = 0.7 m.
P
[I2out * (Vout/Vin) * .5]
Gate-to-drain charge Qgd for the top MOSFET needs to be specified. A simplified expression for switching losses is: Ps = Iout * Vin * f *
{ Vin + Iout }
dv/dt di/dt
...................(3)
where dv/dt and di/dt are the rates at which voltage and current transition across the top MOSFET respectively, and f is the switching frequency. Voltage switching time (Vin /dv/dt) is related to Qgd:
(Vin /dv/dt) = Qgd/Ig............................... (4)
where Ig is Current charging the gate-to-drain capacitance. It can be calculated from: Ig = (VdrivE-VgatE)/RdrivE......................(5) where VdrivE is the drive voltage of the SP638 top driver minus the drop across the boost diode (approximately 4.5V); VgatE is the top MOSFET's gate voltage corresponding to Iout (assume 2.5V) and RdrivE is the internal resistance of the SP638 top driver (assume 2 average for turn-on and turn-off). Substituting these values in equation (5) we get Ig = A. Substituting for Ig in equation (4), we get (Vin /dv/dt) = Qgd. Substituting for (Vin /dv/dt) in equation (3) we have: Ps = Iout * Vin * f * {Qgd + (Iout / di/dt)} Solving for Qgd we get: Qgd =
[{I out * (-Vout/Vin)} * .5]
2
P
{ Iout * Ps * f Vin
_ Iout .............. (6)
di/dt
}
Di/dt is usually limited by parasitic DC-Loop Inductance (Lp) according to di/dt = Vin/Lp.
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APPLICATION INFORMATION Lp is due to wiring and PCB traces connecting input capacitors and switching MOSFETs. For typical Lp of 2nH and Vin of 2V, di/dt is 1A/ns. Substituting for di/dt in equation (6) we get Qgd = 2 nC. In selecting a package type, the main considerations are cost, power/current handling capability and space constraints. A larger package in general offers higher power and current handling at increased cost. Package selection can be narrowed down by calculating the required junction-to-ambient thermal resistance ja: ja = {Tj(max) - Ta(max)} / P(max)........... (7) Where: Tj(max) is the die maximum temperature rating, Ta(max) is maximum ambient temperature, and P(max) is maximum power dissipated in the die. It is common practice to add a guard-band of 25C to the junction temperature rating. Following this convention, a 150C rated MOSFET will be designed to operate at 125C (i.e., Tj(max) = 125C). P(max) = 0.88W (from section 4) and Ta(max) = 40C as specified in the design example. Substituting in equation (7) we get ja = 96.6 C/W. For the top MOSFET, we now have determined the following requirements; BVdss = 30V, Rds(on) = 0.7m, Qgd = 2 nC and ja < 96.6C/W. An SO-8 MOSFET that meets the requirements is Vishay-Siliconix's Si4394DY; BVdss = 30V, Rds(on) = 9.75m @ Vgs = 4.5V, Qgd = 2.nC and ja = 90 C/W. The bottom MOSFET has the requirements of BVdss = 30V and Rds(on) = 5.4m. VishaySiliconix's Si4320DY meets the requirements; BVdss = 30V, Rds(on) = 4m @ Vgs = 4.5V.
Power Good
Power Good (PWRGD) is an open drain output that is pulled low when Vout is outside regulation. The PWRGD pin can be connected to VCC with an external 0K resistor. During startup, output regulates when Soft Start (SS) reaches 0.8V (the reference voltage). PWRGD is enabled when SS reaches .6V. PWRGD output can be used as a "Power on Reset". The simplest way to adjust delay of the "Power on Reset" signal with respect to Vout in regulation is with the Soft Start Capacitor (Css) and is given by: Css = (Iss x Tdelay)/0.8 where Iss is the Soft Start charge current (0A nominal).
Under Voltage Lock Out (UVLO)
The SP638 has two separate UVLO comparators to monitor the bias (Vcc) and Input (Vin) voltages independently. The Vcc UVLO is internally set to 4.25V. The Vin UVLO is programmable through UVin pin. When UVIN pin is greater than 2.5V the SP638 is permitted to start up pending the removal of all other faults. A pair of internal resistors is connected to UVIN as shown in figure 4. Therefore without external biasing the Vin start threshold is 9.5V. A small capacitor may be required between UVIN and GND to filter out noise. For applications with Vin of 5V or 3.3V, connect UVIN directly to Vin.
SP613X
VIN
R4 UVIN
40K
R5 GND
2.5V ON 2.2V OFF 50K
+
Figure 4- Internal and external bias of UVIN
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APPLICATION INFORMATION To program the Vin start threshold, use a pair of external resistors as shown. If external resistors are an order of magnitude smaller than internal resistors, then the Vin start threshold is given by: Vin(start) = 2.5 * (R4+R5)/R5................ (8) For example, if it is required to have a Vin start threshold of 7V, then let R5 = 5K and using equation (9) we get R4 = 9.09K.
Inductor Selection
The peak to peak inductor ripple current is: Ipp = Vout * (Vin(max) - Vout) Vin(max) * Fs * L
Once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency requirements. The core must be large enough not to saturate at the peak inductor current IpEak = Iout(max) + Ipp/2 and provide low core loss at the high switching frequency. Low cost powdered iron cores have a gradual saturation characteristic but can introduce considerable AC core loss, especially when the inductor value is relatively low and the ripple current is high. Ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. Nevertheless, they are preferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. In general, ferrite or molypermalloy materials are the better choice for all but the most cost sensitive applications. The power dissipated in the inductor is equal to the sum of the core and copper losses. To minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. Core losses have a more significant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. Core loss information is usually available from the magnetic vendor. The copper loss in the inductor can be calculated using the following equation: PL(cu) = I2L(rms) * Rwinding
There are many factors to consider in selecting the inductor including cost, efficiency, size and EMI. In a typical SP638 circuit, the inductor is chosen primarily for value, saturation current and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and need more output capacitance to smooth out the larger ripple current. The inductor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. A good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. The switching frequency and the inductor operating point determine the inductor value as follows: L= Vout * (Vin(max) - Vout) Vin(max) * Fs * Kr * Iout(max)
where: Fs = switching frequency Kr = ratio of the ac inductor ripple current to the maximum output current
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APPLICATION INFORMATION where IL(rms) is the RMS inductor current that can be calculated as follows:
.
iL(rms) = Iout(max) *
The total output ripple is a combination of the ESR and the output capacitance value and can be calculated as follows: Vout =.
.
.
+ * 3
{
Ipp Iout(max)
}
2
Output Capacitor Selection
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. During an output load transient, the output capacitor must supply all the additional current demanded by the load until the SP638 adjusts the inductor current to the new value. Therefore, the capacitance must be large enough so that the output voltage is held up while the inductor current ramps up or down to the value corresponding to the new load current. Additionally, the ESR in the output capacitor causes a step in the output voltage equal to the current. Because of the fast transient response and inherent 00% and 0% duty cycle capability provided by the SP638 when exposed to output load transients, the output capacitor is typically chosen for ESR, not for capacitance value. The output capacitor's ESR, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. The maximum allowable ESR required to maintain a specified output voltage ripple can be calculated by: RESR < Vout ipk-pk where: Vout = Peak to Peak Output Voltage Ripple ipk-pk = Peak to Peak Inductor Ripple Current
Oct 24-06 Rev J
(Ipp*REsr)2 +
{
Ipp * (1-d) Cout * Fs
}
2
where: Fs = Switching Frequency D = Duty Cycle Cout = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple current rating, capacitance and voltage rating. The input capacitor must meet the ripple current requirement imposed by the switching current. In continuous conduction mode, the source current of the high-side MOSFET is approximately a square wave of duty cycle Vout/VIN. Most of this current is supplied by the input bypass capacitors. The RMS value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: Icin(rms) = Iout(max) *
D * (-D)
.
Schottky Diode Selection
When paralleled with the bottom MOSFET, an optional Schottky diode can improve efficiency and reduce noise. Without this Schottky diode, the body diode of the bottom MOSFET conducts the current during the non-overlap time when both MOSFETs are turned off. Unfortunately, the body diode has high forward voltage and reverse recovery problems. The reverse recovery of the body diode causes additional switching noise when the diode turns off. The Schottky diode alleviates these sources of noise and additionally improves efficiency thanks to its
(c) 2006 Sipex Corporation
SP638 Synchronous Buck Controller
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APPLICATION INFORMATION low forward voltage. The reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. The power dissipation of the Schottky diode is determined by: PDIODE = 2 * VF * Iout * TNOL * FS where: TNOL = non-overlap time between GH and GL. VF = forward voltage of the Schottky diode.
Loop Compensation Design
The first step of compensation design is to pick the loop crossover frequency. High crossover frequency is desirable for fast transient response, but often jeopardizes the system stability. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The ESR zero is contributed by the ESR associated with the output capacitors and can be determined by: z(Esr) = 2 * Cout * REsr The next step is to calculate the complex conjugate poles contributed by the LC output filter, p(Lc) = 2 * L * COUT
The open loop gain of the whole system can be divided into the gain of the error amplifier, PWM modulator, buck converter output stage, and feedback resistor divider. In order to cross over at the selected frequency FCO, the gain of the error amplifier must compensate for the attenuation caused by the rest of the loop at this frequency. The goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of -20db/dec.
.
.
When the output capacitors are of a Ceramic Type, the SP6138 Evaluation Board requires a Type III compensation circuit to give a phase boost of 180 in order to counteract the effects of an under damped resonance of the output filter at the double pole frequency.
Type III Voltage Loop Compensation GAMP (s) Gain Block VREF (Volts)
PWM Stage GPWM Gain Block VIN VRAMP_PP
Output Stage GOUT (s) Gain Block (SRESRCOUT+ 1) [S^2LCOUT+S(RESR+RDC) COUT+1]
+ _
(SRz2Cz2+1)(SR1Cz3+1) SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
VOUT (Volts)
Notes: RESR = Output Capacitor Equivalent Series Resistance. RDC = Output Inductor DC Resistance. VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage. Condition: Cz2 >> Cp1 & R1 >> Rz3 Output Load Resistance >> RESR & RDC Voltage Feedback GFBK Gain Block R2 VFBK (Volts) (R1 + R2) or VREF VOUT
Figure 5: SP6138 Voltage Mode Control Loop with Loop Dynamic Definitions: REsr = Output Capacitor Equivalent Series Resistance Rdc = Output Inductor DC Resistance Vramp _ pp = SP638 internal RAMP Amplitude Peak to Peak Voltage
Oct 24-06 Rev J SP638 Synchronous Buck Controller (c) 2006 Sipex Corporation
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APPLICATION INFORMATION
Gain (dB)
Error Amplifier Gain Bandwidth Product Condition: C22 >> CP1, R1 >> RZ3
20 Log (RZ2/R1)
1/6.28 (RZ3) (CZ3)
1/6.28 (RZ2) (CP1)
1/6.28(R22) (CZ2)
1/6.28 (R1) (CZ3)
1/6.28 (R1) (CZ2)
Frequency (Hz)
Figure 6: Bode Plot of Type III Error Amplifier Compensation Note: Loop Compensation component calculations discussed in this Datasheet can be quickly iterated with the Type III Loop Compensation Calculator on the web at: www.sipex.com/files/Application-Notes/TypeIIICalculator.xls
INDUCTORS - SURFACE MOUNT Manufacturer/Part No.
Cooper DR73-2R2
Inductance (uH) 2.2
Series R mOhms 16.50
Isat (A)
Inductor Specification Size LxW(mm) Ht.(mm)
Inductor Type
Shielded Ferrite Core
Manufacturer Website www.cooperet.com Manufacturer
5.5 7.6x6.0 3.6 CAPACITORS - SURFACE MOUNT Capacitor Specification Ripple Current Size
(A) @ 5oC rise LxW(mm) Ht.(mm) 1.70 2.01X1.25 1.25
Manufacturer/Part No.
AVX 08053D475MAT AVX 08056D226MAT
Capacitance (uF) 4.7 22
ESR Mohms (max) 5 5
Voltage (V) 25.0 6.3
Capacitor Type X5R Ceramic X5R Ceramic
Website
www.avx.com www.avx.com
2.60
2.01X1.25
1.25
MOSFETS - SURFACE MOUNT Manufacturer/Part No.
Vishay Si7214DN
MOSFET N-Channel
RDS(on) m (max) 47
MOSFET Specification ID Current Qg Voltage (A) nC (Typ) nC (Max) (V) 5.9 4.2 6.5 30
Foot Print PowerPAK 1212-8
Manufacturer Website www.vishay.com
Note: Components highlighted in bold are those used on the SP6138 Evaluation Board.
Table 1. Input and Output Stage Components Selection Charts
Oct 24-06 Rev J SP638 Synchronous Buck Controller (c) 2006 Sipex Corporation
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APPLICATION INFORMATION
90 85 80 75 70 0.5
SP6138 Efficiency versus load current @ Vin=12V, Vout=3.3V
1.0
1.5
2.0
2.5
3.0
Load current (A)
SP6138 Load Regulation @ Vin=12V 3.345
3.340
3.335
3.330 0.5 1.0 1.5 2.0 2.5 3.0 Load current (A)
Oct 24-06 Rev J
SP638 Synchronous Buck Controller
(c) 2006 Sipex Corporation
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PACkAGE: 16 PIN QFN
Oct 24-06 Rev J
SP638 Synchronous Buck Controller
(c) 2006 Sipex Corporation
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ORDERING INFORMATION
Part Number Temperature Range Package
SP638ER ........................................... ....-40C to +85C .......................................... 6 Pin QFN SP638ER/TR ..................................... ....-40C to +85C ...........................................6 Pin QFN
Available in lead free packaging. To order add "-L" suffix to part number. Example: SP6138ER1/TR = standard; SP6138ER1-L/TR = lead free /TR = Tape and Reel Pack quantity is 2500 for QFN.
Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Oct 24-06 Rev J SP638 Synchronous Buck Controller (c) 2006 Sipex Corporation
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