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| TIME SLOT ASSIGNMENT CIRCUIT S5T8555 INTRODUCTION The S5T8555 is a per channel Time Slot Assignment Circuit (TSAC) that produces 8-bit receive and transmit time slots for four 1 CHIP CODEC. Each frame synchronization pulse may be independently assigned to a time slot in a frame of up to 64 time slots 20-CERDIP FEATURES * * * * * * * * Single, 5V operation Low power consumption: 5mW Controls four 1 CHIP CODEC Independent transmit and receive frame syncs channel unidirectional mode Up to 64 time slots per frame Compatible with S5T8554B/7B CODECs TTL and CMOS compatible ORDERING INFORMATION Device S5T8555X01-L0B0 Package 20-CERDIP Operating Temperature -20C to 125C 1 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT PIN CONFIGURATION FSX1 FSR1 FSX0 FSR0 TSX DC CLKC CS MODE 1 2 3 4 5 6 7 8 9 20 VCC 19 FSR2 18 FSX2 17 FSR3 16 FSX3 15 CH0 14 CH1 13 RSYC /CH2 12 XSYC 11 BCLK KT8555 S5T8555 GND 10 2 TIME SLOT ASSIGNMENT CIRCUIT S5T8555 PIN DISCRIPTION Pin No 3 1 18 16 4 2 19 17 5 6 7 8 9 10 11 12 13 Symbol FSX0 FSX1 FSX2 FSX3 FSR0 FSR1 FSR2 FSR3 TSX DC CLKC CS MODE GND BCLK XSYC Description A Transmit frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made. A Receive frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made. This pin pulls low during any active transmit time slot. (N-channel open drain) The input for an 8 bit serial control word. X is the first bit clocked in. The clock input for the control interface. The active-low chip select for the control interface. Mode 1 = Open or VCC Mode 2 = Gnd Ground The bit clock input (2.048 MHz) The transmit Time Slot Output sync pulse input. Must be synchronous with BCLK. RSYC /CH2 The receive time slot sync pulse input. Must be synchronous with BCLK. In mode 1 this input is the receive time slot 0 sync pulse, RSY C, which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word. CH1 CH0 VCC The input for the NSB (next significant bit) of the channel select word. The input for the LSB (last significant bit) of the channel select word, which defines the frame sync output affected by the following control word. Power supply pin. 5V 5% 14 15 20 3 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT ABSOLUTE MAXIMUM RATING (Ta = 25C) Characteristic Positive Supply Voltage Input Voltage Output Voltage Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 secs) Symbol VCC VI VO TOPR TSTG TLEAD Value 70. VCC + 0.3 ~ -0.3 VCC + 0.3 ~ -0.3 - 25 ~ 125 - 65 ~ 150 300 Unit V V V C C C 4 TIME SLOT ASSIGNMENT CIRCUIT S5T8555 ELECTRICAL CHARACTERISTICS (Unless otherwise noted; VCC = 5.0V 5%, Ta = 0C to 70C) Characteristic Operating Current Input Voltage High Input Voltage Low Input Current 1 Input Current 2 Output Voltage High Output Voltage Low Symbol ICC VIH VIL II1 II2 VOH Test Conditions BCLK = 2.048MHz, all output open - - All Inputs Except Mode, VILVINVIH Mode, VIN = 0V FSX and FSR Outputs, IOH = 3mA FSX and FSR Outputs, IOH = 3mA TSX output, IOL=3mA Rise and Fall Time of Clock Delay to TS X Low Delay to TS X High Hold Time BCLK to Frame Sync Set-Up Time from Frame Sync BCLK Delay Time from BLCK Low to FSX/R0-3 High or Low Hold Time from Channel Select to CLK Set-Up Time from Channel Select to CLK Period of Clock Width of Clock High Width of Clock Low Set-Up Time from DC to CLK Hold Time from CLK to DC Set-Up Time from CS to CLK Hold Time from CLK to CS tR (CK) tF (CK) tD (TSXL) tD (TSXH) tH (BFS) tH (FSB) tD tH (CSC) tSU (CSC) tCK tW (CKH) tW (CKL) tSU (DCC) tH (CDC) tSU (CC) tH (CC) BCLK, CLKC BCLK, CLK BCLK, CLK - - - - CL = 50pF - - BCLK, CLKC CL=50pF RL=1k - - Min. - 2.0 - -1 -100 2.4 - - - - 30 50 30 - Typ. 1 - - - - - - - - - - - - - - - - - - - - - - Max. 1.5 - 0.7 1 - - 0.4 0.4 50 140 100 - - 50 - - - - - - - - - Unit mA V V A A V V V nS nS nS nS nS nS 50 30 240 50 50 30 50 30 100 nS nS nS nS nS nS nS nS nS 5 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT TIMING DIAGRAM tHCD tW(CKH) tW(CKL) CONTROL INTERFACE tH(CC) CLKC t R(CK) tF(CK) tSU(CC) tH(CC) CS t SU(CC) CH0, CH1 AND CH2 tSU(DcC) DC 1 2 tWCH tSU(FSB) BCLK t H(BFS) t RS XSYC OR RSYC tD FSX OR FSR tD(TSxH) MIN tD(TSxH) MAX TSX t FS tF(CK) 1 tDT(SxL) 2 t W(CKL) t R(CK) tD 3 4 5 6 7 8 3 4 OUTPUT 5 6 7 tH(CSC) 8 tSU(CSC) Figure 1. APPLICATION INFORMATION OPERATING CONTROL MODE 1 The S5T8555 is a control interface which requires an 8 bit serial control word. Either one of the frame sync output group, FSX0 to FXX3 or FSR0 to FSR3, affected by the control word is defined by the two bits, X and R. Time slot selected from 0 to 63 is specified. A frame sync output is highly active for one time slot which is equivalent to 8 cycles of BCLK. Up to 64 time slots are allowed to form a frame. There are two operational mode. In mode 1, each channel of transmit and receive direction has different time slot assigned. This mode can be selected by either leaving pin 9 (MODE) opened or connecting it with VCC. In such a case, pin 13 is RSYC input defining the start of each receive frame while four out-put, FSR0 to FSR3, are assigned with respect to RSYC. On the other hand, start of each transmit frame is defined by XSYC input by which output FS X0 to FSX3, are assigned. XSYC and RSYC can be phase related. Channels from 0-3 are selected by the input CH0 and CH1 (refer to the table 1). X R T5 T4 T3 T2 T1 T0 CH1 0 0 1 1 CH0 0 1 0 1 Channel Selected Assign to FSX0 and/or FSR0 Assign to FSX1 and/or FSR1 Assign to FSX2 and/or FSR2 Assign to FSX3 and/or FSR3 X is the first bit clocked into DC input 6 TIME SLOT ASSIGNMENT CIRCUIT S5T8555 Control Data Format Table 1. OPERATING CONTROL MODE 1 T5 0 0 0 T4 0 0 0 T3 0 0 0 T2 0 0 0 T1 0 0 1 T1 0 1 0 Time Slot 0 1 2 . . . 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 30 31 32 33 . . . 1 1 1 1 1 1 63 X 0 0 1 1 R 0 1 0 1 Action Assign time slot to both selected FSX and FSR Assign time slot to selected FSX only Assign time slot to selected FSR only Assign time slot to selected FSX and FSR OPERATING CONTROL MODE 2 In mode 2, all 8 frame sync outputs can be assigned with respect to XSYC input. The mode 2, selected by connecting pin 9 (MODE) to GND, enables the S5T8555 TSAC suitable for an 8-channel unidirectional controller and for a system where both transmit and receive direction of each channel have same time slot assigned. For instance, FSX and FSR input of 1 CHIP CODEC are hard wired together. The channel assigned has its channel selected by CH0, CH1 and CH2 (refer to table 2). CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 Channel Selected Assign to FSX0 Assign to FSX1 Assign to FSX2 Assign to FSX3 Assign to FSR0 Assign to FSR1 Assign to FSR2 Assign to FSR3 X 0 0 1 1 R 0 1 0 1 Action Assign time slot to selected output Assign time slot to selected output Assign time slot to selected output Disable both selected output 7 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT APPLICATION CIRCUIT The S5T8555 TSAC combined with any kind of 1 CHIP CODEC from S5T8554B/7B series can obtain data timing as illustrated in Fig. 3. Even though FSX output goes high before BCLK gets high, the DX output of the 1 CHIP CODEC remains in the TRI-STATE mode until both outputs are high. The eight bit period is shortened to avoid PCM data clash at PCM pre-highway. Alternatively, full 8 bits can be obtained by inverting the BCLK to the 1 CHIP CODEC devices, thereby rising edges of BCLK and FSX/R are aligned. Fig. 4 is typical timing of the control data interface. Fig. 5 is the typical application circuit at operating control mode 2. BCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 XSYC FSX1 FSX2 DX 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 TS X Figure 2. Transmit Data Timing CLKC CH0, CH1 CS DC X R T5 T4 T3 T2 T1 T0 X R T5 T4 Figure 3. Control Data Timing 8 S5T8555 13 TS X VFXI+ 16 10 BCLK X 9 MCLK X S5T8554B/7B 7 CLKSEL VFXI- 15 KT8554/57 GSX DX VFRO PDN 14 11 3 8 +5V 6 0.1F 12 FSR 20 VCC GND MODE FS X0 FS X1 1 18 3 10 9 5 FS X DR CH0 CH1 14 CH1 15 CH0 1 CHIP CODEC # 0 1 CHIP CODEC #1 1 CHIP CODEC #2 1 CHIP CODEC #3 CS KT8555 8 CS 7 CLKC 11 BCLK 12 XSYC 6 DC S5T8555 CH2 FS X2 FS X3 16 FSR0 FSR1 4 2 FSR2 19 FSR3 17 13 CH2 CLKC BCLK XSYC DC 1 CHIP CODEC #4 1 CHIP CODEC #5 1 CHIP CODEC #6 NOTE 1 : Dc Format MSB X NOTE 2 : X, R action status X 0 0 1 1 1 1 0 R 0 Action Timesolt assign Time slot assign Time slot assign Time slot assign disable R T5 T3 T2 T4 LSB T1 T0 12 FS X VFRO 3 S5T8554B/7B 6 DR DX 11 KT8554/57 9 MCLK X 10 BCLK X 7 CLKSEL 13 TS X GSX 14 VF XI- 15 TIME SLOT ASSIGNMENT CIRCUIT VF XI+ 16 1 CHIP CODEC #7 NOTE 4 : Time slot assign status Time Slot T4 T3 T2 T1 T0 APPLICATION CIRCUIT NOTE 3 : T5 action status T5 0 1 Action Normal operation Time slot assign disable 0 1 2 . . . . 62 63 0 0 0 . . . . 1 1 0 0 0 . . . . 1 1 0 0 0 . . . . 1 1 0 0 1 . . . . 1 1 0 1 0 . . . . 0 1 NOTES: Different time slot assign for RX and TX respectively 5 FS R PDN 8 Figure 4. Digital Interface on a Typical Subscriber Linecard 9 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT NOTES 10 |
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