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INTEGRATED CIRCUITS
MIPS PR31500 Poseidon embedded processor
Preliminary specification Version 0.1 1996 Sep 24
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
Version 0.1
GENERAL DESCRIPTION
PR31500 Processor is a single-chip, low-cost, integrated embedded processor consisting of MIPS R3000 core and system support logic to interface with various types of devices. PR31500 consists of a MIPS R3000 RISC CPU with 4 KBytes of instruction cache memory and 1 KByte of data cache memory, plus integrated functions for interfacing to numerous system components and external I/O modules. The R3000 RISC CPU is also augmented with a multiply/accumulate module to allow integrated DSP functions, such as a software modem for high-performance standard data and fax protocols. The PR31500 processor can support both Little and Big Endian operating systems. In addition the PR31500 provides a memory management unit with an on-chip Translation Look aside Buffer (TLB) for very fast virtual to physical address translation. PR31500 also contains multiple DMA channels and a high-performance and flexible Bus Interface Unit (BIU) for providing an efficient means for transferring data between external system memory, cache memory, the CPU core, and external I/O modules. The types of external memory devices supported include dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), Flash memory, read-only memory (ROM), and expansion cards (e.g., PCMCIA). PR31500 also contains a System Interface Module (SIM) containing integrated functions for interfacing to numerous external I/O modules such as liquid crystal displays (LCDs), the UCB1100 (which handles most of the analog functions of the system, including sound and telecom codecs and touchscreen ADC), ISDN/high-speed serial, infrared, wireless peripherals, etc. Lastly, PR31500 contains support for implementation of power management, whereby various PR31500 internal modules and external subsystems can be individually (under software control) powered up and down. Figure 1 shows an External Block Diagram of PR31500.
MIPS PR31500
FEATURES
* 32-bit R3000 RISC static CMOS CPU * 4 KByte instruction cache * 1 KByte data cache * Multiply/accumulator Instruction * R3000A memory management unit with on-chip TLB * Supports Big/Little Endian operating systems * On-chip peripherals with individual power-down
- Multi-channel DMA controller - Bus interface unit - Memory controller for ROM, Flash, RAM, DRAM, SDRAM, SRAM, and PCMCIA - Power management module - Video module - Real-time clock 32.760KHz reference - High-speed serial interface - Infrared module - Dual-UART - SPI bus
* 3.3V supply voltage * 208-pin LQFP (Low profile quad flat pack) * 40MHz operation frequency
ORDERING INFORMATION
PART NUMBER PR31500ABC TEMPERATURE RANGE (C) AND PACKAGE 0 to +70, 208-pin Low Profile Quad Flat Pack FREQUENCY (MHz) 40 DRAWING NUMBER LQFP208
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Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
ICache DATA 4KByte ADDR TAG Bus Interface Unit (BIU) Module
Data
Data to Memory Addr
(S)DRAM/PCMCIA/ROM
R3000 RISC CPU Core MMU
Addr MAC
Control
CPU Module
DCache 1KByte
to UCB1100
to LCD
to general purpose I/O
32 KHz
SYSCLK
1996 Sep 24
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
System Interface Unit (SIU) Module Arbitration/DMA/AddrDecode Data Addr SIB Module CHI Module Video Module IR Module UART Module (dual UART) IO Module SPI Module Timer Module (+ RTC) Power Module Clock Module Interrupt Module System Interface Module (SIM) Figure 1. PR31500 Block Diagram 3
to high speed serial
to IR
to UART
to Power Supply
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Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
* high-speed multiplier/accumulator
- on-chip hardware multiplier - supports 16x16 or 32x32 multiplier operations, with 64-bit accumulator - existing multiply instructions are enhanced and new multiply and add instructions are added to R3000 instruction set to improve the performance of DSP applications
OVERVIEW
Each of the on-chip peripherals consist of:
BIU Module
* System memory and PR31500 Bus Interface Unit (BIU)
- supports up to 2 banks of physical memory - supports self-refreshing DRAM and SDRAM - programmable parameters for each bank of DRAM or SDRAM (row/column address configuration, refresh, burst modes, etc.)
* CPU interface
- handles data bus, address bus, and control interface between CPU core and rest of PR31500 logic
* programmable chip select memory access
- 4 programmable (size, wait states, burst mode control) memory device and general purpose chip selects available for system ROM, SRAM, Flash available for external port expansion registers
Clock Module
* PR31500 supports system-wide single crystal configuration,
besides the 32 KHz RTC XTAL (reduces cost, power, and board space)
* supports up to 2 identical full PCMCIA ports
- PR31500 and UCB1100 provide the control signals and accepts the status signals which conform to the PCMCIA version 2.01 standard - appropriate connector keying and level-shifting buffers required for 3.3V versus 5V PCMCIA interface implementations
* common crystal rate divided to generate clock for CPU, video,
sound, telecom, UARTs, etc.
* external system crystal rate is vendor-dependent * independent enabling or disabling of individual clocks under
software control, for power management
SIU Module
(SIU)
* multi-channel 32-bit DMA controller and System Interface Unit * independent DMA channels for video, SIB to/from UCB1100
audio/telecom codecs, high-speed serial port, IR UART, and general purpose UART
CHI Module
* high-speed serial Concentration Highway Interface (CHI) contains
logic for interfacing to external full-duplex serial time-division-multiplexed (TDM) communication peripherals
* supports ISDN line interface chips and other PCM/TDM serial
devices
* address decoding for submodules within System Interface Module
(SIM)
* CHI interface is programmable (number of channels, frame rate,
bit rate, etc.) to provide support for a variety of formats
CPU Module
* R3000 RISC central processing unit core
- full 32-bit operation (registers, instructions, addresses) - 32 general purpose 32-bit registers; 32-bit program counter - MIPS RISC Instruction Set Architecture (ISA) supported
* supports data rates up to 4.096 Mbps * independent DMA support for CHI receive and transmit
Interrupt Module
* contains logic for individually enabling, reading, and clearing all
PR31500 interrupt sources
* on-chip cache
- 4 KByte direct-mapped instruction cache (I-cache) physical address tag and valid bit per cache line programmable burst size instruction streaming mode supported - 1 KByte data cache (D-cache) physical address tag and valid bit per cache line programmable burst size write-through - cache address snoop mode supported for DMA - 4-level deep write buffer
* interrupts generated from internal PR31500 modules or from edge
transitions on external signal pins
IO Module
* contains support for reading and writing the 7 bi-directional
general purpose IO pins and the 32 bi-directional multi-function IO pins
* each IO port can generate a separate positive and negative edge
interrupt
* independently configurable IO ports allow PR31500 to support a
flexible and wide range of system applications and configurations
* Memory Management Unit
- MIPS R3000A MMU contains on-chip TLB with: 32x64 bit wide entries fully associative 2 entry micro TLB for very fast instruction address translation Instruction address translation accesses full TLB after micro TLB miss Data address translation accesses full TLB
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Preliminary specification
Poseidon embedded processor
MIPS PR31500
* PR31500 supplies dedicated chip select and interrupt for an SPI
interface serial power supply
IR Module
* IR consumer mode
- allows control of consumer electronic devices such as stereos, TVs, VCRs, etc. - programmable pulse parameters - external analog LED circuitry
* 8-bit or 16-bit data word lengths for the SPI interface * programmable SPI baud rate
Timer Module
* IRDA communication mode
- allows communication with other IRDA devices such as FAX machines, copiers, printers, etc. - supported by UART module within PR31500 - external analog receiver preamp and LED circuitry - data rate = up to 115 Kbps at 1 meter
* Real Time Clock (RTC) and Timer * 40-bit counter (30.517 sec granularity);
maximum uninterrupted time = 388.36 days
* IR FSK communication mode
- supported by UART module within PR31500 - external analog IR chip(s) perform frequency modulation to generate the desired IR communication mode protocol - data rate = up to 36000 bps at 3 meters
* 40-bit alarm register (30.517 sec granularity) * 16-bit periodic timer (0.868 sec granularity);
maximum timeout = 56.8 msec
* interrupts on alarm, timer, and prior to RTC roll-over
UART Module
* carrier detect state machine
- periodically enables IR receiver to check if a valid carrier is present
* 2 independent full-duplex UARTs * programmable baud rate generator * UART-A port used for serial control interface to external IR
module
Power Module
* power-down modes for individual internal peripheral modules * serial (SPI port) power supply control interface supported * power management state machine has 4 states: RUNNING,
DOZING, SLEEP, and COMA
* UART-B port used for general purpose serial control interface * UART-A and UART-B DMA support for receive and transmit
Video Module
Serial Interconnect Bus (SIB) Module
* PR31500 contains holding and shift registers to support the serial
interface to the UCB1100 and/or other optional codec devices
* interface compatible with slave mode 3 of Crystal CS4216 codec * synchronous, frame-based protocol * PR31500 always master source of clock and frame frequency and
phase; programmable clock frequency
* bit-mapped graphics * supports monochrome, grey scale, or color modes * time-based dithering algorithm for grey scale and color modes * supports multiple screen sizes * supports split and non-split displays * variable size and relocatable video buffer * DMA support for fetching image data from video buffer
Little/Big Endian Configuration
The PR31500 can be configures as a Big Endian or as a Little Endian processor based on the /LB endian pin at power-up. The byte ordering is as follows: LITTLE ENDIAN D[31:24] D[23:16] D[15:8] D[7:0] /CAS3 /CAS2 /CAS1 /CAS0 BIG ENDIAN D[7:0] D[15:8] D[23:16] D[31:24] /CAS0 /CAS1 /CAS2 /CAS3
* each SIB frame consists of 128 clock cycles, further divided into 2
subframes or words of 64 bits each (supports up to 2 devices simultaneously)
* independent DMA support for audio receive and transmit, telecom
receive and transmit
* supports 8-bit or 16-bit mono telecom formats * supports 8-bit or 16-bit mono or stereo audio formats * independently programmable audio and telecom sample rates * CPU read/write registers for subframe control and status
System Peripheral Interface (SPI) Module
* provides interface to SPI peripherals and devices * full-duplex, synchronous serial data transfers (data in, data out,
and clock signals)
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Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
Figure 2 shows a typical system block diagram cosisting of PR31500 and UCB1100 for a total system solution.
1-2 PCMCIA Slots
32 KHz
3.3V I-Cache/RAM SYSCLK R3000 RISC CPU core
32-bit Bus Serial I/F and Magicbus LCD Interface
PR31500 D-Cache/ RAM
TLB
ID ROM Power Supply LCD Main Backup (Lithium) T
Thermistor
IR ISDN or other peripherals
High speed serial port
3.3V Phone Jack DAA or RF Xceiver
Figure 2. System Block Diagram
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II II II II
Touchscreen (Resistive)
III III III III III III III III
Memory Protection
PCMCIA/ROM I/F
Timers Real-time Clock
DRAM/SDRAM Interface
1-64 MBytes ROM
1-16 MBytes (S)DRAM
AC Adapter
UCB1100
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Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
PIN CONFIGURATION
208 1 157 156
208-PIN PLASTIC QUAD FLAT PACK
52 53 TOP VIEW 104 105
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Function VDD D(0) [D(24)] VSS D(1) [D(25)] D(2) [D(26)] VDD D(3) [D(27)] VSS D(4) [D(28)] VDD D(5) [D(29)] D(6) [D(30)] VSS D(7) [D(31)] VSS D(8) [D(16)] VDD D(9) [D(17)] D(10) [D(18)] VSS D(11) [D(19)] VDD D(12) [D(20)] D(13) [D(21)] VSS D(14) [D(22)] D(15) [D(23)] VDD /LB endian MFIO(1) - - VSS - VDD VDD SIBMCLK VSS SIBSCLK SIBSYNC SIBDIN SIBDOUT VDD SIBIRQ MFIO(0) IO(6) IO(50 VSS chiclk chifs chidin chidout
Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
Function VDD RXD TXD IO(4) IRIN IROUT VSS VDD CARDET TXPWR IO(3) IO(2) VSS SPICLK SPIIN SPIOUT VDD TESTCPU TESTIN VIDDONE TESTSIU VSS VCC3 BC32K VDD C32KIN C32KOUT VSS PWRCS PWRINT PWROK ONBUTN /PON /CPURES VDD DISPON FRAME VSS DF LOAD CP VSS VDD VDAT(0) VDAT(1) VDAT(2) VDAT(3) VSS IO(1) VDD
Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Function /CARD2WAIT /CARD2CSH /CARD2CSL IO(0) VSS /IORD /IOWR /CARDREG /CARD1WAIT VDD MFIO(2) VDD /CARD1CSL /CARD1CSH VSS /MCS3 /MCS2 /MCS1 /MCS0 /CS3 /CS2 /CS1 VDD SYSCLKIN SYSCLKOUT VSS VSS VDD D(31) [D(7)] D(30) [D(6)] VSS D(29) [D(5)] VDD D(28) [D(4)] D(27) [D(3)] VSS D(26) [D(2)] VSS D(25) [D(1)] VDD D(24) [D(0)] D(23) [D(15)] VDD D(22) [D(14)] VSS D(21) [D(13)] VDD D(20) [D(12)] D(19) [D(11)] VSS D(18) [D(10)] VDD
Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Function D(17) [D(9)] VSS D(16) [D(8)] VDD /CS0 /RD VSS VDD /DGRNT /DREQ ALE /WE VDD A(12) A(11) VSS A(10) A(9) VDD A(8) A(7) VSS A(6) A(5) VDD A(4) VSS A(3) A(2) VDD A(1) A(0) VSS VSS /DCS0 /RAS1 /RAS0 /CAS3 [/CAS0] VDD /CAS2 [/CAS1] /CAS1 [/CAS2] /CAS0 [/CAS3] VSS VDD DCKE VSS DCLKIN DCLKOUT VDD DQMH DQML
SN00164
NOTE: [ ] indicates the signal name in the Little Endian mode.
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Preliminary specification
Poseidon embedded processor
MIPS PR31500
PIN DESCRIPTIONS Overview
The PR31500 processor contains 208 pins consisting of input, output, bi-directional, and power and ground pins. These pins are used to support various functions. The following sections will describe the function of each pin including any special power-down considerations for each pin.
Pins
The PR31500 PROCESSOR contains 208 total pins, consisting of 136 signal pins, 4 spare pins, 34 power pins, and 34 ground pins. Of the 136 signal pins, 32 of them are multi-function and can be independently programmed either as IO ports or for an alternate standard/normal function. As an IO port, any of these pins can be programmed as an input or output port, with the capability of generating a separate positive and negative edge interrupt. See Section 2.3 for a summary of the multi-function IO ports versus their standard functions. PIN # Memory Pins D(31:0) I/O These pins are the data bus for the system. 8-bit SDRAMs should be connected to bits 7:0 and 16-bit SDRAMs and DRAMs should be connected to bits 15:0. All other 16-bit ports should be connected to bits 31:16. Of course, 32-bit ports should be connected to bits 31:0. These pins are normally outputs and only become inputs during reads, thus no resistors are required since the bus will only float for a short period of time during bus turn-around. These pins are the address bus for the system. The address lines are multiplexed and can be connected directly to SDRAM and DRAM devices. To generate the full 26-bit address for static devices, an external latch must be used to latch the signals using the ALE signal. For static devices, address bits 25:13 are provided by the external latch and address bits 12:0 (directly connected from PR31500's address bus) are held afterward by PR31500 processor for the remainder of the address bus cycle. This pin is used as the address latch enable to latch A(12:0) using an external latch, for generating the upper address bits 25:13. This pin is used as the read signal for static devices. This signal is asserted for reads from /MCS3-0, /CS3-0, /CARD2CS and /CARD1CS for memory and attribute space, and for reads from PR31500 processor accesses if SHOWPR31500 is enabled (for debugging purposes). This pin is used as the write signal for the system. This signal is asserted for writes to /MCS3-0, /CS3-0, /CARD2CS and /CARD1CS for memory and attribute space, and for writes to DRAM and SDRAM. This pin is used as the CAS signal for SDRAMs, the CAS signal for D(7:0) for DRAMs, and the write enable signal for D(7:0) for static devices. This pin is used as the CAS signal for D(15:8) for DRAMs and the write enable signal for D(15:8) for static devices. This pin is used as the CAS signal for D(23:16) for DRAMs and the write enable signal for D(23:16) for static devices. This pin is used as the CAS signal for D(31:24) for DRAMs and the write enable signal for D(31:24) for static devices. This pin is used as the RAS signal for SDRAMs and the RAS signal for Bank0 DRAMs. This pin is used as the chip select signal for Bank1 SDRAMs and the RAS signal for Bank1 DRAMs. This pin is used as the chip select signal for Bank0 SDRAMs. This pin is used as the clock enable for SDRAMs. This pin must be tied externally to the DCLKOUT signal and is used to match skew for the data input when reading from SDRAM and DRAM devices. This pin is the (nominal) 73.728 MHz clock for the SDRAMs. This pin is the upper data mask for a 16-bit SDRAM configuration. This pin is the lower data mask for a 16-bit SDRAM or 8-bit SDRAM configuration. These pins are the Chip Select 3 through 0 signals. They can be configured to support either 32-bit or 16-bit ports. These pins are the MagicCard Chip Select 3 through 0 signals. They only support 16-bit ports. These pins are the Chip Select signals for PCMCIA card slot 2. NAME TYPE NAME AND FUNCTION
A(12:0)
O
168 163
ALE /RD
O O
169
/WE
O
199 198 197 195 194 193 192 202 204 205 207 208 124-126, 162 120-123 106, 107
/CAS0 (/WE0) /CAS1 (/WE1) /CAS2 (/WE2) /CAS3 (/WE3) /RAS0 /RAS1 (/DCS1) /DCS0 DCKE DCLKIN DCLKOUT DQMH DQML /CS3-0 /MCS3-0 /CARD2CSH,L
O O O O O O O O I O O O O O O
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Preliminary specification
Poseidon embedded processor
MIPS PR31500
PIN #
NAME
TYPE
NAME AND FUNCTION
Memory Pins (continued) 117, 118 112 110 111 115 /CARD1CSH,L /CARDREG /CARDIORD /CARDIOWR /CARDDIR O O O O O These pins are the Chip Select signals for PCMCIA card slot 1. This pin is the /REG signal for the PCMCIA cards. This pin is the /IORD signal for the PCMCIA IO cards. This pin is the /IOWR signal for the PCMCIA IO cards. This pin is used to provide the direction control for bi-directional data buffers used for the PCMCIA slot(s). This signal will assert whenever /CARD2CSH or /CARD2CSL or /CARD1CSH or /CARD1CSL is asserted and a read transaction is taking place. This pin is the card wait signal from PCMCIA card slot 2. This pin is the card wait signal from PCMCIA card slot 1.
105 113
/CARD2WAIT /CARD1WAIT
I I
Bus Arbitration Pins 167 /DREQ I This pin is used to request external arbitration. If the TESTSIU signal is high and the TESTSIU function has been enabled, then once /DGRNT is asserted, external logic can initiate reads or writes to PR31500 processor registers by driving the appropriate input signals. If the TESTSIU signal is low or the TESTSIU function has not been enabled, then PR31500 memory transactions are halted and certain memory signals will be tri-stated when /DGRNT is asserted in order to allow an external master to access memory. This pin is asserted in response to /DREQ to inform the external test logic or bus master that it can now begin to drive signals.
166 Clock Pins 128 129 79 80 77 CHI Pins 50
/DGRNT
O
SYSCLKIN SYSCLKOUT C32KIN C32KOUT BC32K
I O I O O
This pin should be connected along with SYSCLKOUT to an external crystal which is the main PR31500 clock source. This pin should be connected along with SYSCLKIN to an external crystal which is the main PR31500 clock source. This pin along with C32KOUT should be connected to a 32.768 KHz crystal. This pin along with C32KIN should be connected to a 32.768 KHz crystal. This pin is a buffered output of the 32.768 KHz clock.
CHIFS
I/O
This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes. As an output, this pin allows PR31500 to be the master CHI sync source. As an input, this pin allows an external peripheral to be the master CHI sync source and the PR31500 CHI module will slave to this external sync. This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output, this pin allows PR31500 to be the master CHI clock source. As an input, this pin allows an external peripheral to be the master CHI clock source and the PR31500 CHI module will slave to this external clock. This pin is the CHI serial data output signal. This pin is the CHI serial data input signal.
49
CHICLK
I/O
52 51 IO Pins 46, 107, 47, 108, 56, 64, 64 30, 45
CHIDOUT CHIDIN
O I
IO(6:0)
I/O
These pins are general purpose input/output ports. Each port can be independently programmed as an input or output port. Each port can generate a separate positive and negative edge interrupt. Each port can also be independently programmed to use a 16 to 24 msec debouncer. These pins are multi-function input/output ports. Each port can be independently programmed as an input or output port, or can be programmed for multi-function use to support vendor-dependent test signals (for debugging purposes only). Each port can generate a separate positive and negative edge interrupt. Note that 30 other multi-function pins are available for usage as multi-function input/output ports. These pins are named after their respective standard/normal function and are not listed here.
MFIO(1:0)
I/O
Endian Processor Pin 29 /LB endian I Little/Big Endian. This pin, when pulled Low at power-up, configures the PR31500 as a Little Endian. When this pin is pulled High at power-up, it configures the PR31500 as a Big Endian processor.
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Preliminary specification
Poseidon embedded processor
MIPS PR31500
PIN # Reset Pins 88
NAME
TYPE
NAME AND FUNCTION
/CPURES
I
This pin is used to reset the CPU core. This pin should be connected to a switch for initiating a reset in the event that a software problem might hang the CPU core. The pin should also be pulled up to VSTANDBY through an external pull-up resistor. This pin serves as the Power On Reset signal for PR31500. This signal must remain low when VSTANDBY is asserted until VSTANDBY is stable. Once VSTANDBY is asserted, this signal should never go low unless all power is lost in the system.
87
/PON
I
Power Supply Pins 86 ONBUTN I This pin is used as the On Button for the system. Asserting this signal will cause PWRCS to set to indicate to the System Power Supply to turn power on to the system. PWRCS will not assert if the PWROK signal is low. This pin is used as the chip select for the System Power Supply. When the system is off, the assertion of this signal will cause the System Power Supply to turn VCCDRAM and VCC3 on to power up the system. The Power Supply will latch SPI commands on the falling edge of PWRCS. This pin provides a status from the System Power Supply that there is a good source of power in the system. This signal typically will be asserted if there is a Battery Charger supplying current or if the Main Battery is good and the Battery Door is closed. If PWROK is low when the system is powered off, PWRCS will not assert as a result of the user pressing the ONBUTN or an interrupt attempting to wake up the system. If the device is on when the PWROK signal goes low, the software will immediately shut down the system since power is about to be lost. When PWROK goes low, there must be ample warning so that the software can shut down the system before power is actually lost. This pin is used by the System Power Supply to alert the software that some status has changed in the System Power Supply and the software should read the status from the System Power Supply to find out what has changed. These will be low priority events, unlike the PWROK status, which is a high priority emergency case. This pin provides the status of the power supply for the ROM, UCB1100, system buffers, and other transient components in the system. This signal will be asserted by the System Power Supply when PWRCS is asserted, and will always be turned off when the system is powered down.
82
PWRCS
O
84
PWROK
I
83
PWRINT
I
76
VCC3
I
SIB Pins 41 42 39 40 SIBDIN SIBDOUT SIBSCLK SIBSYNC I O O O This pin contains the input data shifted from UCB1100 and/or external codec device. This pin contains the output data shifted to UCB1100 and/or external codec device. This pin is the serial clock sent to UCB1100 and/or external codec device. The programmable SIBSCLK rate is derived by dividing down from SIBMCLK. This pin is the frame synchronization signal sent to UCB1100 and/or external codec device. This frame sync is asserted for one clock cycle immediately before each frame starts and all devices connected to the SIB monitor SIBSYNC to determine when they should transmit or receive data. This pin is a general purpose input port used for the SIB interrupt source from UCB1100. This interrupt source can be configured to generate an interrupt on either a positive and/or negative edge. This pin is the master clock source for the SIB logic. This pin is available for use in one of two modes. First, SIBMCLK can be configured as a high-rate output master clock source required by certain external codec devices. In this mode all SIB clocks are synchronously slaved to the main PR31500 system clock CLK2X. Conversely, SIBMCLK can be configured as an input slave clock source. In this mode, all SIB clocks are derived from an external SIBMCLK oscillator source, which is asynchronous with respect to CLK2X. Also, for this mode, SIBMCLK can still be optionally used as a high-rate master clock source required by certain external codec devices.
44
SIBIRQ
I
37
SIBMCLK
I/O
SPI Pins 67 69 68 SPICLK SPIOUT SPIIN O O I This pin is used to clock data in and out of the SPI slave device. This pin contains the data that is shifted into the SPI slave device. This pin contains the data that is shifted out of the SPI slave device.
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Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
PIN #
NAME
TYPE
NAME AND FUNCTION
UART and IR Pins 55 54 59 58 TXD RXD IROUT IRIN RXPWR 62 Video Pins 91 FRAME O This pin is the frame synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to return it's pointers to the top of the display. The Video Module asserts FRAME after all the lines of the LCD have been shifted and transferred, producing a full frame of display. This pin is the AC signal for the LCD. Since LCD plasma tends to deteriorate whenever subjected to a DC voltage, the DF signal is used by the LCD to alternate the polarity of the row and column voltages used to turn the pixels on and off. The DF signal can be configured to toggle on every frame or can be configured to toggle every programmable number of LOAD signals. This pin is the line synchronization pulse signal between the Video Module and the LCD, and is used by the LCD to transfer the contents of it's horizontal line shift register to the LCD panel for display. The Video Module asserts LOAD after an entire horizontal line of data has been shifted into the LCD. This pin is the clock signal for the LCD. Data is pushed by the Video Module on the rising edge of CP and sampled by the LCD on the falling edge of CP. These pins are the data for the LCD. These signals are directly connected to the LCD for 4-bit non-split displays. For 4-bit split and 8-bit non-split displays, an external register is required to demultiplex the 4-bit data into the desired 8 parallel data lines needed for the LCD. This pin is the display-on enable signal for the LCD. CARDET O I O I O I This pin is the UART transmit signal from the UARTA module. This pin is the UART receive signal to the UARTA module. This pin is the UART transmit signal from the UARTB module or the Consumer IR output signal if Consumer IR mode is enabled. This pin is the UART receive signal to the UARTB module. This pin is the receiver power output control signal to the external communication IR analog circuitry. This pin is the carrier detect input signal from the external communication IR analog circuitry.
93
DF
O
94
LOAD
O
95 101, 100, 99, 98 90 Test Pins 74
CP VDAT(3:0)
O O
DISPON
O
TESTSIU
I
This pin allows external logic to initiate read or write transactions to PR31500 registers. The TESTSIU mode is enabled by toggling this signal after the device has powered up. Once the function is enabled, if the TESTSIU pin is high when the bus is arbitrated (using /DREQ and /DGRNT), then external logic can initiate read and write transactions to PR31500 registers. This pin is used for debugging purposes only. This pin allows numerous internal CPU core signals to be brought to external PR31500 pins, in place of the normal signals assigned to these pins. The CPU core signals assigned to their respective pins during TESTCPU mode are vendor-dependent. The TESTCPU mode is enabled by asserting this TESTCPU signal, and this function is provided for generating test vectors for the CPU core. This pin is used for debugging purposes only. This pin is reserved for vendor-dependent use. This pin is used for debugging purposes only. This signal is used to synchronize UCB1100 to read touchscreen input, when there is no video data shifted into LCD panel.
71
TESTCPU
I
72 73 Spare Pins
TESTIN VIDDONE
I O
NC4-1 34 32, 31 Power Supply Pins VDD (34 each) VSS (34 each)
No Connect - -
These pins are reserved for future use and should be left unconnected. Reserved. Reserved.
+3.3V GND
These pins are the power pins for PR31500 and should be connected to the digital +3.3V power supply VSTANDBY. These pins are the ground pins for PR31500 and should be connected to digital ground. NOTE: For some vendor-dependent implementations of PR31500, pin 131 may be used for a filter capacitor for the SYSCLK oscillator (capacitor connected between pin 131 and digital ground).
1996 Sep 24
11
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS
VSS = 0V SYMBOL VDD VIN Tstg Pd Power supply voltage Input voltage Storage temperature range Maximum dissipation (Tamb = 70C) PARAMETER LIMITS VSS - 0.5 to 4.5 VSS - 0.5 to VDD + 0.5 -55 to +125 1 UNIT V V C W
RECOMMENDED OPERATING CONDITION
VSS = 0V LIMITS SYMBOL VDD VIN Topr Power supply voltage Input voltage Operating temperature range PARAMETER MIN 3.0 VSS 0 TYP 3.3 - - MAX 3.6 VDD 70 UNIT V V C
DC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70C, VDD = 3.3 0.3V. LIMITS SYMBOL IDD IDDS IL VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 IIHP PARAMETER Operating current Static current Input leakage current High level input voltage1 Low level input High level input voltage1 voltage2 voltage3 voltage4 voltage5 CONDITIONS VIN = VDD or VSS; VDD = MAX IOH = IOL = 0 VIN = VDD or VSS; VDD = MAX IOH = IOL = 0 VDD = MAX; VIH = VDD VIL = VSS VDD = 3.6V VDD = 3.0V VDD = 3.6V VDD = 3.0V VDD = 3.0; IOH = -4mA VDD = 3.0; IOL = 4mA VDD = 3.0; IOH = -8mA VDD = 3.0; IOL = 8mA VDD = 3.0; IOH = -16mA VDD = 3.0; IOL = 16mA VDD = 3.0; IOH = -24mA VDD = 3.0; IOL = 24mA VDD = MAX; VIN = VDD MIN - - -10 VDD x 0.8 -0.3 2.4 -0.3 VDD - 0.6 - VDD - 0.6 - VDD - 0.6 - VDD - 0.6 - 20 TYP 110 10 - - - - - - - - - - - - - - MAX TBD 100 10 VDD + 0.3 VDD x 0.2 VDD + 0.3 0.6 - VSS + 0.4 - VSS + 0.4 - VSS + 0.4 - VSS + 0.4 120 UNIT mA A A V V V V V V V V V V V V A
Low level input voltage2 High level output Low level output voltage3 High level output Low level output voltage4 High level output Low level output voltage5 High level output voltage Low level output voltage Input current (pull-down resistor)
NOTES: 1. SYSVLKIN 2. Other inputs 3. D[31:0], /RAS0, /RAS1, /DCS0, /DCKE, DQMH, DQML, /DREQ, /DGRNT, BC32K, VDAT[3:0], CP, LOAD, DF, FRAME, DISPON, VIDDONE, PWRCS, TXD, RXD, /CS03, /MCS03, CHIFS, CHICLK, CHIDOUT, CHIDIN, IO[6:0], SPICLK, SPIOUT, SPIIN, SIBSYNC, SIBOUT, SIBMCLK, SIBCLK, RXPWR, IROUT, /CRAD1WAIT, /CARD2WAIT, MIOX[2:0] 4. A[12:0], ALE, /RD, /WE /CAS03, /CARDREG, /IOWR, /CARD1CSL, /CARD1CSH, /CARD2CSL, /CARD2CSH 5. DCLKOUT
1996 Sep 24
12
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
AC ELECTRICAL CHARACTERISTICS
2.0V 0.8V DELAY
2.2V OUTPUTS 0.8V SETUP 0.8VCC INPUTS 0.2VCC 2.2V 0.8V HOLD 2.2V 0.8V
SN00165
Figure 3. PR31500 Timing - Definition of AC Specification
1996 Sep 24
13
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
CRYSTAL OSCILLATOR CHARACTERISTICS 10MHz Crystal
SYSCLKIN 128 SYSCLKOUT 129
100 RECOMMENDED 10MHz CRYSTAL NIHON DEMPA KOGYO CO., LTD.: AT1-51 CIN XTAL COUT
SN00166
RECOMMENDED VALUE SYMBOL Crystal Oscillator frequency crystal impedance External capacitors PARAMETER MIN. fIN CI CIN, COUT 8.25 TBD 10 MAX. 10 TBD 33 MHz k pF UNIT
32kHz Crystal
C32KIN 79 C32KOUT 80
RECOMMENDED 32kHz CRYSTAL KYOCERA CORPORATION: KF-38G CIN XTAL COUT
SN00167
RECOMMENDED VALUE SYMBOL CIN, COUT External capacitors PARAMETER MIN. 10 MAX. 33 pF UNIT
1996 Sep 24
14
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
MEMORY INTERFACE
Tamb = 0 to +70C, VDD = 3.3 0.3V, External Capacitance = 40pF LIMITS ITEM 1 2 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 6 5 6 7 DCLKOUT high time DCLKOUT low time DCLKOUT period Delay DCLKOUT to ALE Delay DCLKOUT to A[12:0] Delay DCLKOUT to D[31:16] Delay DCLKOUT to D[15:0] Delay DCLKOUT to /CS3-0 Delay DCLKOUT to /RD Delay DCLKOUT to /WE Delay DCLKOUT to /SAS3-0 Delay DCLKOUT to /CARDxCSx Delay DCLKOUT to /CARDDIR Delay DCLKOUT to /CARDREG Delay DCLKOUT to /IORD Delay DCLKOUT to /IOWR Delay DCLKOUT to /RAS0 Delay DCLKOUT to /RAS1 Delay DCLKOUT to DQMH/L Delay DCLKOUT to /DCS0 Delay DCLKOUT to DCKE Delay DCLKOUT to /MCS3-0 D[31:16] to DCLKIN Setup time D[31:16] to DCLKIN Hold time D[15:0] to DCLKIN Setup time D[15:0] to DCLKIN Hold time DCLKOUT to DCLKIN Board Delay time PARAMETER RISING/FALLING - - - Rising Falling - - - Rising Falling Risng Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling - - - - - MIN 5.4 5.4 13.5 - - - - 1.5 - - - - - - - - - - - - - - - - - - - - 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 - - 2 1 1 1.5 0 MAX - - - 4 3 8 8 8 10 10 8 7 5 4 1.5 1.5 9 8 12 11 9 10 10 9 9 9 6 6 8 9 8 9 7 6 8 8 10 10 - - - - 3 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1996 Sep 24
15
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
MEMORY INTERFACE TIMING DIAGRAMS
1 2
DCLKOUT
MEMORY OUTPUTS
3
4
SN00168
Figure 1. Memory Output and Clock Timing
DCLKIN
MEMORY INPUTS
5
6
SN00169
Figure 2. Memory Input Timing
DCLKOUT
7
DCLKIN
SN00170
Figure 3. DCLKOUT to DCLKIN
1996 Sep 24
16
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
CHI
Tamb = 0 to +70C, VDD = 3.3 0.3V, External Capacitance = 40pF LIMITS ITEM 1 2 3 4 7 4 7 4 7 4 7 5 6 8 9 5 6 8 9 5 6 8 9 CHICLK high time CHICLK low time CHICLK period Delay CHICLK Rising to CHIDOUT (Master) Delay CHICLK Falling to CHIDOUT (Master) Delay CHICLK Rising to CHIFS (Master) Delay CHICLK Falling to CHIFS (Master) Delay CHICLK Rising to CHIDOUT (Slave) Delay CHICLK Falling to CHIDOUT (Slave) Delay CHICLK Rising to CHIFS (Slave) Delay CHICLK Falling to CHIFS (Slave) CHIDIN to CHICLK Rising Setup time (Master) CHIDIN to CHICLK Rising Hold time (Master) CHIDIN to CHICLK Falling Setup time (Master) CHIDIN to CHICLK Falling Hold time (Master) CHIFS to CHICLK Rising Setup time (Slave) CHIFS to CHICLK Rising Hold time (Slave) CHIFS to CHICLK Falling Setup time (Slave) CHIFS to CHICLK Falling Hold time (Slave) CHIDIN to CHICLK Rising Setup time (Slave) CHIDIN to CHICLK Rising Hold time (Slave) CHIDIN to CHICLK Falling Setup time (Slave) CHIDIN to CHICLK Falling Hold time (Slave) PARAMETER RISING/FALLING - - - Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling - - - - - - - - - - - - MIN 100 100 225 - - - - - - - - - - - - - - - - 20 20 20 20 20 20 20 20 20 20 20 20 MAX - - - 5 5 5 5 5 5 5 5 10 10 10 10 10 10 10 10 - - - - - - - - - - - - UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1996 Sep 24
17
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
CHI TIMING DIAGRAMS
1 2
CHICLK
CHI OUTPUTS
3
4
SN00171
Figure 4. CHI Output and Clock Timing (CHITXEDGE = 1)
CHICLK
CHI INPUTS
5
6
SN00172
Figure 5. CHI Input Timing (CHIRXEDGE = 1)
CHICLK
CHI OUTPUTS
7
SN00173
Figure 6. CHI Output and Clock Timing (CHITXEDGE = 0)
CHICLK
CHI INPUTS
8
9
SN00174
Figure 7. CHI Input Timing (CHIRXEDGE = 0)
1996 Sep 24
18
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
SIB
Tamb = 0 to +70C, VDD = 3.3 0.3V, External Capacitance = 40pF LIMITS ITEM 1 2 3 4 5 6 6 7 8 SIBMCLK high time SIBMCLK low time SIBMCLK period Delay SIBMCLK to SIBSCLK Delay SIBMCLK to SIBSCLK Delay SIBSCLK Rising to SIBSYNC Delay SIBSCLK Rising to SIBDOUT SIBDIN to SIBSCLK Rising Setup time SIBDIN to SIBSCLK Rising Hold time PARAMETER RISING/FALLING - - - Rising Falling Rising Falling Rising Falling - - MIN 20 20 50 - - - - - - 20 0 MAX - - - 5 5 2 2 2 2 - - UNIT ns ns ns ns ns ns ns ns ns ns ns
SIB TIMING DIAGRAMS
1 2
SIBMCLK
3 4
5
SIBSCLK
SN00175
Figure 8. SIB CLK Timing
SIBSCLK
SIB OUTPUTS 6
SIBDIN
7
8
SN00176
Figure 9. SIB Timing
1996 Sep 24
19
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
SPI
LIMITS ITEM 1 2 3 4 4 7 7 8 9 5 6 SPIMCLK high time SPICLK low time SPICLK period Delay SPICLK Rising to SPIOUT Delay SPICLK Rising to SPIOUT Delay SPICLK Falling to SPIOUT Delay SPICLK Falling to SPIOUT SPIIN to SPICLK Rising Setup time SPIIN to SPICLK Rising Hold time SPIIN to SPICLK Falling Setup time SPIIN to SPICLK Falling Hold time PARAMETER RISING/FALLING - - - Rising Falling Rising Falling - - - - MIN 120 120 250 - - - - 15 15 15 15 - - - - MAX - - - UNIT ns ns ns ns ns ns ns ns ns ns ns
SPI TIMING DIAGRAMS
1 2
SPICLK
SPIOUT
3
4
SPIIN
5
6
SN00177
Figure 10. SPI Timing (PHAPOL = 1)
SPICLK
SPIOUT
7
SPIIN
8
9
SN00178
Figure 11. SPI Timing (PHAPOL = 0)
1996 Sep 24
20
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
VIDEO
Tamb = 0 to +70C, VDD = 3.3 0.3V, External Capacitance = 40pF LIMITS ITEM 1 2 3 4 5 6 7 LOAD Pulse width Delay LOAD Falling to FRAME Delay LOAD Falling to DF Delay LOAD Falling to CP Delay CP Rising to VDAT[3:0] VDAT to CP Rising Setup VDAT to CP Rising Hold PARAMETER RISING/FALLING - - - - - - - MIN 100 100 100 100 - 15 15 MAX 1600 3200 3200 3200 3 25 25 UNIT ns ns ns ns ns ns ns
NOTE: Values shown assume a 40MHz clock for the CPU, MIN and MAX values are programmable using Video Control Registers.
VIDEO TIMING DIAGRAMS
2 FRAME
DF
3
LOAD
1
4
CP
VDAT[3:0]
5
SN00179
Figure 12. Video Timing, 4 Bit Non-Split LCD
CP
VDAT[3:0]
6
7
SN00180
Figure 13. Video Data Timing, 4 Bit Split LCD and 8 Bit Non-Split LCD
1996 Sep 24
21
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS PR31500
POWER
Tamb = 0 to +70C, VDD = 3.3 0.3V, External Capacitance = 40pF LIMITS ITEM 1 2 PARAMETER VSTANDBY to /PON Rising VSTANDBY to ONBUTN delay time RISING/FALLING - - MIN 50 2 MAX - - UNIT ns s
POWER TIMING DIAGRAM
VSTANDBY
1
/PON 2
ONBUTN
SN00181
Figure 14.
CPU RESET
Tamb = 0 to +70C, VDD = 3.3 0.3V, External Capacitance = 40pF LIMITS ITEM 1 /CPURES low time PARAMETER RISING/FALLING - MIN 10 MAX - UNIT ns
1
/CPURES
SN00182
Figure 15.
1996 Sep 24
22
Philips Semiconductors
Preliminary specification
Poseiden embedded processor
MIPS PR31500
LQFP208: 208-PIN PLASTIC LOW PROFILE QUAD FLAT PACKAGE
1.25 TYP.
156 157
105
104
30.00 0.2
28.00 0.1
208 52 0.5 1.25 TYP. 0.22 +0.05 -0.04 0.1
53
1
1.4 0.05 0.1 29.00 0.2 0.17 +0.03 -0.05 0.45-0.75
UNIT = mm (Drawing not to scale)
0.25
(0.5)
0-10
1996 Sep 24
23
0.1 0.05
1.7 MAX.
Philips Semiconductors
Preliminary specification
Poseiden embedded processor
MIPS PR31500
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1996 Sep 24 24

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