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| Preliminary PLL602-89T 12-27 MHz XO IC with 3 Pairs of LVDS and 1 CMOS Outputs FEATURES * * * * * * * Low jitter XO for the 12MHz to 27MHz range. Integrated crystal load capacitor: no external load capacitor required. 3 pairs of LVDS outputs and 1 CMOS output. 12-27 MHz fundamental crystal input. Low jitter (RMS): 2.5 ps period jitter (1 sigma). 2.5V to 3.3V operation. Available in 16-Pin SSOP package. PIN CONFIGURATION (Top View) VDDBUF VDDANA VDDANA XOUT XIN GNDBUF GNDANA CMOS_CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 LVDS1BAR_CLK LVDS1_CLK GNDBUF LVDS2BAR_CLK LVDS2_CLK VDDBUF LVDS3BAR_CLK LVDS3_CLK 16 - pin SSOP PLL602-89T DESCRIPTION The PLL602-89T is a high performance multiple output XO IC chip. It provides 3 pairs of LVDS and 1 CMOS outputs. The chip combines a crystal oscillator (XO) with a multiple-output buffer. It accepts a low cost fundamental parallel resonant mode crystal from 12MHz to 27MHz, which is reproduced at the outputs. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for data and telecommunication applications. BLOCK DIAGRAM LVDS1_CLK LVDS1BAR_CLK XIN XOUT Oscillator Amplifier LVDS2_CLK LVDS2BAR_CLK LVDS3_CLK LVDS3BAR_CLK CMOS_CLK 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1 Preliminary PLL602-89T 12-27 MHz XO IC with 3 Pairs of LVDS and 1 CMOS Outputs PIN DESCRIPTION Name VDD XOUT XIN GND CMOS_CLK LVDS3_CLK LVDS3BAR_CLK LVDS2_CLK LVDS2BAR_CLK LVDS1_CLK LVDS1BAR_CLK Pin Number 1,2,3,11 4 5 6,7,14 8 9 10 12 13 15 16 Type P I I P O O O O O O O Description +3.3V VDD connection. VDDANA and VDDBUF should be decoupled separately. Crystal out connector. This is the output of the crystal oscillator circuitry. The crystal should be mounted as close to the IC as possible, with minimum parasitic capacitance. Crystal in connector. This is the input of the crystal oscillator circuitry. The crystal should be mounted as close to the IC as possible, with minimum parasitic capacitance. Ground connection. CMOS output signal. LVDS output. LVDS complementary output. LVDS output. LVDS complementary output. LVDS output. LVDS complementary output. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Recommended ESR SYMBOL FXIN CL (xtal) RE CONDITIONS Parallel Fundamental Mode MIN. 12 TYP. 21.5 MAX. 27 30 UNITS MHz pF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2 Preliminary PLL602-89T 12-27 MHz XO IC with 3 Pairs of LVDS and 1 CMOS Outputs 3. General Electrical Specifications PARAMETERS Operating Voltage Supply Current, Dynamic (with Loaded Outputs) Short Circuit Current SYMBOL VDD IDD CONDITIONS CMOS outputs loaded with 15pF, LVDS outputs loaded with 100 Fout = 12 MHz Fout = 25 MHz MIN. 2.25 TYP. 15 20 50 MAX. 3.63 20 25 UNITS V mA mA 4. AC Electrical Specifications PARAMETERS Input Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle tr tr tf tf 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load 2.0V ~ 0.8V with 10 pF load 3.0V ~ 0.3V with 15pF load Measured @ 1.25 V (LVDS) Measured @ 50% VDD (CMOS) SYMBOL CONDITIONS MIN. 12 TYP. MAX. 27 1.5 5 1.5 5 55 55 UNITS MHz 2 2 50 50 ns 45 45 % 5. Jitter Specifications PARAMETERS Period jitter RMS Peak to Peak jitter CONDITIONS With capacitive decoupling between VDD and GND. With capacitive decoupling between VDD and GND. Over 10,000 cycles. FREQUENCY 25MHz 25MHz MIN. TYP. 2.5 18 MAX. 4 30 UNITS ps ps 6. CMOS Output Electrical Specifications PARAMETERS Output Output Output level Output High Voltage Low Voltage High Voltage at CMOS drive current SYMBOL VOH VOL VOHC CONDITIONS IOH = -12mA IOL = 12mA IOH = -4mA At TTL level MIN. 2.4 TYP. MAX. 0.4 UNITS V V V mA VDD- 0.4 10 7. CMOS Switching Characteristics PARAMETERS Output Clock Rise/Fall Time (Standard Drive) SYMBOL CONDITIONS 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load MIN. TYP. 1.15 2.4 MAX. UNITS ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3 Preliminary PLL602-89T 12-27 MHz XO IC with 3 Pairs of LVDS and 1 CMOS Outputs 8. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current SYMBOL VOD VOD VOH VOL VOS VOS IOXD IOSD CONDITIONS MIN. 247 -50 TYP. 355 1.4 1.1 1.2 3 1 -5.7 MAX. 454 50 1.6 1.375 25 10 -8 UNITS mV mV V V V mV uA mA RL = 100 (see figure) 0.9 1.125 0 Vout = VDD or GND VDD = 0V 9. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS RL = 100 CL = 10 pF (see figure) MIN. 0.2 0.2 TYP. 0.7 0.7 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT 50 CL = 10pF VOD VOS VDIFF RL = 100 50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4 Preliminary PLL602-89T 12-27 MHz XO IC with 3 Pairs of LVDS and 1 CMOS Outputs PACKAGE INFORMATION 16 PIN SSOP ( inch ) SSOP Symbol A A1 B C D E H L e Min. .053 .004 .008 .007 .189 .150 .228 .016 Nom. .064 .006 .193 .154 .236 .025 .025 BASIC Max. .069 .010 .012 .010 .197 .157 .244 .050 A1 B C L e A D E H ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL602-89T PART NUMBER XC TEMPERATURE RANGE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE X=SSOP Order Number PLL602-89TXC-R PLL602-89TXC Marking P602-89T XC P602-89T XC Package Option SSOP - Tape and Reel SSOP - Tube PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information urnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 5 |
Price & Availability of P602-89TXC
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