View P502-30DC_1292996.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PLL502-30
750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
FEATURES
* * * * * * * * * * 750kHz to 800MHz output range. Low phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz). Selectable CMOS, PECL and LVDS output. Selectable High Drive or Standard CMOS. 12 to 25MHz crystal input. No external load capacitor or varicap required. Output Enable selector. Wide pull range (+/-200ppm) 3.3V operation. Available in DIE (65 mil x 62 mil).
DIE CONFIGURATION
65 mil
OUTSEL0^
OUTSEL1^
SEL0^
SEL1^
VDD
VDD
VDD
VDD
(1550,1475)
17 16
25
24
23
22
21
20
19
18
GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^
XIN XOUT SEL3^
62 mil
26
Die ID: A0505-18
27
15
28
14
13
SEL2^
29
12
11
OE_CTRL VCON
30
DESCRIPTION
The PLL502-30 is a monolithic low jitter and low phase noise (-142dBc/Hz @ 10kHz offset) VCXO IC Die, with CMOS, LVDS and PECL output, covering the 750kHz to 800MHz output range. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The same die can be used as a VCXO with output frequencies ranging from F XIN / 16 to F XIN x 32 thanks to frequency selector pads. This makes the PLL502-30 ideal as a universal die for applications ranging from ADSL to SONET.
C502A
10 31 1 2 3 4 5 6 7 8 9
Y X
(0,0)
Note: ^ denotes internal pull up
OUTPUT SELECTION AND ENABLE
OUTSEL1 (Pad #18) 0 0 1 1 OUTSEL0 (Pad #25) 0 1 0 1
OE_CTRL (Pad #30)
Selected Output High Drive CMOS Standard CMOS PECL LVDS
State
DIE SPECIFICATIONS
Name Size Reverse side Pad dimensions Thickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil
OE_SELECT (Pad #9)
0
BLOCK DIAGRAM
VCO Divider Charge Pump + Loop Filter VCO
1 (Default)
Pad #9:
0 (Default) 1 0 1 (Default)
Output enabled Tri-state Tri-state Output enabled
Bond to GND to set to "0", bond to VDD to set to "1"
Pad #30: Logical states defined by PECL levels if OE_SELECT is "0" Logical states defined by CMOS levels if OE_SELECT is "1"
CLKBAR CLK
SEL
Reference Divider XTAL OSC VARICAP
Phase Detector
XIN XOUT
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 1
GNDBUF
GND
GND
GND
GND
GND
GND
N/C
PLL502-30
750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
FREQUENCY SELECTION TABLE
SEL3 (Pad #28) SEL2 (Pad #29) SEL1 (Pad #19) SEL0 (Pad #20) Selected Multiplier
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Reserved Reserved Reserved Fin x 32 Reserved Reserved Fin / 8 Fin x 2 Reserved Fin / 2 Fin / 16 Fin x 4 Fin / 4 Fin x 8 Fin x 16 No multiplication
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 2
PLL502-30
750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR
SYMBOL
FXIN CL (xtal) C0/C1 (xtal) RE
CONDITIONS
Parallel Fundamental Mode at VCON = 1.65V AT cut AT cut
MIN.
12
TYP.
9.5
MAX.
25 250 30
UNITS
MHz pF
Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity VCON pin input impedance VCON modulation BW
SYMBOL
TVCXOSTB
CONDITIONS
From power valid FXIN = 12 - 25MHz; XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V
MIN.
TYP.
MAX.
10
UNITS
ms ppm ppm ppm/V % k kHz
500 200 150 10 2000 25
0V VCON 3.3V, -3dB
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications PARAMETERS
Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
IDD VDD
CONDITIONS
PECL/LVDS/CMOS Fout<24MHz 24MHzMIN.
TYP.
MAX.
60/28/15 65/45/30 100/80/40 3.63 55 55 55
UNITS
mA V % mA
@ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD - 1.3V (PECL)
2.97 45 45 45
50 50 50 50
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 3
PLL502-30
750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
5. Jitter Specifications PARAMETERS CONDITIONS
With capacitive decoupling between VDD and GND. Over 10,000 cycles.
FREQUENCY
19.44MHz 77.76MHz 155.52MHz 622.08MHz 19.44MHz 77.76MHz 155.52MHz 622.08MHz 155.52MHz 622.08MHz
MIN.
TYP.
2.2 3.5 4.3 5.0 17 25 27 35 2.6 2.5
MAX.
UNITS
Period jitter RMS 1
ps
Period jitter Peak-toPeak 1
With capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz
ps
Integrated jitter RMS 2
4 4
ps
6. Phase Noise Specifications PARAMETERS
Phase Noise 2 relative to carrier (typical)
FREQUENCY
19.44MHz 77.76MHz 155.52MHz 622.08MHz
@10Hz
-80 -72 -65 -55
@100Hz
-108 -103 -95 -85
@1kHz
-132 -122 -120 -109
@10kHz
-142 -130 -125 -115
@100kHz
-150 -125 -121 -110
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Electrical Characteristics PARAMETERS
Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive)
SYMBOL
IOH IOL IOH IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V 0.3V ~ 3.0V with 15 pF load 0.3V ~ 3.0V with 15 pF load
MIN.
30 30 10 10
TYP.
MAX.
UNITS
mA mA mA mA
2.4 1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 4
PLL502-30
750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
8. LVDS Electrical Characteristics PARAMETERS
Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current
SYMBOL
VOD VOD VOH VOL VOS VOS IOXD IOSD
CONDITIONS
MIN.
247 -50
TYP.
355
MAX.
454 50
UNITS
mV mV V V V mV uA mA
RL = 100 (see figure)
1.4 0.9 1.125 0 1.1 1.2 3 1 -5.7
1.6 1.375 25 10 -8
Vout = VDD or GND VDD = 0V
9. LVDS Switching Characteristics PARAMETERS
Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
tr tf
CONDITIONS
RL = 100 CL = 10 pF (see figure)
MIN.
0.2 0.2
TYP.
0.7 0.7
MAX.
1.0 1.0
UNITS
ns ns
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% VDIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 5
PLL502-30
750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
10. PECL Electrical Characteristics PARAMETERS
Output High Voltage Output Low Voltage
SYMBOL
VOH VOL
CONDITIONS
RL = 50 to (VDD - 2V) (see figure)
MIN.
VDD - 1.025
MAX.
VDD - 1.620
UNITS
V V
11. PECL Switching Characteristics PARAMETERS
Clock Rise Time Clock Fall Time
SYMBOL
tr tf
CONDITIONS
@20/80% - PECL @80/20% - PECL
MIN.
TYP.
0.6 0.5
MAX.
1.5 1.5
UNITS
ns ns
PECL Levels Test Circuit
OUT VDD OUT
PECL Output Skew
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 6
PLL502-30
750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
PAD ASSIGNMENT
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name GND GND GND GND GND N/C GND GNDBUF OE_SELECT LVDS PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1 SEL1 SEL0 VDD VDD VDD VDD OUTSEL0 XIN XOUT SEL3 SEL2 OE_CTRL VCON X (m) 248 361 473 587 702 874 1042 1171 1400 1400 1400 1400 1400 1400 1400 1400 1389 1232 1042 854 659 559 459 358 194 109 109 109 109 109 109 Y (m) 109 109 109 109 109 109 109 109 125 259 476 616 716 871 1089 1227 1365 1365 1365 1365 1365 1365 1365 1365 1365 1223 1017 858 646 397 181 Ground. Ground. Ground. Ground. Ground. No Connection. Ground. Ground, buffer circuitry. Used to select between PECL or CMOS logic states for OE. Internal pull up. LVDS Output. PECL Output. 3.3V power supply, Buffer circuitry. 3.3V power supply, Buffer circuitry. Complementary PECL Output. Complementary LVDS Output. CMOS Output. Ground, buffer circuitry. Used to select CMOS, PECL or LVDS output type. Internal pull up. Used to select multiplication factor. Internal pull up. Used to select multiplication factor. Internal pull up. 3.3V power supply. 3.3V power supply. 3.3V power supply. 3.3V power supply. Used to select CMOS, PECL or LVDS output type. Internal pull up. Crystal input. See crystal specification page 3. Crystal output. See crystal specification page 3. Used to select multiplication factor. Internal pull up. Used to select multiplication factor. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Voltage Control Input. 0V to 3.3V. Description
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 7
PLL502-30
750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL502-30 D C
PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE D=DIE
Order Number PLL502-30DC
Marking P502-30DC
Package Option Die (Waffle Pack)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 8

▲Up To Search▲

Price & Availability of P502-30DC

	To Download P502-30DC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .