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| P4C1024 HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM FEATURES High Speed (Equal Access and Cycle Times) -- 15/20/25/35 ns (Commercial) -- 20/25/35/45 ns (Industrial) -- 20/25/35/45/55/70/85/100/120 ns (Military) Single 5 Volts 10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down Packages --32-Pin 300 mil DIP and SOJ --32-Pin 400 mil SOJ --32-Pin 600 mil Ceramic DIP --32-Pin 400 mil Ceramic DIP --32-Pin Solder Seal Flatpack --32-Pin LCC (450 x 500 mil) --32-Pin Ceramic SOJ DESCRIPTION The P4C1024 is a 1,048,576-bit high-speed CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. Access times of 15 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1024 is a member of a family of PACE RAMTM products offering fast access times. The P4C1024 device provides asynchronous operations with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (P300, C10, C11), SOJ (J300, J400, CJ1), SOLDER SEAL FLATPACK (FS-3) SIMILAR LCC (L6) Document # SRAM124 REV A Revised October 2005 P4C1024 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value -0.5 to +7 -0.5 to VCC +0.5 -55 to +125 Unit V Symbol TBIAS TSTG PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -55 to +125 -65 to +150 1.0 50 Unit C C W mA VTERM TA V C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Military Ambient Temperature GND 0V 0V 0V VCC 5.0V 10% 5.0V 10% 5.0V 10% CAPACITANCES(4) VCC = 5.0V, TA = 25C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 8 10 pF pF -55C to +125C -40C to +85C Industrial Commercial 0C to +70C Output Capacitance VOUT = 0V DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VIH VIL VHC VLC VCD VOL VOH ILI ILO Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage VCC = Min., IIN = -18 mA Output Low Voltage IOL = +8 mA, VCC = Min. (TTL Load) Output High Voltage IOH = -4 mA, VCC = Min. (TTL Load) VCC = Max. Mil. Input Leakage Current VIN = GND to VCC Ind./Com'l. Output Leakage Current VCC = Max., CE = VIH, VOUT = GND to VCC Mil. Ind./Com'l. Test Conditions P4C1024 Min Max 2.2 VCC +0.5 -0.5(3) -0.5(3) 0.8 0.2 -1.2 0.4 2.4 -10 -5 -10 -5 ___ ___ +10 +5 +10 +5 35 30 2.4 -5 n/a -5 n/a ___ ___ +5 n/a +5 n/a 25 n/a P4C1024L Unit Min Max 2.2 VCC +0.5 V -0.5(3) -0.5(3) 0.8 0.2 -1.2 0.4 V V V V V V A A mA VCC -0.2 VCC +0.5 VCC -0.2 VCC +0.5 ISB Standby Power Supply Current (TTL Input Levels) CE1 VIH or Mil. CE2 VIL, Ind./Com'l. VCC= Max, f = Max., Outputs Open CE1 VHC or Mil. CE2 VLC, Ind./Com'l. VCC= Max, f = 0, Outputs Open VIN VLC or VIN VHC ISB1 Standby Power Supply Current (CMOS Input Levels) ___ ___ 25 20 ___ ___ 2 n/a mA Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Document # SRAM124 REV A Page 2 of 14 P4C1024 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial ICC Dynamic Operating Current* Industrial Military -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Unit mA mA mA 190 160 150 145 N/A N/A N/A N/A N/A N/A N/A 175 165 160 155 N/A N/A N/A N/A N/A N/A 150 140 135 130 125 115 110 105 100 *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH DATA RETENTION CHARACTERISTICS (P4C1024L, Military Temperature Only) Symbol VDR ICCDR tCDR tR Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Condition Min 2.0 Typ.* VCC= 2.0V 3.0V 50 200 Max VCC= 2.0V 3.0V 400 600 Unit V A ns CE1 VCC - 0.2V or CE2 0.2V, VIN VCC - 0.2V or VIN 0.2V tRC ns *TA = +25C tRC = Read Cycle Time This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM124 REV A Page 3 of 14 P4C1024 AC ELECTRICAL CHARACTERISTICS--READ CYCLE (VCC = 5V 10%, All Temperature Ranges)(2) Symbol tRC tAA tAC tOH Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 0 7 0 3 -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit 15 15 15 3 20 20 20 3 25 25 25 3 35 35 35 3 45 45 45 3 55 55 55 3 70 70 70 3 85 85 85 3 100 100 100 3 120 120 120 ns ns ns ns tLZ tHZ 3 8 3 9 3 11 3 15 3 20 3 25 3 30 3 35 3 40 3 50 ns ns tOE tOLZ tOHZ tPU 7 0 9 0 9 0 11 0 11 0 15 0 15 0 20 0 20 0 25 0 25 0 30 0 30 0 35 0 35 0 40 0 40 0 50 ns ns 50 ns ns tPD 12 20 20 20 25 30 35 40 45 50 ns TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5) OE Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. Document # SRAM124 REV A Page 4 of 14 P4C1024 TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10) CE Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. Document # SRAM124 REV A Page 5 of 14 P4C1024 AC CHARACTERISTICS--WRITE CYCLE (VCC = 5V 10%, All Temperature Ranges)(2) Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 Unit Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max 20 15 15 0 15 0 8 0 8 3 3 10 3 25 18 20 0 18 0 10 0 11 3 35 22 25 0 22 0 15 0 15 3 45 30 35 0 25 0 20 0 18 3 55 35 45 0 30 0 25 0 20 3 70 45 60 0 40 0 30 0 25 3 85 50 70 0 45 0 35 0 30 3 100 60 85 0 55 0 45 0 40 3 120 75 100 0 70 0 60 0 50 ns ns ns ns ns ns ns ns ns ns Write Cycle Time 15 Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Date Hold Time Write Enable to Output in High Z Output Active from End of Write 12 12 0 12 0 7 0 TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(11) WE Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state. 14. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM124 REV A Page 6 of 14 P4C1024 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(11) CE AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Fig. 1 and 2 TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CE1 CE2 OE WE H X L L L X L H H H X X H L X X X H H L I/O Power High Z Standby High Z Standby High Z DOUT High Z Active Active Active Figure 1. Output Load * including scope and test fixture. Figure 2. Thevenin Equivalent Note: Because of the ultra-high speed of the P4C1024, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long highinductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 resistor must be used in series with DOUT to match 166 (Thevenin Resistance). Document # SRAM124 REV A Page 7 of 14 P4C1024 ORDERING INFORMATION SELECTION GUIDE The P4C1024 is available in the following temperature, speed and package options. Te m pe ra ture Ra nge Commercial Pa cka ge Plastic DIP (300 mil) Plastic SOJ (300 mil) Plastic SOJ (400 mil) Industrial Plastic DIP (300 mil) Plastic SOJ (300 mil) Plastic SOJ (400 mil) Military Temperature Ceramic DIP (600 mil) Ceramic DIP (400 mil) Solder Seal Flatpack LCC (450 x 550 mil) Ceramic SOJ Military Processed* Ceramic DIP (600 mil) Ceramic DIP (400 mil) Solder Seal Flatpack LCC (450 x 550 mil) Ceramic SOJ Spe e d 15 -15P3C -15J3C -15J4C N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 20 -20P3C -20J3C -20J4C -20P3I -20J3I -20J4I -20C6M -20C4M -20FSM -20LM -20CJM -20C6MB -20C4MB -20FSMB -20LMB -20CJMB 25 -25P3C -25J3C -25J4C -25P3I -25J3I -25J4I -25C6M -25C4M -25FSM -25LM -25CJM -25C6MB -25C4MB -25FSMB -25LMB -25CJMB 35 -35P3C -35J3C -35J4C -35P3I -35J3I -35J4I -35C6M -35C4M -35FSM -35LM -35CJM -35C6MB -35C4MB -35FSMB -35LMB -35CJMB 45 N/A N/A N/A -45P3I -45J3I -45J4I -45C6M -45C4M -45FSM -45LM -45CJM -45C6MB -45C4MB -45FSMB -45LMB -45CJMB * Military temperature range with MIL-STD-883, Class B compliance. N/A = Not Available Document # SRAM124 REV A Page 8 of 14 P4C1024 Temperature Range Commercial Package Plastic DIP (300 mil) Plastic SOJ (300 mil) Plastic SOJ (400 mil) Speed 55 N/A N/A N/A N/A N/A N/A -55C6M -55C4M -55FSM -55LM -55CJM -55C6MB -55C4MB -55FSMB -55LMB -55CJMB 70 N/A N/A N/A N/A N/A N/A -70C6M -70C4M -70FSM -70LM -70CJM -70C6MB -70C4MB -70FSMB -70LMB -70CJMB 85 N/A N/A N/A N/A N/A N/A -85C6M -85C4M -85FSM -85LM -85CJM -85C6MB -85C4MB -85FSMB -85LMB -85CJMB 100 N/A N/A N/A N/A N/A N/A -100C6M -100C4M -100FSM -100LM -100CJM -100C6MB -100C4MB -100FSMB -100LMB -100CJMB 120 N/A N/A N/A N/A N/A N/A -120C6M -120C4M -120FSM -120LM -120CJM -120C6MB -120C4MB -120FSMB -120LMB -120CJMB Industrial Plastic DIP (300 mil) Plastic SOJ (300 mil) Plastic SOJ (400 mil) Military Temperature Ceramic DIP (600 mil) Ceramic DIP (400 mil) Solder Seal Flatpack LCC (450 x 550 mil) Ceramic SOJ Military Processed* Ceramic DIP (600 mil) Ceramic DIP (400 mil) Solder Seal Flatpack LCC (450 x 550 mil) Ceramic SOJ * Military temperature range with MIL-STD-883, Class B compliance. N/A = Not Available Document # SRAM124 REV A Page 9 of 14 P4C1024 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J300 32 (300 mil) Min Max 0.128 0.148 0.082 0.016 0.020 0.007 0.010 0.820 0.830 0.050 BSC 0.335 BSC 0.295 0.305 0.267 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE (300 mil) Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q J400 32 (400 mil) Min Max 0.128 0.148 0.082 0.015 0.020 0.007 0.013 0.820 0.830 0.050 BSC 0.435 0.445 0.395 0.405 0.370 BSC 0.025 - SOJ SMALL OUTLINE IC PACKAGE (400 mil) Document # SRAM124 REV A Page 10 of 14 P4C1024 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P300 32 (300 mil) Min Max 0.200 0.015 0.014 0.022 0.048 0.054 0.008 0.014 1.580 1.620 0.270 0.300 0.300 0.310 0.100 BSC 0.320 0.390 0.120 0.140 0 15 PLASTIC DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b c D E E1 E2 E3 e L Q S S1 M N FS-3 32 Min Max 0.097 0.125 0.015 0.019 0.003 0.009 0.830 0.400 0.420 0.450 0.180 0.030 0.050 BSC 0.250 0.370 0.020 0.045 0.045 0.000 0.0015 32 SOLDER SEAL FLAT PACKAGE Document # SRAM124 REV A Page 11 of 14 P4C1024 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C10 32 (600 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.680 0.510 0.620 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - SIDEBRAZED DUAL IN-LINE PACKAGE (600 mil) Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C11 32 (400 mil) Min Max 0.232 0.014 0.023 0.038 0.065 0.008 0.018 1.700 0.350 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - SIDEBRAZED DUAL IN-LINE PACKAGE (400 mil) Document # SRAM124 REV A Page 12 of 14 P4C1024 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE L6 32 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.442 0.458 0.300 BSC 0.150 BSC 0.458 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 7 9 RECTANGULAR LEADLESS CHIP CARRIER Pkg # # Pins Symbol A A1 A2 B B1 B2 B3 D D1 E E1 E2 e e1 e2 j S S1 CJ1 32 Min Max 0.120 0.165 0.088 0.120 0.070 REF 0.010 REF 0.030R TYP 0.020 REF 0.025 0.045 0.816 0.838 0.750 REF 0.419 0.431 0.430 0.445 0.360 0.380 0.050 BSC 0.038 TYP 0.005 0.005 TYP 0.030 0.040 0.020 TYP CERAMIC SOJ SMALL OUTLINE IC PACKAGE Document # SRAM124 REV A Page 13 of 14 P4C1024 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A ISSUE DATE 1997 Oct-05 SRAM124 P4C1024 HIGH SPEED 128K x 8 DUAL CHIP ENABLE CMOS STATIC RAM ORIG. OF CHANGE DAB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Document # SRAM124 REV A Page 14 of 14 |
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