View ML87V3104_1280503.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

OKI Semiconductor ML87V3104
LCD Display Controller with Embedded Display Memory
FEDL87V3104-03
Issue Date: Nov. 28, 2003
GENERAL DESCRIPTION
The ML87V3104 is an LCD graphic display controller intended for use in medium to small-sized equipment having such as QVGA grade medium-sized LCD panels, such as PDA or portable information terminals. Since this LSI device has an internal display memory, use of this device reduces the component count. It is possible to set an easy to use configuration of the display memory size, such as 1024 x 1024 dots x 4 bits or 2048 x 256 dots x 8 bits, depending on the application at hand, and it is possible to access the image data without having to be concerned about address conversion. The area specified in the display memory can be output on the display. The display data and the control information can be set by the host CPU.
FEATURES
* Display memory: * Display size: * Number of display colors: * Color palette: * Output data: * Display functions: Horizontal 4096 dots, maximum, vertical 4096 dots, maximum (with restrictions) Horizontal 1024 dots, maximum, vertical 1024 dots, maximum (with restrictions) suitable for QVGA (320 x 240) or HVGA (640 x 240, 480 x 320) 16/256 Colors out of 4096 colors (pseudo-colors) 4096/65536 Colors (direct colors) 256 Colors x 12 bits (R4, G4, B4) STN 4/8 bits parallel, TFT 12 bits (R4, G4, B4) / 16 bits (R5, G6, B5) Scroll (in units of 16 horizontal pixels and 1 vertical line), Sub-screen display (any position, pseudo-color mode only) Hardware cursor (16 x 16 x 2 bits) Duty 1/64 to 1/1024, up to 16-gray levels, Programmable AC driving signal (Toggle period can be specified.) (68k- Series, 80-Series, RISCs of different companies, etc.) 4M bit DRAM 15 MHz, maximum 3.3 V 0.3 V 100-Pin plastic TQFP (TQFP100-P-1414-0.50-K)
* LCD Drive signals: * Host CPU: 8/16 bits * Embedded memory: * Operating frequency: * Power supply voltages: * Package:
1/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
BLOCK DIAGRAM
Display Memory (4M bit DRAM)
ADRS C CPU Bus (8/16bits) P U I/F Config. Reg. Conv.
Memory Controller
Color Palette
Output Format
to LCD
Cursor Gen. Timing Gen. LCD Interface LCD control signals
APPLICATION CIRCUIT
The following is an example of application to a handy terminal for POS systems.
Key 16-bit MCU RAM ROM PC Card Barcode Serial I/F Scanner
System BUS ML87V3104 QVGA Color STN LCD module Touch Panel Peripheral Interface
2/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
PIN CONFIGURATION (TOP VIEW)
100-pin Plastic TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
D00 D01 D02 D03 VDDI D04 D05 D06 D07 (NC) (NC) (NC) VSS AD00 AD01 VDDI AD02 AD03 AD04 AD05 VSS AD06 AD07 AD08 AD09
(NC) CSN REN WEN BSN VSS DSN BSYN REGS BCLK VDDI XOSCI (NC) XOSCO VSS RESETN (NC) HMOD3 HMOD2 VDDI HMOD1 HMOD0 TEST1 TEST0 (NC)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TQFP100-P-1414-0.50-K
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
(NC) AD10 AD11 (NC) AD12 AD13 (NC) VDDI AD14 AD15 A16 A17 VSS A18 VDDI PORT1 PORT0 (TOUT) (NC) VSS DDD0 DDD1 DDD2 DDD3 (NC)
NC: No-connection pins These pins should be left open during normal use. Please supply the same voltage to all the "VDDI" pins, also "VDDO" pins.
(NC) DISP DF FRP LCP VSS DDA3 DDA2 DDA1 DDA0 VDDO CPS CP (NC) VSS (NC) DDB3 DDB2 DDB1 DDB0 VDDO DDC3 DDC2 DDC1 DDC0
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
PIN DESCRIPTIONS
Table P1. List of pins and their descriptions Pin Symbol I/O Type
27 28 29 30 32-35 37 38 42-45 47-50 52-55 59, 60 62, 64, 65 66, 67, 70, 71 73, 74, 76-79 81-84, 86, 87 92-95, 97-100 2 3 4 5 7 8 10 9 12 14 16 18, 19, 21, 22 23, 24 58 11, 20, 61, 68, 85, 96 36, 46 6, 15, 31, 40, 56, 63, 80, 88 DISP DF FRP LCP DDA3 - 0 CPS CP DDB3 - 0 DDC3 - 0 DDD3 - 0 PORT0, 1 A18 - 16 AD15 - 00 O O O O O O O O O O I/O I I/O 4mA drive 4mA drive 4mA drive 4mA drive 4mA drive 3-state 4mA drive 4mA drive 4mA drive 3-state 4mA drive 3-state 4mA drive 3-state LVTTL / 4mA drive LVTTL LVTTL / 4mA drive LVTTL / 4mA drive LVTTL, Schmitt LVTTL, Schmitt LVTTL, Schmitt LVTTL, Schmitt LVTTL, Schmitt 8mA drive 3-state LVTTL, Schmitt LVTTL, Schmitt X'tal oscillation buffer LVTTL LVTTL LVTTL 2mA drive Power Supply Power Supply Power Supply
Description
LCD Display enable LCD AC driving signal pin LCD Frame pulse LCD Line clock pulse LCD Data A LCD Data clock pulse 2 or Data Strobe LCD Data clock pulse LCD Data B LCD Data C LCD Data D General purpose I/O port (input / output direction can be set for each pin) Host address bus Host address/data multiplexed bus
D07 - 00 CSN REN WEN BSN DSN BSYN BCLK REGS XOSCI XOSCO RESETN HMOD3 - 0 TEST1, 0 (TOUT) VDDI VDDO VSS
I/O I I I I I O I I I O I I I O -- -- --
Host data bus Chip select (active "L") Read enable (active "L") Write enable (active "L") Bus start/address strobe (active "L") Data strobe (active "L") Busy/wait (active "L", 3-stated) Bus clock Register select Clock oscillator input (built-in feedback resistor) Clock oscillator output System reset (active "L") Host mode select Test mode select (normally tied to "L") (Test output. Not used.) Power supply for the internal core and I/O Power supply for the LCD interface signal outputs Common ground
4/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
FUNCTIONAL DESCRIPTION
1. Display Memory The address and data configuration of the display memory is specified by making control register settings. When the defined memory size is smaller than the internal DRAM (4M bits), the page mode operation is started automatically, making it possible to specify the display address in units of a page and to access the host CPU (a maximum of 256 pages). Even when the address space of the host CPU bus is smaller than the display memory space, the entire area can be accessed using the page mode. There are limitations on the LCD drive mode depending on the display memory data width. (See Section 3.1.) Note that the LCD control timings must be defined before accessing the display memory. (See Section 3.1.2) * Control registers: IMASZX [#03h: bit 3-0]: IMASZY [#03h: bit 7-4]: IMDBPP [#02h: bit 1-0]: HSTPGA [#3Bh]: Display memory horizontal size (2n) (Table F1.1) Display memory vertical size (2n) (Table F1.1) Number of bits per pixel (Table F1.2) Page number for host access Table F1.1 Display memory size selection
IMASZY 0000 0001 0010 0011 0100 0101 0110 0111 1XXX Vertical size (lines) 64 128 256 512 1024 2048 4096 (Reserved) (Reserved) IMASZX 0000 0001 0010 0011 0100 0101 0110 0111 1XXX Horizontal size (pixels) 64 128 256 512 1024 2048 4096 (Reserved) (Reserved)
Table F1.2 Display memory data width
IMDBPP 00X 010 011 100 Number of bits (bits / pixel) -- 4 8 16*1 Pseudo color Direct color Number of simultaneously displayed colors Color mode -- 16/4096 256/4096 4096 65536 Monochrome mode -- 16 256 -- -- Applicable LCD type -- STN/TFT STN TFT
*1: Correspondence between the display memory data and the color data in the 16BPP mode.
7
Upper byte
(no use)
0
7
Lower byte
0
STN 16 BPP (12)
7
RRRR 3210
0
GGGGBBBB 32103210
7
Upper byte
Lower byte
0
TFT 16 BPP
RRRRRGGG 54321543
GGGBBBBB 21054321
5/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
Example 1:
When IMASZX = "100", IMASZY = "100", and IMDBPP = "010": The memory size is 1024 horizontal pixels, 1024 vertical lines and 4 bits/pixel. 1024 x 1024 x 4 = 4M bits The memory can be accessed using 19 host address bits (10 horizontal bits plus 9 vertical bits) with the host data width being 8 bits (in 2-pixel packed format).
Example 2:
When IMASZX = "010", IMASZY = "010", and IMDBPP = "011": The memory size is 256 horizontal pixels, 256 vertical lines with 8 bits/pixel and 8 pages. 256 x 256 x 8 = 512K bits (< 4M bits) 4M bits/512 K bits = 8 pages The memory can be accessed using 16 host address bits (8 horizontal bits plus 8 vertical bits) and the lower 3 bits of the page register, with the host data width being 8 bits (in 2-pixel packed format).
6/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2. Display Control 2.1 Display section The display section of the ML87V3104 is composed of the display memory, the cursor and cursor color registers, the color palette, the FRC table, and output format conversion section. (Fig. F2.1) The color display in the case of 4 bits/pixel and 8 bits/pixel can be made using, respectively, 16 and 256 colors out of 4096 colors. (Pseudo-color mode) Further, in the STN mode, the output is made after conversion into the gradation expression data in the FRC method. In the case of 16 bits/pixel, the output is made directly without passing through the color palette. (Direct color mode) In the STN mode, out of the total 16 bits, only 4 bits each of RGB (12 bits in all) will be valid and display 4096 colors can be made. In the TFT mode, the 16 bits are divided into 5 bits of R, 6 bits of G, and 5 bits of B, making it possible to display 65536 colors. Even the direct mode can also be used in the case of 8 bits/pixel.
Display memory 512 x 8b
8/16
4
1
SEL
4
DDA3-0 DDB3-0 DDC3-0 DDD3-0
8
SEL
Color palette
256 x 12b
4
FRC Table
16 x 16b
Output 1 format conversion
1
4
SEL
Cursor pattern register
16 x 16 x 2b
2
Color register
3 x 8b Cursor display control
4 8
4
SEL
4 8/16
Fig. 2.1 The display section
7/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2.2 Display screen composition The display screen consists of the main screen with a size equal to the display size of the LCD panel, and a sub-screen displayed in a smaller area within the main screen. (Fig. F2.2.1) In the case of a color LCD panel, one set of the three colors (RGB) is considered as one pixel. (Fig. F2.2.2)
(1)
(6)
Main screen Sub-screen
(2)
(4)
(5)
(3)
Fig. F2.2.1 The display screen composition
1 Pixel 1 Line 1 Line 1 Pixel
(a) Monochrome LCD
(b) Color LCD
Fig. F2.2.2 The LCD panel dot composition * Control registers:
(1) MSCSZH (2) MSCSZV (3) SSCSZH (4) SSCSZV (5) SDPOSH (6) SDPOSV [#21h, #20h]: Horizontal display size 1024 pixels [#23h, #22h]: Vertical display size 1024 lines [#25h, #24h]: Sub-screen horizontal display size < (1) [#27h, #26h]: Sub-screen vertical display size < (2) [#29h, #28h]: Sub-screen horizontal display position < (1) [#2Bh, #2Ah]: Sub-screen vertical display position < (2)
8/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2.3 Display functions 2.3.1 Main screen, sub-screen, and scrolling The main screen and the sub-screen in the display screen (see Fig. F2.2.1) can respectively display the areas specified in the display memory. (Fig. F2.3.1)
Origin (2) (1)
Display memory
LCD Screen (4)
Main screen Sub-screen
(3)
Fig. F2.3.1 The display screen composition * Control registers:
(1) MDPSTX [#31h, #30h]: (2) MDPSTY [#33h, #32h]: (3) SDPSTX [#35h, #34h]: (4) SDPSTY [#37h, #36h]: (5) MDPPGA [#38h]: (6) SDPPGA [#39h]: Starting horizontal address of reading out the main screen display area Starting vertical address of reading out the main screen display area Starting horizontal address of reading out the sub-screen display area Starting vertical address of reading out the sub-screen display area Page number of the main screen display area Page number of the sub-screen display area
The starting addresses of reading out the display memory can be specified for the separate main screen and sub-screen in units of 16 horizontal pixels and one vertical line. In addition, by successively over-writing by the host CPU, it is possible to realize scrolling of the display screen. The sub-screen is always displayed by superimposing on the main screen.
9/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2.3.2 Screen mode It is possible to select the method of placing the LCD panel by setting the screen mode. It is possible to specify the landscape (horizontal screen) or portrait (vertical screen), and to specify the left/right and top/bottom reversal of the displayed image. * Control register:
SCRMOD [#02h; bit6-4]: Screen mode
Table F2.3.2 The screen modes
SCRMOD Screen mode
000
Normal
001
Landscape (longer horizontal side)
Left/right flip
010
Top/bottom flip
011
Left/right and top/bottom flip
100
Normal
101
Portrait (longer vertical side)
Top/bottom flip
110
Left/right flip
111
Left/right and top/bottom flip
: LCD data output scanning direction
Note: The screen mode definition has a difference between Landscape and Portrait.
10/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2.4 Cursor 2.4.1 Cursor display It is possible to display the cursor on the screen. It is also possible to select whether or not to display the cursor, and when cursor display is selected, it is always displayed in the front-most screen. This LSI has a pattern register for the display of a cursor with a size of 16 pixels x 16 lines x 2 bits in which it is possible to write the cursor shape. Displaying the cursor has no effect on the display memory. The cursor display color can be specified by the contents of the 2-bit (4-value) cursor pattern register for each pixel. One of the four values is "transparent", and that pixel is not displayed when this value is specified. The other 3 values respectively correspond to the 8-bit cursor color registers (CSCOL1 to CSCOL3), and the specified value is converted to the actually displayed pixel data from the color palette common to the display memory output.
2.4.2 Cursor display position The cursor display position is specified in terms of the position in the screen of the cursor origin (the top left corner of the cursor).
LCD screen (2) (1) Cursor
Fig. F2.4.2 The cursor position * Control registers:
(1) CSPOSH [#2Dh, #2Ch]: (2) CSPOSV [#2Fh, #2Eh]: (3) CSDENB [#2Fh; bit7]: Cursor display horizontal position Cursor display vertical position Cursor display enable (`0': disable, `1': enable)
11/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2.4.3 Cursor color register The display data of the cursor is determined corresponding to the cursor data by the contents of the 8-bit cursor color register. The number of valid bits depends on the number of bits per pixel (IMDBPP).
8 Display memory data 8 Cursor color register 1 Cursor color register 2 Cursor color register 3 2 Cursor data 8 8 11 01 SEL 10 To color palette 00
Fig. F2.4.3 The cursor color register * Control registers:
CSCOL1 CSCOL2 [#1Dh]: [#1Eh]: Cursor color register 1 Cursor color register 2 Cursor color register 3
CSCOL3 [#1Fh]: Valid bits: Bits 3 to 0 for 4BPP Bits 7 to 0 for 8BPP
12/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2.4.4 Cursor pattern register The cursor pattern (shape) can be prepared by writing data in the 16 x 16 x 2-bit cursor pattern register. The data is accessed in the 4-pixel packed format. (Fig. F2.4.4)
X=0 1 2 3 4 5 6 7 8 Y=0 16 pixels Y=1 Y=2
2 bits
16
lines
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Cursor
Register data
X = 4n + 0 X = 4n + 1 X = 4n + 2 X = 4n + 3 bit1 bit0 bit1 bit0 bit1 bit0 bit1 bit0
Fig. F2.4.4 The cursor pattern register * Control registers:
CSPTAY [#18h; bit5-2]: CSPTAX [#18h; bit1-0]: CSPTD0 [#19h; bit7-6]: CSPTD1 [#19h; bit5-4]: CSPTD2 [#19h; bit3-2]: CSPTD3 [#19h; bit1-0]: Cursor pattern register address Y (4 bits) Cursor pattern register address X (higher 2 bits) Cursor pattern register data (X address = 4n+0) Cursor pattern register data (X address = 4n+1) Cursor pattern register data (X address = 4n+2) Cursor pattern register data (X address = 4n+3)
13/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2.5 Color palette The data written in the display memory is converted into the actual color data output to the LCD panel by the color palette. (Pseudo-color mode) The color palette contains 4-bit x 3-color (R, G, B) (= 12 bits) registers corresponding to each of the 256 entries addresses. The correspondence between the display memory data and the color palette entry is established as shown in Table F2.5 depending on the data width of the display memory. The color palette cannot be used in the direct color mode (16BPP). Table F2.5 The display memory data vs. the color palette entries
Display memory data 8 BPP 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 FC FD FE FF
*1
4 BPP 0 1 2 3 4 5 6 7 8 9 A B C D E F -- -- -- -- -- -- -- -- --
Color palette entry 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 FC FD FE FF
*1: A hyphen "--" indicates that the data value is not used. * Control registers:
COLPTA [#10h]: COLPDR [#11h; bit7-4]: COLPDG [#12h; bit7-4]: COLPDB [#13h; bit7-4]: Color palette entry address Color palette data R Color palette data G Color palette data B
14/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
2.6 Gray level control In the case of an STN type LCD panel, the FRC (Frame Rate Control) method is used for the multiple gray level display. By controlling the blinking pattern of the dot, it is possible to express intermediate gray levels in a quasi manner. Taking 16 frames as one period, it is possible to express up to 16 gray levels. The dot blinking pattern is set in the 16-word x 16-bit FRC table. The 4-bit table address corresponds to the gray levels from 0 to 15. The 16-bit table data expresses the dot blinking patterns corresponding to the different gray levels, and the dot display is switched for each frame sequentially from the MSB to the LSB, with the operation being repeated at a period of 16 frames. In the case of a color STN panel, the FRC pattern is the same for all colors. * Control registers:
FRCTBA [#15h; bit3-0]: FRCTBD [#17h, #16h]: FRC table address FRC table data
Table F2.6 The FRC table (initial value)
Table address (gradation) 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 FRC table (displayed in the sequence 15, 14, ..., 1, 0) 14 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 13 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 12 0 0 0 0 1 0 0 0 1 1 1 0 1 1 1 1 11 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1 10 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 9 0 1 0 0 0 0 0 1 0 1 1 1 1 1 0 1 8 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 7 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 6 0 0 0 1 0 0 1 0 1 0 1 1 0 1 1 1 5 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 4 0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 1 3 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 2 0 0 1 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1
Note:
This table shows the initial value set after a reset, and is not one assuming any specific LCD panel specifications. Set the values in this table to suit the characteristics of the LCD panel being used.
15/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3. LCD Interface 3.1 LCD driving method 3.1.1 LCD driving mode The ML87V3104 is suitable for various types of LCD panels, and allows the LCD driving mode to be selected by setting the control registers. The number of valid data bits in the LCD interface varies depending on the driving mode. The output data signals that are not used will be maintained in the high-impedance state. Further, there are some restrictions on the selection of the display memory data width (bits per pixel) depending on the driving mode. (Table F3.1) * Control registers:
LCDMOD [#00h; bit7-4]: LCDDAT [#00h; bit3-0]: LCD panel operation mode LCD panel interface data width
Table F3.1 LCD driving modes
LCDMOD LCDDAT LCD driving mode 4 bits Pseudo-color 8 bits 4 bits, 2 phase 4 bits Direct color 8 bits 4 bits, 2 phase 4 bits Monochrome STN 8 bits 4 bits, 2 phase Pseudo-color Color TFT Direct color 12 bits 16 bits Display memory BPP DDA DDB DDC DDD O O O O O O O O O O O Z O Z Z O Z Z O Z O O Z Z Z Z Z Z Z Z Z O O Z Z Z Z Z Z Z Z Z Z O Output data
000 0000 010 100
Color STN
4, 8
000 0001 010 100 000 0100 010 100 1000 1001 000 001
16(12)
4
4, 8 16
BPP: bits per pixel `O': 4 bits are active. `Z': 4 bits are in a high impedance state.
16/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.1.2 LCD control timing The LCD control timing is determined by the LCP (line clock pulse) signal and the FRP (frame pulse) signal. It is also possible to set the polarities of these pulses individually.
(1)
LCP FRP (5) (6) (7) (2) (3)
Active display area
Fig. F3.1.2 LCD drive timing * Control registers:
(1) LCPCYC [#05h, #04h]: (LCP signal period - 1) In units of a CP clock in the STN color 4-bit mode In units of 2 CP clocks in the STN color 8-bit mode or 4-bit 2-phase mode In units of 4 CP clocks in the STN monochrome 4-bit mode In units of 8 CP clocks in the STN monochrome 8-bit mode or 4-bit 2-phase mode In units of a CP clock in the TFT color mode (2) LCPSTA [#07h, #06h]: (4) LCPPOL [#05h; bit7]: (5) FRPCYC [#09h, #08h]: LCP start timing, in units of a CP clock LCP pulse polarity, `0': Positive, `1': Negative FRP signal period, in units of a line, (5) (6)+2 (3) LCPWID [#07h; bit7-4]: (LCP pulse width - 1), in units of 4 x CP clocks
(6) FRPSTA [#0Bh, #0Ah]: FRP start timing, in units of a line (7) FRPWID [#0Bh; bit7-4]: (FRP pulse width - 1), in units of a line (8) FRPPOL [#09h; bit7]: FRP pulse polarity, `0': Positive, `1': Negative
Note: The internal memory gets started by setting above registers. These must be set at first after the power up or the internal memory cannot be accessed.
17/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.1.3 LCD AC driving signal DF The toggle period of the DF signal (AC driving signal) can be specified to be either one frame period or the period of the set number of lines. * Control registers:
DFFALT DFLALT [#0Dh; bit7]: [#0Dh, #0Ch]: DFFALT 0 1 DF signal toggle mode (DF signal toggle period - 1), in units of a line DF toggle mode Reversal at one frame periods Reversal at periods of (DFLALT+1) line
3.1.4 LCD data clocks CP, CPS It is possible to select whether or not to output the CP and CPS clock pulses during the invalid period (blanking period) of the LCD display data. In most cases, the appropriate setting is CPBLK = `1' for an STN LCD and CPBLK = `0' for a TFT LCD. * Control register:
CPBLK [#01h; bit7]: CPBLK 0 1 Control of CP and CPS clock output during blanking CP and CPS clock output during blanking Active Clock pulses are stopped
18/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.1.5 LCD data output control Three types of control registers are provided in this LSI device for control of the LCD data output. The register COLORD can be used for changing R, G, B sequence in a color LCD. This is also valid in the frame sequential color mode. The register DPDMOD is used for inverting the bits of the output data or for making the data all-zero or all-one. The register DPMENB can be used for stopping the display memory readout operation itself. At this time, even the LCD driving signals will be stopped. Further, it is also possible to specify the level of the DISP signal output. The register REFENB controls the refresh operation of the display memory (embedded DRAM). If the refresh operation is stopped, the entire contents of the display memory will be lost. Along with the register DPMENB, this register is useful for achieving low power consumption when no display is being made. * Control registers:
COLORD [#01h; bit7]: 000 001 010 101 110 111 DPDMOD [#01h; bit3-2]: LCD data display mode DPDMOD 00 01 10 11 DPMENB [#01h; bit1-0]: 00 01 10 11 REFENB LCD data display mode Normal Reverse All `0' All `1' Display memory readout control, definition of DISP signal output Display memory readout Memory readout stopped LCD drive stopped Memory readout operating LCD drive operating DISP signal DISP = `L' DISP = `H' DISP = `L' DISP = `H' Color arrangement sequence of the color LCD panel Color arrangement sequence R, G, B, R, G, B, * * * G, B, R, G, B, R, * * * B, R, G, B, R, G, * * * R, B, G, R, B, G, * * * G, R, B, G, R, B, * * * B, G, R, B, G, R, * * * COLORD
DPMENB
[#02h, bit7, 3]: Embedded DRAM refresh operation enable REFENB 1 0 1 0 X 0 1 DRAM refresh operation Fully stopped (sleep mode)*1 Operation only during blanking Always operating
*1: The contents of the display memory will be lost in the sleep mode.
19/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.1.6 Calculation of the display frame rate The frame rate (the frame frequency) is determined by the periods of the LCD panel driving signals LCP and FRP, the clock frequency, and the LCD driving mode.
Frame rate = FXOSC/{(FRPCYC) x (LCPCYC) x (TPX)} Where, FXOSC : External input clock frequency, FRPCYC : Period (in units of a line) of the FRP (frame pulse) signal, LCPCYC : Period (in units of a pixel) of the LCP (line pulse) signal, TPX : TPX = 3/4 in the case of a color STN type LCD and TPX = 1 in all other cases.
Example:
What is the input clock frequency for making the frame rate equal to 150 Hz in the case of a color STN QVGA (320 x 240) type LCD panel?
FRPCYC = 240 + 2 = 242 LCPCYC = 320 + 40 = 360 FXOSC = 150 x 242 x 360 x 3/4 = 9.8 MHz
20/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.2 LCD data output format The valid output data signal and the data format are determined depending on the LCD driving mode.
3.2.1 Color STN, 4-bit mode
LCD data output sequence DDA3 DDA2 DDA1 DDA0
R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5
LCD panel segment arrangement
RGBRGBRGBRGB 000111222333
Fig. F3.2.1 Color STN, 4-bit mode
3.2.2 Color STN, 8-bit mode
LCD data output sequence DDA3 DDA2 DDA1 DDA0 DDB3 DDB2 DDB1 DDB0
R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5
LCD panel segment arrangement RGBRGBRGBRGB 000111222333
Fig. F3.2.2 Color STN, 8-bit mode
21/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.2.3 Color STN, 4-bit 2-phase mode
LCD data output sequence DDA3 DDA2 DDA1 DDA0
R0 B0 G1 R2 G0 R1 B1 G2 B2 G3 R4 B4 R3 B3 G4 R5
LCD panel segment arrangement RGB RGB RGB RGB 000111222333
Fig. F3.2.3 Color STN, 4-bit, 2-phase mode
22/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.2.4 Monochrome STN, 4-bit mode
LCD data output sequence DDA3 DDA2 DDA1 DDA0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LCD panel segment arrangement 0 1 2 3 4 5 6 7 8 9
Fig. F3.2.4 Monochrome STN, 4-bit mode
3.2.5 Monochrome STN, 8-bit mode
LCD data output sequence DDA3 DDA2 DDA1 DDA0 DDB3 DDB2 DDB1 DDB0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LCD panel segment arrangement 0 1 2 3 4 5 6 7 8 9
Fig. F3.2.5 Monochrome STN, 8-bit mode
23/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.2.6 Monochrome STN, 4-bit 2-phase mode
LCD data output sequence DDA3 DDA2 DDA1 DDA0 0 2 4 6 1 3 5 7 8 10 12 14 9 11 13 15 LCD panel segment arrangement 0 1 2 3 4 5 6 7 8 9
Fig. F3.2.6 Monochrome STN, 4-bit, 2-phase mode
24/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
3.2.7 Color TFT, 12-bit mode
LCD data output sequence
DDA 3-0 (R) DDB3-0 (G) DDC3-0 (B)
R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3
LCD panel segment arrangement
RGBRGBRGBRGB 000111222333
Fig. F3.2.7 Color TFT, 12-bit mode
3.2.8 Color TFT, 16-bit mode
LCD data output sequence
DDA 3-0 (R) DDB3 DDB2-0 (G) DDC3-1 DDC0 DDD3-0
R0 R1 R2 R3
LCD panel segment arrangement
RGBRGBRGBRGB 000111222333
G0
G1
G2
G3
(B) B0
B1
B2
B3
Fig. F3.2.8 Color TFT, 16-bit mode
25/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
4. General Purpose I/O Port The ML87V3104 has two general purpose ports (PORT1, PORT0). It is possible to specify the input/output directions independently for these ports. The output level of the output port can be set by writing data in the data register. Further, the input level of the input port can be read out from the data register. When set as an input port, writing to the data register will not be valid. * Control registers:
PTDDIR [#0Eh; bit1-0]: General purpose port input/output mode (`0': output, `1': input) General purpose port data register (`0': L level, `1': H level) PTDREG [#0Fh; bit1-0]:
Bit 1 corresponds to PORT1 and bit 0 corresponds to PORT0. PTDDIR[n] 0 1 Output Input PORTn PTDREG[n] PORTn PTDREG[n] PORTn
PTDDIR[0] PTDREG[0]
Host Data Pin 59
PORT0
PTDDIR[1] PTDREG[1]
Host Data Pin 60
PORT1
Fig. F4.1 General purpose ports
26/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
5. Host Interface 5.1 Host interface bus mode selection The host interface bus can be selected to suit the external bus modes of different types of CPUs by setting the pins HMOD3 to HMOD0. Table F5.1 Host interface bus mode
HMOD [3:0] 0000 Bus type Address/ data bus Bus control CSN, WEN, REN, Busy AS, WEN, REN, Busy BSN, WEN, REN, Separate A[18:00] 0011 -- D[07:00] (Reserved) BSN, RWN, DSN, ACK BSN, RWN, DSN, Busy (Reserved) Hitachi SH-1,2, 1000 B0 Multiplexed A[18:16] 1001 101X 11XX B1 -- (Reserved) -- -- AD[15:00] AS, WEN, REN, Busy ASN, WEN, REN, Busy NEC V850, 78K/IV Mitsubishi M16C Oki MSM66K, 80C51 Fujitsu F2MC-16L, Toshiba TLCS-900 Toshiba TX19, Motorola MCF5206, MPC801/850, M68K Mitsubishi M32R, NEC V830, Intel SA-110 -- ACK Applicable CPUs*1 Hitachi SH-1,2, H8S, Fujitsu F2MC-16F, FR30 Toshiba TLCS-900/H2 Hitachi SH-4 Hitachi SH-3, Motorola MCF5204 Toshiba TX39 --
A0
0001
A1
0010
A2
0100
A4
0101 011X
A5 --
*1: The types of CPUs listed here are only for reference. Please examine well about the specifications of the host interface signals and the timings of the MCU being used, and then select the host mode.
27/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
5.1.1 Bus control signals The assignment of the bus control signals to the input/output pins is determined by the host interface bus mode. Table F5.5.1 Bus control signals
Bus type Pin name A0 A18-16 AD15-00 D07-00 REGS CSN REN WEN BSN DSN BSYN BCLK REGS: CSN: REN: WEN: WEHN: WELN: RWN: BSN: ASN: DSN: BSYN: ACK: BCLK: A18-16 A15-00 D07-00 REGS CSN REN WEN -- -- BSYN BCLK A1 A18-16 A15-00 D07-00 REGS CSN REN WEN BS -- BSYN BCLK A2 A18-16 A15-00 D07-00 REGS CSN REN WEN BSN -- ACK BCLK A4 A18-16 A15-00 D07-00 REGS CSN RWN -- BSN -- ACK BCLK A5 A18-16 A15-00 D07-00 REGS CSN RWN -- BSN -- BSYN BCLK B0 A18-16 AD15-00 -- REGS CSN REN WELN ASN WEHN BSYN BCLK B1 A18-16 AD15-00 -- REGS CSN REN WELN AS WEHN BSYN BCLK
Memory/register address space selection; `L': memory, `H': register Chip select (Active `L') Read enable (Active `L') Write enable (Active `L') Higher byte write enable (Active `L') Lower byte write enable (Active `L') Read/write selection; `L': write, `H': read Bus start (Active `L') Address strobe (Active `L') Data strobe (Active `L') Bus busy or wait (Active `L') Data acknowledge (Active `L') Bus clock
28/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
5.1.2 Bus interface timings [Type A0 Write]
BCLK CSN REGS A18-00 WEN D7-0
(write) (z)
REG
MEM
BSYN
[Type A0 Read]
BCLK CSN REGS A18-00 REN D7-0
(read) (z)
REG
MEM
BSYN
29/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[Type A1 Write]
BCLK CSN BS REGS A18-00 WEN D7-0
(write) (z) REG MEM
BSYN
[Type A1 Read]
BCLK CSN BS REGS A18-00 REN D7-0
(read) (z) REG MEM
BSYN
30/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[Type A2 Write]
BCLK CSN BSN REGS A18-00 WEN D7-0
(write) (z) REG MEM
ACK
[Type A2 Read]
BCLK CSN BSN REGS A18-00 REN D7-0
(read) (z) REG MEM
ACK
31/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[Type A4 Write]
BCLK CSN BSN REGS A18-00 RWN D7-0
(write) (z) REG MEM
ACK
[Type A4 Read]
BCLK CSN BSN REGS A18-00 RWN D7-0
(read) (z) REG MEM
ACK
32/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[Type A5 Write]
BCLK CSN BSN REGS A18-00 RWN D7-0
(write) (z) REG MEM
BSYN
[Type A5 Read]
BCLK CSN BSN REGS A18-00 RWN D7-0
(read) (z) REG MEM
BSYN
33/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[Type B0 Write]
BCLK CSN ASN REGS A18-16 WEHN WELN AD15-0 BSYN
(z) A D (write) A D (write)
[Type B0 Read]
BCLK CSN ASN REGS A18-16 REN AD15-0 BSYN
(z) A D (read) A D (read)
34/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[Type B1 Write]
BCLK CSN AS REGS A18-16 WEHN WELN AD15-0 BSYN
(z) A D (write) A D (write) MEM
[Type B1 Read]
BCLK CSN AS REGS A18-16 REN AD15-0 BSYN
(z) A D (read) A D (read) MEM
35/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
5.2 Address mapping The ML87V3104 supports a 19-bit byte address for access from the host CPU. The 4M bit display memory and the 32-byte control registers are mapped to this address. When accessing the display memory, the bit assignment of the address is determined by the setting of the memory size. (Fig. F5.2) See the next section for details of the control registers.
Page No. 7 0 18 Host address 0 Host data 7 0
7 4 bits/pixel
0
18
Y 0
0
X 1
7
0
px0 px1 3 03 0 X=2n+0 X=2n+1
Effective page No. (w bits) 7 8 bits/pixel Effective page No. (w bits) 7 16 bits/pixel Effective page No. (w bits) 0 18 0 18
Y address (v bits)
X address ((u-1) bits) 0
2-pixel packed format 7
px 7 0
0
Y 0
X 0
Y address (v bits)
X address (u bits) 0 7
G 2 05 B 1
0 B='0'
Y 0
XB 0
R G B='1' Y address X address Byte 15 3 (u bits) address 5 (v bits)
The number of total address bits = ( w bits ) + ( v bits ) + ( u bits ) = 19 bits (512K Byte)
Fig. F5.2 Display memory address mapping
36/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
5.3 Control registers 5.3.1 Outline of control registers The initial setting and the operation of the ML87V3104 are controlled by writing data from the host CPU in the control registers. There are 64 single-byte control registers, and in addition, a register space is provided by indirect addressing for the color palette table (256 x 3 bytes), the FRC table (16 x 2 bytes), and the cursor pattern register (64 bytes). (See Table F5.1) The control registers can be accessed by the host CPU by taking the REGS signal input to the `H' level.
18 Host address
15
11
7
5
0
xxxxxxxxxxxxx Control register address (6 bits)
Fig. F5.3 The control register address
37/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
Table F5.1 List of control registers (part 1/2)
Register address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F (Res) CSPTD0 (Reserved) FRCTBD[7:0] FRCTBD[15:8] CSPTAY[3:0] CSPTD1 CSPTD2 (Reserved) (Reserved) (Reserved) CSCOL1[7:0] CSCOL2[7:0] CSCOL3[7:0] CSPTD3
DFF ALT FRP POL LCP POL CP BLK REF ENB1
Register name*1 bit 7 bit 6 bit 5 bit 4 bit 3
(Res)
bit 2
bit 1 LCDDAT
bit 0
Function LCD driving mode Display operation mode Memory operation mode Display memory size LCP (line) period and polarity
LCDMOD COLORD SCRMOD IMASZY
DPDMOD
REF ENB0
DPMENB IMDBPP
IMASZX LCPCYC[7:0]
(Reserved) LCPSTA[7:0] LCPWID
(Res)
LCPCYC[10:8]
LCPSTA[10:8]
LCP start position, pulse width
FRPCYC[7:0] FRP (frame) period and polarity (Reserved) FRPSTA[7:0] FRPWID
(Res)
FRPCYC[10:8] FRP start position, pulse width
FRPSTA[10:8]
DFLALT[7:0] (Reserved) (Reserved) (Reserved) COLPTA[7:0] COLPDR[3:0] COLPDG[3:0] COLPDB[3:0] (Reserved) FRCTBA[3:0] (Reserved) (Reserved) (Reserved) DFLALT[10:8] PTDDIR PTDREG
DF (AC driving signal) toggle period (1 frame or n lines) General purpose port I/O mode General purpose port data register Color palette table address Color palette table data R Color palette table data G Color palette table data B (Reserved) FRC table address FRC table data
CSPTAX[3:2] Cursor pattern register address Cursor pattern register data (Reserved) (Reserved) (Reserved) Cursor color register 1 Cursor color register 2 Cursor color register 3
*1: The entries "(Reserved)" or "(Res)" indicate reserved bits. Writing data to these bits is not valid and the data read out from these bits will be indeterminate.
38/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
Table F5.1 List of control registers (part 2/2)
Register address 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F (Reserved) (Reserved) (Reserved) (Reserved)
CSD ENB SSD ENB
Register name*1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 MSCSZH[7:0] (Reserved) MSCSZV[7:0] (Reserved) SSCSZH[7:0] (Reserved) SSCSZV[7:0] (Reserved) SDPOSH[7:0] (Reserved) SDPOSV[7:0] (Reserved) CSPOSH[7:0] (Reserved) CSPOSV[7:0] (Reserved) MDPSTX[7:0] MDPSTX[11:8] MDPSTY[7:0] MDPSTY[11:8] SDPSTX[7:0] SDPSTX[11:8] SDPSTY[7:0] SDPSTY[11:8] MDPPGA[7:0] SDPPGA[7:0] (Reserved) HSTPGA[7:0] (Reserved) (Reserved) (Reserved) (Reserved) [9:8] [9:8] [9:8] [9:8] [9:8] [9:8] [9:8] [9:8]
Function Main screen horizontal size Main screen vertical size Sub-screen horizontal size Sub-screen vertical size Sub-screen display horizontal position Sub-screen display vertical position Sub-screen display enable Cursor display horizontal position Cursor display vertical position Cursor display enable Display memory horizontal position for main screen Display memory vertical position for main screen Display memory horizontal position for sub-screen Display memory vertical position for sub-screen Display memory page number for main screen Display memory page number for sub-screen (Reserved) Display memory page number for host access
(For testing, cannot be written into)
*1: The entries "(Reserved)" or "(Res)" indicate reserved bits. Writing data to these bits is not valid and the data read out from these bits will be indeterminate.
39/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
5.3.2 Register details In the following descriptions of the different registers, the underlined part indicates the initial value after a reset. [#00h] LCD driving mode
Data bit Register W/R bit 7 3 bit 6 2 W/R LCD panel operation mode selection LCD panel interface data width selection LCDDAT 000 0000 010 100 0010 XXX 000 0100 010 100 0110 1000 1001 11XX `X': Don't care XXX 000 Color TFT 001 XXX (Reserved) 16-bit mode (direct color) -- (Reserved) Monochrome STN (Reserved) Color STN LCD Driving mode 4-bit mode 8-bit mode 4-bit 2-phase mode -- 4-bit mode 8-bit mode 4-bit 2-phase mode -- 12-bit mode (pseudo-color) bit 5 1 bit 4 0 bit 3 (Reserved) -- bit 2 2 bit 1 LCDDAT 1 W/R 0 bit 0
LCDMOD
* LCDMOD[3:0]: * LCDDAT[2:0]:
LCDMOD
40/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#01h] Display operation mode
Data bit Register W/R
* CPBLK:
bit 7 CP BLK W/R
bit 6 2
bit 5 COLORD 1 W/R
bit 4 0
bit 3 1 W/R
bit 2 0
bit 1 1 W/R
bit 0 0
DPDMOD
DPMENB
Control of CP clock output during blanking CPBLK 0 1 CP Output during blanking Active Fixed at CP = `L', CPS = `H'
* COLORD[2:0]:
Color arrangement sequence of color LCD panel Color arrangement sequence R, G, B, R, G, B, * * * G, B, R, G, B, R, * * * B, R, G, B, R, G, * * * (Reserved) (Reserved) R, B, G, R, B, G, * * * G, R, B, G, R, B, * * * B, G, R, B, G, R, * * *
COLORD[2:0] 000 001 010 011 100 101 110 111
* DPDMOD[1:0]:
LCD data display mode LCD data display mode Normal Inverted All `0' All `1'
DPDMOD[1:0] 00 01 10 11
* DPMENB[1:0]:
Display memory readout control, DISP signal output specification Display memory readout Memory readout stopped LCD drive stopped Memory readout operating LCD drive operating DISP signal DISP = `L' DISP = `H' DISP = `L' DISP = `H'
DPMENB[1:0] 00 01 10 11
41/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#02h] Memory operation mode
Data bit Register W/R bit 7 REF ENB1 W/R bit 6 2 bit 5 SCRMOD 1 W/R 0 bit 4 bit 3 REF ENB0 W/R bit 2 2 bit 1 IMDBPP 1 W/R 0 bit 0
* REFENB[1:0]:
Embedded DRAM refreshing operation enable REFENB
1 0 1
0
x
DRAM refreshing (Reserved) Operation only during blanking Always operating
0 1
* SCRMOD[2:0]: Screen mode
SCRMOD[2:0] 000 001 010 011 100 101 110 111 Portrait Landscape Screen mode Normal Left/right flip Top/bottom flip Left/right and top/bottom flips Normal Left/right flip Top/bottom flip Left/right and top/bottom flips
* IMDBPP[1:0]:
Display memory data mode (number of bits per pixel) Number of displayable colors -- 16 colors 256 colors 65,536 colors --
IMDBPP[2:0] 00X 010 011 100 101 110 111
Bits/pixel (Reserved) 4 8 16 Reserved
Note: The pseudo-color mode using the color palette for 4 or 8 bits/pixel, and direct color mode for 16 bits/pixel.
42/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#03h] Display memory size
Data bit Register W/R bit 7 3 bit 6 2 W/R Display memory vertical size (2n) Display memory horizontal size (2n) Vertical size (lines) 64 128 256 512 1024 2048 4096 (Reserved) (Reserved) Horizontal size (pixels) 64 128 256 512 1024 2048 4096 (Reserved) (Reserved) bit 5 1 bit 4 0 bit 3 3 bit 2 2 W/R bit 1 1 bit 0 0
IMASZY
IMASZX
* IMASZY[3:0]: * IMASZX[3:0]:
IMASZY 0000 0001 0010 0011 0100 0101 0110 0111 1XXX
IMASZX 0000 0001 0010 0011 0100 0101 0110 0111 1XXX
43/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#04h] LCP (line clock) period (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
LCPCYC
[#05h] LCP (line clock) period (MSB) and pulse polarity
Data bit Register W/R bit 7 LCP POL W/R (LCP signal period - 1) In units of a CP clock in the STN color 4-bit mode In units of 2 CP clocks in the STN color 8-bit mode or 4-bit 2-phase mode In units of 4 CP clocks in the STN monochrome 4-bit mode In units of 8 CP clocks in the STN monochrome 8-bit mode or 4-bit 2-phase mode In units of a CP clock in the TFT color mode bit 6 bit 5 bit 4 bit 3 bit 2 10 bit 1 LCPCYC 9 W/R 8 bit 0
(Reserved) --
* LCPCYC[10:0]:
* LCPPOL:
LCP Pulse output polarity LCPPOL 0 1 LCP Output polarity Positive pulse Negative pulse
[#06h] LCP (line clock) start position (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
LCPSTA
[#07h] LCP (line clock) start position (MSB) and pulse width
Data bit Register W/R bit 7 3 bit 6 2 W/R LCP start timing, in units of a CP clock (LCP pulse width/4 - 1), in units of a CP clock bit 5 1 bit 4 0 bit 3 (Reserved) -- bit 2 10 bit 1 LCPSTA 9 W/R 8 bit 0
LCPWID
* LCPSTA[10:0]: * LCPWID[3:0]:
44/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#08h] FRP (frame pulse) period (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
FRPCYC
[#09h] FRP (frame pulse) period (MSB) and pulse polarity
Data bit Register W/R bit 7 FRP POL W/R bit 6 bit 5 bit 4 bit 3 bit 2 10 bit 1 FRPCYC 9 W/R 8 bit 0
(Reserved) -- FRP signal period, in units of a line FRP pulse output polarity
* FRPCYC[10:0]: * FRPPOL:
LCPPOL 0 1
FRP pulse output polarity Positive pulse Negative pulse
[#0Ah] FRP (frame pulse) start position (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
FRPSTA
[#0Bh] FRP (frame pulse) start position (MSB) and pulse width
Data bit Register W/R bit 7 3 bit 6 2 W/R FRP start position (FRP pulse width - 1) bit 5 1 bit 4 0 bit 3 (Reserved) -- bit 2 10 bit 1 FRPSTA 9 W/R 8 bit 0
FRPWID
* FRPSTA[10:0]: * FRPWID[3:0]:
45/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#0Ch] DF (AC driving signal) toggle period (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
DFLALT
[#0Dh] DF (AC driving signal) toggle period (MSB) and toggle mode
Data bit Register W/R bit 7 FRP POL W/R bit 6 bit 5 bit 4 bit 3 bit 2 10 bit 1 DFLALT 9 W/R 8 bit 0
(Reserved) --
* DFLALT[10:0]: * DFFALT:
(DF signal toggle period - 1), in units of a line Valid when DFFALT = `1'. DF signal toggle mode DFFALT 0 1 DF toggle mode Reversal at one frame periods Reversal at periods of (DFLALT+1) lines
[#0Eh] General purpose port I/O mode
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 1 W/R bit 0 0
(Reserved) --
PTDDIR
[#0Fh] General purpose port data register
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 1 W/R bit 0 0
(Reserved) -- General purpose port (PORT1, PORT0) I/O direction setting General purpose port (PORT1, PORT0) data register PTDDIR[n] 0 1 Output Input PORTn PTDREGn PORTn PTDREGn PORTn
PTDREG
* PTDDIR[1:0]: * PTDREG[1:0]:
46/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#10h] Color palette table address
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R Color palette table address Table address when writing table data The table address is equivalent to the color palette entry number Incremented automatically every time the table data B is written. bit 3 3 bit 2 2 bit 1 1 bit 0 0
COLPTA
* COLPTA[7:0]:
[#11h] Color palette table data R
Data bit Register W/R bit 7 3 bit 6 2 W only bit 5 1 bit 4 0 bit 3 bit 2 bit 1 bit 0
COLPDR
(Reserved) --
[#12h] Color palette table data G
Data bit Register W/R bit 7 3 bit 6 2 W only bit 5 1 bit 4 0 bit 3 bit 2 bit 1 bit 0
COLPDG
(Reserved) --
[#13h] Color palette table data B, table address incrementing
Data bit Register W/R bit 7 3 bit 6 2 W only Color palette table data R (red) Color palette table data G (green) Color palette table data B (blue) Contents of the entry specified by the color palette table address. The table address is incremented automatically when data is written in COLPDB. bit 5 1 bit 4 0 bit 3 bit 2 bit 1 bit 0
COLPDB
(Reserved) --
* COLPDR[3:0]: * COLPDG[3:0]: * COLPDB[3:0]:
47/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#15h] FRC table address
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 3 bit 2 2 W only bit 1 1 bit 0 0
(Reserved) -- FRC table address
FRCTBA
* COLPTA[7:0]:
The address of the table containing the setting of the FRC dot blinking pattern. Incremented automatically when the table data (MSB) is written.
[#16h] FRC table data (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W only bit 3 3 bit 2 2 bit 1 1 bit 0 0
FRCTBD
[#17h] FRC table data (MSB)
Data bit Register W/R bit 7 15 bit 6 14 bit 5 13 bit 4 12 W only FRC table data The data of the table containing the setting of the FRC dot blinking pattern. The table address denotes the gray level for each color of the color palette output, and the table data specifies the dot blinking pattern for that gradation value. (Blinking in sequence from FRCTBD[15] to FRCTBD[0].) bit 3 11 bit 2 10 bit 1 9 bit 0 8
FRCTBD
* FRCTBD[3:0]:
48/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#18h] Cursor pattern register address
Data bit Register W/R bit 7 bit 6 bit 5 3 bit 4 2 bit 3 1 W only bit 2 0 bit 1 3 bit 0 2
(Reserved) --
CSPTAY
CSPTAX
* CSPTAY[3:0]: * CSPTAX[3:2]:
Cursor pattern register Y address Cursor pattern register X address The address of the register for setting the dot pattern of the cursor. The X address is incremented automatically when the register data is written, and the Y address is incremented when there is an overflow in the X address.
[#19h] Cursor pattern register data
Data bit Register W/R bit 7 1 bit 6 0 bit 5 1 bit 4 0 W only Cursol pattern register data The data of the register for setting the dot pattern of the cursor. This is the 2 bits/pixel data in the 4-pixel packed format. CSPTDn 00 01 10 11 Cursor display data Transparent (display memory contents) Color register 1 (CSCOL1) Color register 2 (CSCOL2) Color register 3 (CSCOL3) bit 3 1 bit 2 0 bit 1 1 bit 0 0
CSPTD0
CSPTD1
CSPTD2
CSPTD3
* CSPTDO-3[1:0]:
49/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#1Dh] Cursor color register 1
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
CSCOL1
[#1Eh] Cursor color register 2
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
CSCOL2
[#1Fh] Cursor color register 3
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R Cursor color register 0 to 3 Color data of the cursor. Corresponds to the entry of the color palette. bit 3 3 bit 2 2 bit 1 1 bit 0 0
CSCOL3
* CSCOL0-3[1:0]:
50/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#20h] Main screen horizontal size (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
MSCSZH
[#21h] Main screen horizontal size (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 9 W/R bit 0 8
(Reserved) -- (Main screen horizontal size - 1), in units of 16 pixels.
MSCSZH
* MSCSZH[9:0]:
[#22h] Main screen vertical size (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
MSCSZV
[#23h] Main screen vertical size (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 9 W/R bit 0 8
(Reserved) -- (Main screen vertical size - 1), in units of the number of lines.
MSCSZV
* MSCSZV[9:0]:
51/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#24h] Sub-screen horizontal size (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
SSCSZH
[#25h] Sub-screen horizontal size (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 9 W/R bit 0 8
(Reserved) -- (Sub-screen horizontal size - 1), in units of a pixel.
SSCSZH
* SSCSZH[9:0]:
[#26h] Sub-screen vertical size (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
SSCSZV
[#27h] Sub-screen vertical size (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 9 W/R bit 0 8
(Reserved) -- (Sub-screen vertical size - 1), in units of the number of lines.
SSCSZV
* SSCSZV[9:0]:
52/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#28h] Sub-screen display horizontal position (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
SDPOSH
[#29h] Sub-screen display horizontal position (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 9 W/R bit 0 8
(Reserved) -- Sub-screen display horizontal position in units of 16 pixels.
SDPOSH
* SDPOSH[9:0]:
The position of displaying the origin of the sub-screen is specified in terms of the display address within the main screen.
[#2Ah] Sub-screen display vertical position (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
SDPOSV
[#2Bh] Sub-screen display vertical position (MSB)
Data bit Register W/R bit 7 SSD ENB W/R bit 6 bit 5 bit 4 (Reserved) -- Sub-screen display vertical position in units of a line. The position of displaying the origin of the sub-screen is specified in terms of the display address within the main screen. bit 3 bit 2 bit 1 9 W/R bit 0 8
SDPOSV
* SDPOSV[9:0]:
* SSDENB:
Sub-screen display enable SSDENB 0 1 Sub-screen Not displayed Displayed
53/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#2Ch] Cursor display horizontal position (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
CSPOSH
[#2Dh] Cursor display horizontal position (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 9 W/R bit 0 8
(Reserved) -- Cursor display horizontal position in units of the number of pixels.
CSPOSH
* CSPOSH[9:0]:
The position of displaying the origin of the cursor is specified in terms of the display address within the main screen.
[#2Eh] Cursor display vertical position (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
CSPOSV
[#2Fh] Cursor display vertical position (MSB), Cursor display enable
Data bit Register W/R bit 7 CSD ENB W/R bit 6 bit 5 bit 4 (Reserved) -- Cursor display vertical position in units of the number of lines. The position of displaying the origin of the cursor is specified in terms of the display address within the main screen. bit 3 bit 2 bit 1 9 W/R bit 0 8
CSPOSV
* CSPOSV[9:0]:
* CSDENB:
Cursor display enable
CSDENB 0 1
Cursor display Disable (Not displayed) Enable (Displayed)
54/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#30h] Display memory horizontal position for main screen (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
MDPSTX
[#31h] Display memory horizontal position for main screen (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 11 bit 2 10 W/R bit 1 9 bit 0 8
(Reserved) --
MDPSTX
* MDPSTX[11:0]:
Main screen display memory horizontal position in units of 16 pixels. The start address of the display memory for displaying in the main screen is specified here.
[#32h] Display memory vertical position for main screen (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
MDPSTY
[#33h] Display memory vertical position for main screen (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 11 bit 2 10 W/R bit 1 9 bit 0 8
(Reserved) --
MDPSTY
* MDPSTY[11:0]:
Main screen display memory vertical position in units of a line. The start address of the display memory for displaying in the main screen is specified here.
55/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#34h] Display memory horizontal position for sub-screen (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
SDPSTX
[#35h] Display memory horizontal position for sub-screen (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 11 bit 2 10 W/R bit 1 9 bit 0 8
(Reserved) --
SDPSTX
* SDPSTX[11:0]:
Sub-screen display memory horizontal position in units of 16 pixels. The start address of the display memory for displaying in the sub-screen is specified here.
[#36h] Display memory vertical position for sub-screen (LSB)
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R bit 3 3 bit 2 2 bit 1 1 bit 0 0
SDPSTY
[#37h] Display memory vertical position for sub-screen (MSB)
Data bit Register W/R bit 7 bit 6 bit 5 bit 4 bit 3 11 bit 2 10 W/R bit 1 9 bit 0 8
(Reserved) --
SDPSTY
* SDPSTY[11:0]:
Sub-screen display memory vertical position in units of a line. The start address of the display memory for displaying in the sub-screen is specified here.
56/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
[#38h] Display memory page number for main screen
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R Main screen display memory page number This is the page number of the display memory that is to be displayed in the main screen. bit 3 3 bit 2 2 bit 1 1 bit 0 0
MDPPGA
* MDPPGA[7:0]:
[#39h] Display memory page number for sub-screen
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R Sub-screen display memory page number This is the page number of the display memory that is to be displayed in the sub-screen. bit 3 3 bit 2 2 bit 1 1 bit 0 0
SDPPGA
* SDPPGA[7:0]:
[#3Bh] Display memory page for host access
Data bit Register W/R bit 7 7 bit 6 6 bit 5 5 bit 4 4 W/R Host access display memory page number This is the page number of the display memory to be accessed by the host CPU. bit 3 3 bit 2 2 bit 1 1 bit 0 0
HSTPGA
* HSTPGA[7:0]:
[#3Ch-3Fh] Writing and reading of these registers are prohibited
57/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Power supply voltage (for the internal core) Power supply voltage (for the LCD driving signals) Output voltage Input voltage Output short-circuit current Power dissipation Storage temperature range Symbol VDDI VDDO Vout Vin Ios Pd Tstg Condition -- -- -- -- -- Ta = 25C -- Rating -0.5 to +4.6 -0.5 to +4.6 VSS - 0.5 to VDD +0.5 VSS - 0.5 to VDD +0.5 50 1 -55 to +150 Unit V V V V mA W
C
RECOMMENDED OPERATING CONDITIONS
(VSS = 0 V) Parameter Power supply voltage Internal core LCD driving signals Operating temperature range Symbol VDDI VDDO Ta Condition Min. 3.0 3.0 -40 Typ. 3.3 3.3 25 Max. 3.6 3.6 85 Unit V V
C
Note: VDDI and VDDO must be powered up at the same time.
58/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(Ta = -40 to 85C, VDD = VDDO = VDDI = 3.3 0.3 V, VSS = 0 V) Parameter H level input voltage L level input voltage H level input voltage L level input voltage H level output voltage L level output voltage H level output voltage L level output voltage Input leakage current Output leakage current During operation Supply current (internal core) Display Off Clock Stopping Clock input feedback resistance XOSCI Symbol VIH1 VIL1 VIH VIL VOH1 VOL1 VOH2 VOL2 ILI ILO IDDI1 IDDI2 IDDI3 RF -- fope = 15MHz Condition -- -- -- -- IOH = 8 mA IOL = 8 mA IOH = 4 mA IOL = 4 mA -- -- Min. 2.4 VSS -0.3 2.0 VSS -0.3 0.8VDD -- 0.8VDD -- -10 -10 -- -- -- 0.4 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- 1.0 Max. VDDI+0.3 0.4 5.5 0.8 -- 0.2VDD -- 0.2VDD +10 +10 55 45 5 2.0 Unit V V V V V V V V
A A
Others BSYN, PORT0,1 Others
mA mA mA M
2. AC Characteristics
(Ta = -40 to 85C, VDDO = VDDI = 3.3 0.3 V, VSS = 0 V) Parameter Operating frequency Output rise time (10% to 90%) Output fall time (90% to 10%) BCLK clock period BCLK H level pulse width BCLK L level pulse width Input setup time (to BCLK) Input hold time (to BCLK) Output delay time (from BCLK)*1 XOSCI clock period XOSCI H level pulse width XOSCI L level pulse width Output delay time (XOSCI to CP, CPS)* Output hold time (from CP, CPS)*2
1
Symbol fope tRO tFO tCK1 tWH1 tWL1 tS1 tH1 tPD1 tCK2 tWH2 tWL2 tPD2 tHCP
Condition -- CL = 15 pF CL = 15 pF -- -- -- -- -- CL = 15 pF -- -- -- CL = 15 pF CL = 15 pF
Min. -- 2 2 66 30 30 10 8 5 66 30 30 2 25
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. 15.0 15 15 -- -- -- -- -- 20 -- -- -- 25 50
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
*1: The output timing characteristics are measured at the signal levels of VDD/2. *2: The output hold time is a relative value, which should be used as a reference value for application design.
59/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
tCK1 tWH1 tWL1
VIH VIL VIH VIL VIH VIL
BCLK INPUT
(CSN, BSN, DSN, WEN, REN, REGS, A, AD, D) tS1 tH1 tS1 tH1
OUTPUT
(BSYN, AD, D)
tPD1
tPD1
(a) Host interface
tCK2 tWH2 tWL2
VIH VIL
XOSCI CP, CPS
tPD2 tPD2
CP, CPS OUTPUT
(DDAn, DDBn, DDCn, DDDn, LCP, FRP, DF) tHCP
(b) LCD interface Fig. A1 AC characteristics
60/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
TIMING DIAGRAMS
1. LCD Interface 1.1 Color STN, 4-bit mode
LCP TCP CP DDA3 DDA2 DDA1 DDA0
Gn-3 Bn-3 Rn-2 Gn-2 Bn-2 Rn-1 Gn-1 Bn-1 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 Gn-3 Bn-3 Rn-2 Gn-2 Bn-2 Rn-1 Gn-1 Bn-1
(MSCSZH+1) x 3/4 [TCP] (LCPCYC+1) [TCP]
TCP = TX (TX is the XOSCI input clock period)
1.2 Color STN, 8-bit mode
LCP TCP CP DDA3 DDA2 DDA1 DDA0 DDB3 DDB2 DDB1 DDB0
Gn-3 Bn-3 Rn-2 Gn-2 Bn-2 Rn-1 Gn-1 Bn-1 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G12 B12 R13 Gn-3 Bn-3 Rn-2 Gn-2 Bn-2 Rn-1 Gn-1 Bn-1
(MSCSZH+1) x 3/8 [TCP] (LCPCYC+1) [TCP]
TCP = 2TX (TX is the XOSCI input clock period)
61/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.3 Color STN, 4-bit 2-phase mode
LCP TCP TCP 1/2TCP CP CPS DDA3 DDA2 DDA1 DDA0
Gn-3 Bn-2 Bn-3 Rn-1 R0 B0 G1 R2 G0 R1 B1 G2 B2 G3 R4 B4 R3 B3 G4 R5 G5 R6 B6 G7 B5 G6 R7 B7 R8 B8 G9 R10 G8 R9 B9 G10 B10 G11 R12 B12 Gn-3 Bn-2 Bn-3 Rn-1
Rn-2 Gn-1 Gn-2 Bn-1
Rn-2 Gn-1 Gn-2 Bn-1
(MSCSZH+1) x 3/4 [TCP] (LCPCYC+1) [TCP]
TCP = TX (TX is the XOSCI input clock period)
62/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.4 Monochrome STN, 4-bit mode
LCP TCP CP DDA3 DDA2 DDA1 DDA0
n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1
(MSCSZH+1) / 4 [TCP] (LCPCYC+1) [TCP]
TCP = 4TX (TX is the XOSCI input clock period)
1.5 Monochrome STN, 8-bit mode
LCP TCP CP DDA3 DDA2 DDA1 DDA0 DDB3 DDB2 DDB1 DDB0
n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1
(MSCSZH+1) / 8 [TCP] (LCPCYC+1) [TCP]
TCP = 8TX (TX is the XOSCI input clock period)
63/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.6 Monochrome STN, 4-bit 2-phase mode
LCP TCP TCP 1/2TCP CP CPS DDA3 DDA2 DDA1 DDA0
n-8 n-6 n-4 n-2 n-7 n-5 n-3 n-1 0 2 4 6 1 3 5 7 8 10 12 14 9 11 13 15 16 18 20 22 17 19 21 23 24 26 28 30 25 27 29 31 32 34 36 38 n-8 n-6 n-4 n-2 n-7 n-5 n-3 n-1
(MSCSZH+1) / 4 [TCP] (LCPCYC+1) [TCP]
TCP = 4TX (TX is the XOSCI input clock period)
64/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.7 Color TFT, 12-bit mode
LCP T CP CP CPS DDA 3 (R3) DDA2 (R2) DDA1 (R1) DDA0 (R0) DDB 3 (G3) DDB2 (G2) DDB1 (G1) DDB0 (G0) DDC 3 (B3) DDC2 (B2) DDC1 (B1) DDC0 (B0)
n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1
(DPSCH+1) [TCP ] (DCYCH+1) [TCP ]
TCP = TX (TX is the XOSCI input clock period)
1.8 Color TFT, 16-bit mode
LCP TCP CP CPS DDA3 (R5) DDA2 (R4) DDA1 (R3) DDA0 (R2) DDB3 (R1) DDB2 (G5) DDB1 (G4) DDB0 (G3) DDC3 (G2) DDC2 (G1) DDC1 (G0) DDC0 (B5) DDD3 (B4) DDD2 (B3) DDD1 (B2) DDD0 (B1)
n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-2 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1 n-1
(DPSCH+1) [TCP] (DCYCH+1) [TCP]
TCP = TX (TX is the XOSCI input clock period)
65/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
1.9 STN vertical timing
FRP
(FRPSTA+1) [TLCP] TLCP
LCP DDA3-0 DDB3-0 DDC3-0 DDD3-0
Line 0 Line 0 Line 0 Line 0 Line 1 Line 1 Line 1 Line 1 Line 2 Line 2 Line 2 Line 2 Line 3 Line 3 Line 3 Line 3 Line 4 Line 4 Line 4 Line 4
(MSCSZV+1) [TLCP] (FRPCYC+1) [TLCP]
1.10 TFT vertical timing
FRP
TLCP (FRPSTA + 1) [TLCP] FRPWID
LCP CPS DDA3-0 DDB3-0 DDC3-0 DDD3-0
Line 0 Line 0 Line 0 Line 0 Line 1 Line 1 Line 1 Line 1 Line 2 Line 2 Line 2 Line 2 Line 3 Line 3 Line 3 Line 3
(MSCSZV+1) [TLCP] (FRPCYC+1) [TLCP]
66/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
PACKAGE DIMENSIONS
TQFP100-P-1414-0.50-K
(Unit: mm)
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.55 TYP. 4/Oct. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
67/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
REVISION HISTORY
Document No.
FEDL87V3104-01 FEDL87V3104-02
Date
Feb., 2001 Nov., 2001
Page Previous Current Edition Edition
- 67 1 4 5, 17 10 19 20 - 67 1 4 5, 17 10 19 20 27 36 40
Description
First version released
Fixed the memory size descriptions Added the pin types Added the notations Fixed the behavior at the Portrait mode COLORD[1:0] "352" "360" [2:0]
FEDL87V3104-03
Nov. 28, 2003
27 36 40
Added the descriptions Added the descriptions of the bit number LCDDAT[1:0] #02h bit3 "--" IMDBPP[1:0] [2:0]
42 42 58, 59 -
42 42 58, 59 68, 69
"W/R"
[2:0] -45 to 85C
Temp. ranges 0 to 70C
Added "REV. HISTORY" and "NOTICE" pages
68/69
FEDL87V3104-03
OKI Semiconductor
ML87V3104
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd.
69/69

▲Up To Search▲

Price & Availability of ML87V3104

	To Download ML87V3104 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .