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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64DBKG is 8388608 - word by 64-bit Synchronous DRAM module. This consists of eight industry standard 4Mx16 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules.
Utilizes industry standard 4M x 16 Sy nchronous DRAMs TSOP and industry standard EEPROM in TSSOP 144-pin (72-pin dual in-line package)
single 3.3V0.3V power supply Max. Clock frequency -6:133MHz,-7,8:100MHz Fully synchronous operation referenced to clock rising edge 4 bank operation controlled by BA0,1(Bank Address) /CAS latency- 2/3(programmable)
FEATURES
Frequency -6,-6L -7,-7L -8,-8L 133MHz 100MHz 100MHz CLK Access Time
(Component SDRAM)
Burst length- 1/2/4/8/Full Page(programmable) Burst type- sequential / interleave(programmable) Column access - random Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycle /64ms LVTTL Interface
5.4ns(CL=3) 6.0ns(CL=2) 6.0ns(CL=3)
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front) (Back)
1 2
143 144
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 1 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM PIN CONFIGURATION
PIN Number Front side Pin Name PIN Number Back side Pin Name PIN Number Front side Pin Name PIN Number Back side Pin Name
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss NC NC CLK0 Vcc /RAS /WE /S0 /S1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss NC NC CKE0 Vcc /CAS CKE1 NC NC
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
NC Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc DQMB2 DQMB3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
CLK1 Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 BA0 Vss BA1 A11 Vcc DQMB6 DQMB7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc
NC = No Connection
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 2 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM Block Diagram
/S0 /S1
DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQML /CS
DQML /CS
DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQML /CS
DQML /CS
I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQMU
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D4 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D2 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D6 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DQMU
DQMU
DQMU
I/O I/O I/O I/O I/O I/O I/O I/O
8 9 10 11 12 13 14 15
DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
10
DQML /CS
DQML /CS
DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQML /CS
DQML /CS
I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQMU
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D5 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D3 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D7 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DQMU
DQMU
DQMU
I/O I/O I/O I/O I/O I/O I/O I/O
8 9 10 11 12 13 14 15
CLK1 CLK0 CKE0 CKE1 /RAS /CAS /WE BA0,BA1,A<11:0> Vcc Vss
4loads 4loads D0 - D3 D4 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7 D0 - D7
SERIAL PD SCL A0 A1 A2 SDA
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 3 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function described Defines # bytes written into serial memory at module mfgr Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL). -6,-6L -7,-7L,-8,-8L -6,-6L -7,-7L,-8,-8L
SPD enrty data 128 256 Bytes SDRAM A0-A11 A0-A7 2BANK x64 0 LVTTL 7.5ns 10ns 5.4ns 6ns
Non-PARITY
SPD DATA(hex) 80 08 04 0C 08 02 40 00 01 75 A0 54 60 00 80 10 00 01 8F 04 06 01 01 00 0E A0 A0 D0 60 60 70 00 00 14 0F 14 14 2D 32
Cycle time for CL=3 SDRAM Access from Clock tAC for CL=3 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
self refresh(15.625uS) x16 N/A 1 1/2/4/8/Full page 4bank 2/3 0 0
non-buffered,non-registered Precharge All,Auto precharge -6,-6L -7,-7L -8,-8L
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported # Banks on Each SDRAM device CAS# Latency CS# Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest CAS latency) Cycle time for CL=2
10ns 10ns 13ns 6ns 6ns 7ns N/A N/A 20ns
24
SDRAM Access form Clock(2nd highest CAS latency)
-6,-6L -7,-7L -8,-8L
tAC for CL=2 25 26 27 28 29 30 SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum Row Active to Row Active Min. RAS to CAS Delay Min Active to Precharge Min
-6,-6L -7,-7L,-8,-8L
15ns 20ns 20ns
-6,-6L -7,-7L,-8,-8L
45ns 50ns
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 4 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31 32 Density of each bank on module Command and Address signal input setup time
-6,-6L -7,-7L,-8,-8L
32MByte 1.5ns 2ns 0.8ns 1ns 1.5ns 2ns 0.8ns 1ns option rev 1.2B Check sum for -6,-6L Check sum for -7,-7L Check sum for -8,-8L
08 15 20 08 10 15 20 08 10 00 12 9E 05 45 1CFFFFFFFFFFFFFF 01 02 03 04
4D483853363444424B472D36202020202020 4D483853363444424B472D364C2020202020 4D483853363444424B472D37202020202020 4D483853363444424B472D374C2020202020 4D483853363444424B472D38202020202020 4D483853363444424B472D384C2020202020
33
Command and Address signal input hold time
-6,-6L -7,-7L,-8,-8L
34 35 36-61 62 63
Data signal input setup time Data signal input hold time Superset Information (may be used in future) SPD Revision Checksum for bytes 0-62
-6,-6L -7,-7L,-8,-8L -6,-6L -7,-7L,-8,-8L
64-71 72
Manufactures Jedec ID code per JEP-108E Manufacturing location
MITSUBISHI Miyoshi,Japan Tajima,Japan NC,USA Germany MH8S64DBKG-6 MH8S64DBKG-6L MH8S64DBKG-7 MH8S64DBKG-7L MH8S64DBKG-8 MH8S64DBKG-8L PCB revision year/week code serial number option 100MHz
-6,-6L,-7,-7L
73-90
Manufactures Part Number
91-92 93-94 95-98 99-125 126
Revision Code Manufacturing date Assembly Serial Number Manufacture Specific Data Intetl specification frequency
rrrr yyww ssssssss 00 64 CF CD 00
127 128+
Intel specification CAS# Latency support
-8,-8L
CL=2/3,AP,CK0,1 CL=3,AP,CK0,1 open
Unused storage locations
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 5 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
CLK (CLK0 ~ CLK1) Input Master Clock:All other inputs are referenced to the rising edge of CK Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. Chip Select: When /S is high,any command means No Operation. Combination of /RAS,/CAS,/WE defines basic commands. A0-11 specify the Row/Column Address in conjunction with BA0,1.The Row Address is specified by A0-11.The Column Address is specified by A0-7.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Bank Address:BA0,1 is not simply BA.BA specifies the bank to which a command is applied.BA0,1 must be set with ACT,PRE,READ,WRITE commands
CKE0, CKE1
Input
/S0, /S1
Input Input
/RAS,/CAS,/WE
A0-11
Input
BA0,1
Input
DQ0-63
Input/Output Data In and Data out are referenced to the rising edge of CK Input Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Vdd,Vss SCL SDA
Power Supply Power Supply for the memory mounted module. Input Output Serial clock for serial PD Serial data for serial PD
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 6 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH8S64DBKG provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.
CK /S /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Ref resh Option @ref resh command Precharge Option @precharge or read/write command def ine basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 7 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Adress Entry & Bank Activate Single Bank Precharge Precharge All Bank Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with Auto Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE CKE n-1 n H H H H H H X X X X X X /S H L L L L L /RAS /CAS X H L L L H X H H H H L /WE BA0,1 A11 X H H L L L X X V V X V X X V X X V A10 A0-9 X X V L H L X X V X X V
WRITEA
H
X
L
H
L
L
V
V
H
V
READ
H
X
L
H
L
H
V
V
L
V
READA REFA REFS REFSX TERM MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
V X X X X X L
H X X X X X L
V X X X X X V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 8 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Current State IDLE /S H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS /CAS X H H H L L L L X H H H H L L L L X H H H X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X X BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X X BA,CA,A10 Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST READ/READA WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST NOP NOP ILLEGAL*2 Bank Active,Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read,Latch CA, Determine Auto-Precharge Begin Write,Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL*2 Precharge/Precharge All ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst Terminate Burst,Latch CA, READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L L L L L H L L L L L H H L L L H L H L BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 BA,RA BA,A10 X Op-Code, Mode-Add ACT PRE/PREA REFA MRS Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL Action
READ/WRITE ILLEGAL*2
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 9 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State WRITE /S H L L L /RAS /CAS X H H H X H H L /WE X H L H X X X BA,CA,A10 Address Command DESEL NOP TBST Action NOP(Continue Burst to END) NOP(Continue Burst to END) Terminate Burst
Terminate Burst,Latch CA, READ/READA Begin Read,Determine AutoPrecharge*3 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 Terminate Burst,Precharge ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X X BA,CA,A10 BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add
WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST WRITE/ WRITEA ACT PRE/PREA REFA MRS DESEL NOP TBST WRITE/ WRITEA ACT PRE/PREA REFA MRS
READ/READA ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL
READ/READA ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 10 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State PRE CHARGING /S H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X X BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X X BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X X BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST ACT PRE/PREA REFA MRS DESEL NOP TBST Action NOP(Idle after tRP) NOP(Idle after tRP) ILLEGAL*2 ILLEGAL*2 NOP*4(Idle after tRP) ILLEGAL ILLEGAL NOP(Row Active after tRCD NOP(Row Active after tRCD ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2
READ/WRITE ILLEGAL*2 ACT PRE/PREA REFA MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 11 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING /S H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS /CAS X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X X BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add X X X BA,CA,A10 BA,RA BA,A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP(Idle after tRC) NOP(Idle after tRC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Idle after tRSC) NOP(Idle after tRSC) ILLEGAL
READ/WRITE ILLEGAL ACT PRE/PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 12 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
Current State SELF REFRESH*1 CK n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CK n X H H H H H L X H L H L L L L L L X H L H L /S X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP(Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3 Exit CK0 Suspend at Next Cycle*3 Maintain CK0 Suspend Action
ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A m inimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only form the All banks idle State. 3. Must be legal command.
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 13 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX MRS
MODE REGISTER SET
REFA
IDLE
AUTO REFRESH
CKEL
CLK SUSPEND
CKEL CKEH
CKEH ACT
POWER DOWN
TERM WRITE
ROW ACTIVE
TERM READ
CKEL
WRITEA
READA READ
CKEL
WRITE SUSPEND
WRITE
CKEH
WRITE
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
CKEL
WRITEA SUSPEND
WRITEA
CKEH PRE
PRE PRE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 14 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock.Attempt to maintain CKE high,DQM0-7 high and NOP condition at the inputs. 2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CK /S BA0 BA1 A11 A10 A9 0 0 0 0 WM A8 0 A7 0 A6 A5 A4 A3 A2 A1 A0 /RAS /CAS LTMODE BT BL /WE BA0,1 A11-0 BL 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 BT= 0 1 2 4 8 R R R FP SEQUENTIAL INTERLEAVED
V
BT= 1 1 2 4 8 R R R R
CL 000 001 LATENCY MODE 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1
/CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT BURST LENGTH
101 110 111 BURST TYPE 0 1
WRITE MODE
R:Reserved for Future Use FP: Full Page
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 15 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CK Command Address DQ CL= 3 BL= 4
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
/CAS Latency
Burst Length Burst Type
Burst Length
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 2 1 1 0 2 3 0 3 0 1 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 16 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-11. Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank is tRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP. Bank Activation and Precharge All (BL=4, CL=2)
CK Command ACT
tRRD ACT tRCD Xb Xb 01 Yb 0 01 Qb0 Qb1 Qb2 Qb3 1 READ PRE tRP Xa Xa 00 ACT
A0-9,11 A10 BA0,1 DQ
Xa Xa 00
Precharge all
READ A READ command can be issued to any active bank. The start address is specified by A07(x16) . 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 17 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=2)
CK Command ACT
tRCD READ Ya 0 00 ACT tRCD Xb Xb 01 Qa0 Qa1 Yb 0 01 Qa2 0 00 Qa3 Qb0 READ PRE tRP Xa Xa 00 Qb1 Qb2 Qb3 ACT
A0-9, 11 A10 BA0,1 DQ
Xa Xa 00
READ with Auto-Precharge (BL=4, CL=2)
CK Command ACT
tRCD READ BL Ya 1 00 Qa0 Qa1 Qa2 Qa3 tRP Xa Xa 00 ACT
A0-9, 11 A10 BA0,1 DQ
Xa Xa 00
Internal precharge starts
Auto-Precharge Timing (READ BL=4)
CK Command ACT
tRCD READ BL Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3 ACT
CL=3 CL=2
DQ DQ
Internal precharge starts
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 18 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
WRITE A WRITE command can be issued to any active bank. The start address is specified by A0-7 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
WRITE (BL=4)
CK Command ACT
tRCD Write BL Ya 0 00 tWR Da0 Da1 Da2 Da3 0 PRE tRP Xa Xa 00 ACT
A0-9, 11 A10 BA0,1 DQ
Xa Xa 00
WRITE with Auto-Precharge (BL=4)
CK Command ACT
tRCD Write BL Ya 1 00 tWR Da0 Da1 Da2 Da3 tRP Xa Xa 00 ACT
A0-9, 11 A10 BA0,1 DQ
Xa Xa 00
Internal precharge begins
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 19 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION [ Read Interrupted by Read ] Burst read oparation can be interrupted by new read of the same or the other bank. Random column access is allowed READ to READ interval is minimum 1 CK Read Interrupted by Read (BL=4, CL=2)
CK Command A0-9,11 A10 BA0,1 DQ
READ Ya 0 00 Qa0 READ READ Yb 0 00 Qa1 Yc 0 10 Qa2 Qb0 Qc0 Qc1 Qc2 Qc3
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=2)
CK Command ACT A0-9,11 A10 BA0,1 DQMB0-7 DQ
Qa0 Da0 Da1 Da2 Da3 Xa Xa 00 READ Ya 0 00 Write Ya 0 00
Output disable by DQM
by WRITE
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 20 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ] A burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CK. A PRE command output disable latency is equivalent to the /CAS Latency. Read Interrupted by Precharge (BL=4)
CK
Command DQ
READ
PRE Q0 Q1 Q2
CL=3
Command DQ Command DQ
READ PRE Q0 READ PRE Q0 Q1
Command DQ
READ Q0
PRE Q1 Q2
CL=2
Command DQ Command DQ
READ PRE Q0 READ PRE Q0 Q1
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 21 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ] Sim ilarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. The terminated bank remains active,READ to TBST interval is minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS Latency. Read Interrupted by Terminate (BL=4)
CK
Command DQ Command
READ
TBST Q0 Q1 Q2
READ
TBST Q0 Q1
CL=3
DQ Command DQ
READ TBST Q0
Command DQ Command
READ Q0
TBST Q1 Q2
READ
TBST Q0 Q1
CL=2
DQ
Command DQ
READ TBST Q0
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 22 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CK. Write Interrupted by Write (BL=4)
CK Command A0-9, 11 A10 BA0,1 DQ
Write Ya 0 00 Da0 Da1 Da2 Write Write Yb 0 00 Db0 Yc 0 10 Dc0 Dc1 Dc2 Dc3
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=2)
CK Command ACT A0-9,11 A10 BA0,1 DQ
Xa Xa 00 Write Ya 0 00 Da0 Da1 READ Yb 0 00 Qb0 Qb1 Qb2 Qb3
don't care
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 23 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank . Write recovery time(tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM. Write Interrupted by Precharge (BL=4)
CK Command A0-9,11 A10 BA0,1
ACT Xa 0 00 Write Ya 0 00 0 00 PRE tRP Xa 0 00 ACT
DQMB0-7 DQ
Da0 Da1
tWR
[ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active.The WRITE to TBST minimum interval is 1CK. Write Interrupted by Burst Terminate (BL=4)
CK Command A0-9,11 A10 BA0,1 DQ
ACT Xa 0 00 Write Ya 0 00 Da0 Da1 TBST Write Yb 0 00 Db0 Db1 Db2 Db3
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 24 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ] Burst write with auto-precharge can be interrupted by write or read toanother bank . Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Autoprecharge interrrupted by a command to the same bank is inhibited. WRITEA Interrupted by WRITE to another bank (BL=4)
CK Command A0-9,11 A10 BA0,1 DQ
Write Ya 1 00 Da0 Da1 Write BL Ya tWR 0 10 Db0 Db1 Db2 Db3 Xa 00 ACT tRP Xa
auto-precharge interrupted
activate
WRITEA interrupted by READ to another bank (CL=2,BL=4)
CK Command A0-9,11 A10 BA0,1 DQ
Write Ya 1 00 Da0 Da1 Read BL Yb tWR 0 10 Db0 Db1 Db2 Xa 00 Db3 tRP Xa ACT
auto-precharge interrupted
activate
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 25 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read with Auto-Precharge interrupted by Read to anotehr Bank ] Burst read with auto-precharge can be interrupted by read toanother bank . Next ACT command can be issued after (BL+tRP) from the READA. Auto-precharge interrrupted by a command to the same bank is inhibited. READA Interrupted by READ to another bank (CL=2,BL=4)
CK Command A0-9,11 A10 BA0,1 DQ
Read Ya 1 00 Read BL Ya 0 10 Qa0 Qa1 Qb0 Qb1 ACT tRP Xa Xa 00 Qb2 Qb3
auto-precharge interrupted
activate
Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill aPrecharge or a Burst Terminate command is issued. In case of the full page burst , a read or write with auto-precharge command is illegal. Single Write When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 26 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L, /WE=/CKE=H) command. The refresh address is generated internally.4096 REFA cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command.
Auto-Refresh
CK /S NOP or DESLECT /RAS /CAS /WE CKE A0-11 BA0,1
minimum tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 27 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L, /WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is kept low.During the self-refresh mode, CKE is asynchronous and the only enabled input , all other inputs including CK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CK edge follwing CKE=H, all banks are in the idle state and a new command can be issued after, but DESEL or NOP commands must be asserted till then. Self-Refresh
CK
Stable CK
/S /RAS /CAS /WE CKE
NOP
new command
A0-11 BA0,1
X
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC for recovery
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 28 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
CK (ext.CLK) tIH CKE tIS tIH tIS
int.CLK
Power Down by CKE
CK CKE Command
PRE NOP NOP NOP Standby Power Down
CKE Command
ACT NOP NOP NOP
Activ e Power Down
DQ Suspend by CKE
CK CKE Command
Write READ
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 29 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL DQMB0-7 is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7 to Data In latency is 0. During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z latency is 2. DQM Function
CK Command DQMB0-7
Write READ
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMB=H
disabled by DQMB=H
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 30 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
ABSOLUTE M AXIMUM RATINGS
Symbol Vdd VI VO IO Pd Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25C Condition with respect to Vss with respect to Vss with respect to Vss Ratings -0.5 ~ 4.6 -0.5 ~ Vdd+0.5 -0.5 ~ Vdd+0.5 50 8 0 ~ 70 -40 ~ 100 Unit V V V mA W C C
RECOM M ENDED OPERATING CONDITION
(Ta=0 ~ 70C, unless otherwise noted) Symbol Vdd Vss VIH VIL Parameter Min. Supply Voltage Supply Voltage High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 3.0 0 2.0 -0.3 Limits Typ. 3.3 0 Max. 3.6 0 Vdd+0.3 0.8 Unit V V V V
Note) 1:VIH(max)=5.5V f or pulse width less than 10ns. 2.VIL(min)=-1.0 f or pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted) Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CK pin Input Capacitance, I/O pin Test Condition VI = 1.4V f=1MHz Vi=200mVrms Limits(max.) 45 45 35 22 Unit pF pF pF pF
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 31 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Parameter
operating current one bank activ e (discrete)
Symbol
Test Condition
Limits (max) -7,-7L, -6,-6L -8,-8L 460 16 8 160 120 240 200 520 1040 8 4 440 16 8 160 120 240 200 440 880 8 4
Unit mA mA mA mA mA mA mA mA mA mA mA
tRC=min.tCLK=min, BL=1,CL=3 Icc1 precharge stanby Icc2P CKE=L,tCLK=15ns, /CS>Vcc-0.2V current in power-down mode Icc2PS CKE=CLK=L, /CS>Vcc-0.2V precharge stanby current Icc2N CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V in non power-down mode Icc2NS CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed) active stanby current in non power-down mode
one bank activ e (discrete)
Icc3N
CKE=H,tCLK=15ns
burst current auto-refresh current self-refresh current
Icc3NS CKE=H,CLK=L tCLK=min, BL=4, CL=3,all banks activ e(discerte) Icc4 tRC=min, tCLK=min Icc5 Icc6 CKE <0.2V -6,-7,-8 -6L,-7L,-8L
Note) 1:Icc(max) is specif ied at the output open condition. 2.Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted)
Symbol VOH(DC) VOL(DC) IOZ VOH(AC) Ii VOL(AC) Limits Min. Max. Unit High-Level Output Voltage(DC) IOH=-2mA 2.4 V Low-Level Output Voltage(DC) IOL=2mA 0.4 V 10 uA Off-stare Output Current High-Level Output Voltage(AC) Q floating VO=0 ~ Vdd -10 CL=50pF, IOH=2 V 40 uA -40 Input Current 2mA ~ Vdd+0.3V VIH=0 Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V Parameter Test Condition
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 32 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V Symbol Parameter CL=2 CL=3 -6,-6L Min. Max. 10 Limits -7,-7L Min. Max. 10 10 3 3 1 2 1 70 80 20 50 20 12 20 10 -8,-8L Unit Min. Max. 13 10 3 3 1 2 1 70 80 20 50 20 12 20 10 ns ns ns ns 10 ns ns ns ns ns ns 100K ns ns ns ns ns 64 ms
tCLK tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF
7.5 2.5 CK High pulse width 2.5 CK Low pilse width 1 Transition time of CK 1.5 Input Setup time(all inputs) 0.8 Input Hold time(all inputs) 67.5 Row cycle time 75 Refresh Cycle time 20 Row to Column Delay 45 Row Active time 20 Row Precharge time 12 Write Recovery time 15 Act to Act Deley time Mode Register Set Cycle time 10 Refresh Interval time
CK cycle tim e
10
10
100K
100K
64
64
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns should be added to the parameter.
CK
1.4V
Any AC timing is referenced to the input
Signal
1.4V
signal crossing through 1.4V.
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 33 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70C, Vdd = 3.3 0.3V, Vss = 0V, unless otherwise note3) Limits -6,-6L -8,-8L -7,-7L Min. Max. Min. Max. Min. Max. CL=2 CL=3 tOH Output Hold tim e from CK CL=2 CL=3 tOLZ tOHZ Delay time, output low impedance from CK Delay time, output high impedance from CK 3 2.7 0 2.7 5.4 6 5.4 3 3 0 3 6 6 6 3 3 0 3 6 7 6
Symbol Parameter tAC Access time from CK
Unit ns ns ns ns ns ns
Note) 1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
CK
1.4V
VOUT 50pF
DQ
1.4V
Output Timing Measurement Reference Point
CK
tOLZ
1.4V
DQ
tAC MIT-DS-0340-0.3 tOH
tOHZ
1.4V
MITSUBISHI ELECTRIC ( 34 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE
tWR tWR
CKE DQM A0-7
X Y X Y
A10 A8-9,11
X
X
X
X
BA0,1 DQ
0
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
PRE#0
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 35 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 tRC tRC 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
tRAS
tRP tRCD
/RAS
tRCD tRCD
/CAS
tWR tWR
/WE CKE DQM A0-7
X Y X Y X Y X
A10 A8-9,11
X
X
X
X
X
X
X
X
BA0,1 DQ
0
0
1
1
0
0
0
1
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0
WRITE#0 ACT#1
PRE#0 ACT#0 WRITEA#1 (Auto-Precharge)
WRITE#0 ACT#1 PRE#0
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 36 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP tRAS
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-7
X Y X Y
A10 A8-9,11
X
X
X
X
BA0,1 DQ
0
0
0
0
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
ACT#0
READ#0
PRE#0 ACT#0
READ#0
PRE#0
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 37 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC tRC
/CS
tRRD tRAS
/RAS
tRCD tRCD tRCD
/CAS /WE CKE
DQM A0-7
X Y X Y X Y X
A10 A8-9,11
X
X
X
X
X
X
X
X
BA0,1 DQ
0
0
1
1
0
0
1
0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0
READA#0 ACT#1
ACT#0 READA#1
READ#0 ACT#1
PRE#0
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 38 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Write @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE CKE DQM A0-7
X Y X Y Y Y X
A10 A8-9,11
X
X
X
X
X
X
BA0,1 DQ
0
0
1
0
1
0
0
1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
WRITE#0 ACT#0 WRITE#0 WRITEA#1 ACT#1 interrupt same bank interrupt other bank
WRITE#0 interrupt other bank
PRE#0
ACT#1
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 39 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Read @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS /WE CKE DQM A0-7
X Y X Y Y Y X
A10 A8-9,11
X
X
X
X
X
X
BA0,1 DQ
0
0
1
1
1
0
1
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READ#0 ACT#1
READ#1 READA#1 interrupt interurrpt other bank same bank
READ#0 interurrpt other bank
ACT#1
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 40 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Read, Read Interrupted by Write @BL=4,CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-7
X X Y Y Y
A10 A8-9,11
X
X
X
X
BA0,1 DQ
0
1
0
1
1
1
D0
D0
Q1
Q1
D1
D1
D1
D1
ACT#0
WRITE#0 READ#1 ACT#1
PRE#1 WRITE#1 Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 41 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Write/Read Terminated by Precharge @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRP tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR
/WE CKE DQM A0-7 A10 A8-9,11
X Y X Y X
X
X
X
X
X
X
BA0,1 DQ
0
0
0
0
0
0
0
D0
D0
Q0
Q0
ACT#0
PRE#0 ACT#0 Termination WRITE#0
READ#0
PRE#0 ACT #0 Termination
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 42 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Write/Read Terminated by Burst Terminate @BL=4,CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS
tWR
/WE CKE
DQM A0-7
X Y Y Y
A10 A8-9,11
X
X
BA0,1 DQ
0
0
0
0
0
D0
D0
D0
Q0
Q0
D0
D0
D0
D0
ACT#0
WRITE#0 TBST READ#0 TBST
WRITE#0
PRE#0
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 43 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Single Write Burst Read @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-7 A10 A8-9,11
X Y Y
X
X
BA0,1 DQ
0
0
0
D0
Q0
Q0
Q0
Q0
ACT#0
READ#0 WRITE#0
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 44 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Power-Up Sequence and Intialize
CLK
200us
/CS
tRP tRFC tRFC tRSC
/RAS /CAS /WE CKE DQM A0-7
MA X
A10 A8-9,11
0
X
0
X
BA0,1 DQ
NOP Power On PRE ALL REFA REFA REFA
0
0
MRS
ACT#0
Minimum 8 REFA cy c les
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 45 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Auto Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRFC
/CS /RAS
tRP tRCD
/CAS /WE CKE DQM A0-7
X Y
A10 A8-9,11
X
X
BA0,1 DQ
PRE ALL REFA
0
0
D0
D0
D0
D0
ACT #0
WRITE#0
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 46 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Self Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRFC
/CS
tRP
/RAS /CAS /WE CKE DQM A0-7
X
A10 A8-9,11
X
X
BA0,1 DQ
0
PRE ALL
Self Refresh Entry
Self RefreshExit
ACT#0
All banks must be idle bef ore REFS is issued.
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 47 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CLK Suspension @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-7
X Y Y
A10 A8-9,11
X
X
BA0,1 DQ
0
0
0
D0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0 Internal CLK suspended
READ#0 Internal CLK suspended
Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 48 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS /CAS /WE
Stanby Power Down Active Power Down
CKE DQM A0-7
X
A10 A8-9,11 BA0,1 DQ
PRE ALL
X
X
0
ACT#0 Italic parameter indicates minimum case
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 49 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
OUTLINE
31.75 20.00 4.00 6.00
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 50 / 51 )
27.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). 4.When using any or all of the information contained in these materials, including product data, diagrams, charts, programs and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 7.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MIT-DS-0340-0.3
MITSUBISHI ELECTRIC ( 51 / 51 )
27.Mar.2001

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