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PD - 95390
IRFIB5N50LPBF
SMPS MOSFET
Applications * Zero Voltage Switching SMPS VDSS RDS(on) typ. Trr typ. ID * Telecom and Server Power Supplies 0.67 500V 73ns 4.7A * Uninterruptible Power Supplies * Motor Control applications * Lead-Free Features and Benefits * SuperFast body diode eliminates the need for external diodes in ZVS applications. * Lower Gate charge results in simpler drive requirements. * Enhanced dv/dt capabilities offer improved ruggedness. TO-220 Full-Pak * Higher Gate voltage threshold offers improved noise immunity.
Absolute Maximum Ratings
ID @ TC = 25C IDM Parameter Continuous Drain Current, VGS @ 10V Pulsed Drain Current Max. 4.7 3.0 16 42 0.33 30 13 -55 to + 150 W W/C V V/ns C 300 (1.6mm from case ) 10lbxin (1.1Nxm) A Units
HEXFET(R) Power MOSFET
ID @ TC = 100C Continuous Drain Current, VGS @ 10V
PD @TC = 25C Power Dissipation VGS dv/dt TJ TSTG Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and
d
Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- --- --- --- 73 99 200 360 6.7 4.7 A 16 1.5 110 150 310 540 10 A V ns
Conditions
MOSFET symbol showing the integral reverse
G S D
p-n junction diode. TJ = 25C, IS = 4.0A, VGS = 0V TJ = 25C, IF = 4.0A TJ = 125C, di/dt = 100A/s TJ = 125C, di/dt = 100A/s TJ = 25C
f f
f f
nC TJ = 25C, IS = 4.0A, VGS = 0V
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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06/10/04
IRFIB5N50LPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
500 --- --- 3.0 --- --- --- --- --- --- 0.43 0.67 --- --- --- --- --- 2.0 --- --- 0.80 5.0 50 2.0 100 -100 --- V V A mA nA
Conditions
VGS = 0V, ID = 250A VGS = 10V, I D = 2.4A
V/C Reference to 25C, ID = 1mA
f
VDS = VGS, ID = 250A VDS = 500V, VGS = 0V VDS = 400V, VGS = 0V, TJ = 125C VGS = 30V VGS = -30V f = 1MHz, open drain
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Coss eff. (ER)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Effective Output Capacitance (Energy Related)
Min. Typ. Max. Units
2.8 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 13 17 26 10 1000 110 12 1360 31 75 55 --- 45 13 23 --- --- --- --- --- --- --- --- --- --- --- pF ns nC S ID = 4.0A
Conditions
VDS = 50V, ID = 2.4A VDS = 400V VGS = 10V, See Fig. 7 & 16 VDD = 250V ID = 4.0A RG = 9.0 VGS = 10V, See Fig. 11a & 11b VGS = 0V VDS = 25V = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 400V, = 1.0MHz VGS = 0V,VDS = 0V to 400V
f f
g
Avalanche Characteristics
Symbol
EAS IAR EAR Parameter Single Pulse Avalanche Energyd Avalanche CurrentA Repetitive Avalanche Energy Typ. --- --- --- Max. 140 4.0 3.0 Units mJ A mJ
Thermal Resistance
Symbol
RJC RJA
Parameter
Junction-to-Case Junction-to-Ambient
Typ.
--- ---
Max.
3.0 65
Units
C/W
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11). Starting TJ = 25C, L = 18mH, RG = 25, IAS = 4.0A, dv/dt = 13V/ns. (See Figure 12a). ISD 4.0, di/dt 280A/s, VDD V(BR)DSS, TJ 150C.
Notes:
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS. Coss eff.(ER) is a fixed capacitance that stores the same energy as C oss while VDS is rising from 0 to 80% VDSS.
2
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IRFIB5N50LPBF
100
TOP VGS 15V 12V 10V 8.0V 7.0V 6.5V 6.0V 5.5V
100
TOP VGS 15V 12V 10V 8.0V 7.0V 6.5V 6.0V 5.5V
ID, Drain-to-Source Current (A)
10
ID, Drain-to-Source Current (A)
10
BOTTOM
1
BOTTOM
1
5.5V
0.1
5.5V
0.01
0.1
20s PULSE WIDTH Tj = 25C
0.001 0.1 1 10 100
0.01 0.1 1
20s PULSE WIDTH Tj = 150C
10 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
I D = 4.0A
2.5
RDS(on) , Drain-to-Source On Resistance
10
TJ = 150
C
I D, Drain-to-Source Current (A)
2.0
1
TJ = 25 C
(Normalized)
1.5
1.0
0.1
0.5
V DS 50V = 20s PULSE WIDTH 0.01 5.0 6.0 7.0 8.0 9.0
V GS = 10V
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
V GS Gate-to-Source Voltage (V) ,
Tj, Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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IRFIB5N50LPBF
100000 VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C SHORTED gs ds Crss = C gd Coss = C + C ds gd
10 9 8 7
10000
C, Capacitance(pF)
1000
Ciss Coss Crss
Energy (J)
100 1000
6 5 4 3
100
10
2 1
1 1 10
0 0 100 200 300 400 500 600
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typ. Output Capacitance Stored Energy vs. VDS
12
100
I D = 4.0A
10
VDS = 400V VDS = 250V VDS = 100V
VGS , Gate-to-Source Voltage (V)
I SD , Reverse Drain Current (A)
8
10
6
T J= 25 C TJ = 150 C
1
4
2
V GS = 0 V
0.1
0 0 5 10 15 20 25 30 35
0.2
0.4
0.6
0.8
1.0
1.2
QG, Total Gate Charge (nC)
V SD ,Source-to-Drain Voltage (V)
Fig 7. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 8. Typical Source-Drain Diode Forward Voltage
4
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IRFIB5N50LPBF
100 OPERATION IN THIS AREA LIMITED BY R DS(on)
4.0 5.0
ID, Drain-to-Source Current (A)
10
ID , Drain Current (A)
3.0
100sec 1 Tc = 25C Tj = 150C Single Pulse 0.1 1 10 100 1msec 10msec
2.0
1.0
0.0
1000
10000
25
50
75
100
125
150
VDS, Drain-to-Source Voltage (V)
TC , Case Temperature ( C)
Fig 9. Maximum Safe Operating Area
Fig 10. Maximum Drain Current vs. Case Temperature
V DS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
RD
VDS 90%
D.U.T.
+
-VDD
10% VGS
td(on) tr t d(off) tf
Fig 11a. Switching Time Test Circuit
Fig 11b. Switching Time Waveforms
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IRFIB5N50LPBF
10
(Z thJC )
D = 0.50 1 0.20
Thermal Response
0.10 0.05 P DM 0.1 0.02 0.01 t1 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 0.1 t1 / t 2 +TC 1 10 t2
J = P DM x Z thJC
t 1, Rectangular Pulse Duration (sec)
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
6.0
VGS(th) Gate threshold Voltage (V)
5.0
ID = 250A
4.0
3.0
2.0 -75 -50 -25 0 25 50 75 100 125 150
T J , Temperature ( C )
Fig 13. Threshold Voltage vs.Temperature
6
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IRFIB5N50LPBF
320
TOP BOTTOM
ID 1.8A 2.5A 4.0A
EAS , Single Pulse Avalanche Energy (mJ)
240
160
80
0 25 50 75 100 125 150
Starting Tj, Junction Temperature
( C)
Fig 14. Maximum Avalanche Energy vs. Drain Current
15V
V(BR)DSS
VDS L
DRIVER
tp
RG
20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 15a. Unclamped Inductive Test Circuit
Current Regulator Same Type as D.U.T.
Fig 15b. Unclamped Inductive Waveforms
50K 12V .2F .3F
QG
10 V
D.U.T. + V - DS
QGS VG
QGD
VGS
3mA
IG
ID
Current Sampling Resistors
Charge
Fig 16a. Gate Charge Test Circuit
Fig 16b. Basic Gate Charge Waveform
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IRFIB5N50LPBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. For N-Channel HEXFET(R) Power MOSFETs
8
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IRFIB5N50LPBF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
E X AM P L E : T H IS IS AN IR F I8 4 0G W IT H AS S E M B L Y L O T COD E 3 4 3 2 AS S E M B L E D O N W W 24 1 9 9 9 IN T H E AS S E M B L Y L IN E "K " P AR T N U M B E R IN T E R N AT ION AL R E CT I F IE R L OG O AS S E M B L Y L O T COD E
IR F I84 0G 9 24 K 34 32
Note: "P" in assembly line position indicates "Lead-Free"
D AT E CO D E Y E AR 9 = 1 9 9 9 W E E K 24 L IN E K
TO-220AB FullPak package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.06/04
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