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TECHNICAL DATA IN74LV640 Octal 3-State Inverting Bus Transceiver The 74LV640 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT640. The 74LV640 provides six inverting buffers with Schmitt-trigger action. * * * * Wide Operating Voltage: 1.2 to 3.6 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low input current ORDERING INFORMATION IN74LV640N Plastic IN74LV640D SOIC IZ74LV640 Chip TA = -40 to 125 C for all packages PIN ASSIGNMENT DIR 01 A1 02 20 VCC 19 OE 18 17 16 LOGIC DIAGRAM DIR 01 OE A1 B1 03 A2 B2 04 A3 B3 05 A4 B4 06 A5 B5 07 A6 B6 08 A7 B7 A8 09 B8 11 12 13 14 15 16 17 18 19 A2 03 A3 04 A4 05 A5 06 A6 07 A7 08 A8 09 GND 10 640 B1 B2 B3 B4 B5 B6 B7 B8 15 14 13 12 11 02 FUNCTION TABLE Inputs OE L L H DIR L H X Inputs/Outputs A A=B input Z A input B=A Z PIN 20=VCC PIN 10 = GND 1 IN74LV640 MAXIMUM RATINGS * Symbol VCC IIK* 1 IOK* Io* 2 3 Parameter DC supply voltage (Referenced to GND) DC input diode current DC output diode current DC output source or sink current -bus driver outputs DC GND current for types with - bus driver outputs DC VCC current for types with - bus driver outputs Power dissipation per paskade, plastic DIP+ SOIC package+ Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) Value -0.5 / +5.0 20 50 35 70 70 750 500 -65 / +150 260 Unit V mA mA mA mA mA mW C C IGND ICC PD Tstg TL * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 65 to 125C SOIC Package: : - 8 mW/C from 65 to 125C * 1: VI < -0.5V or VI > VCC+0.5V * 2: Vo < -0.5V or Vo > VCC+0.5V * 3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tLH, t HL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Min 1.2 0 -40 0 Max 3.6 VCC +125 1000 700 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. 2 IN74LV640 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol VIH Parameter High-Level Input Voltage Test Conditions VO = VCC0.1 V VCC V 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 VI = VIH -or VIL IO = -50 A VI = VIH -or VIL IO = -8.0 mA VOL Low-Level Output Voltage VI = VIH -or VIL IO = 50 A VI = VIH -or VIL IO = 8.0 mA IIL IIH Low-Level Input Leakage Current High-Level Input Leakage Current Maximum ThreeState Leakage Current Quiescent Supply Current (per Package) VI=0 V VI= VNN * * -0.1 0.1 -1.0 1.0 -1.0 1.0 A A 1.2 2.0 3.0 3.6 3.0 0.09 0.09 0.09 0.09 0.33 0.1 0.1 0.1 0.09 0.40 0.1 0.1 0.1 0.09 0.50 V 1.2 2.0 3.0 3.6 3.0 25C min 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 max 0.3 0.6 0.9 1.1 Guaranteed Limit -40C / 85C min max 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.34 0.3 0.6 0.9 1.1 -40C / 125C min max 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 0.3 0.6 0.9 1.1 Unit V VIL Low -Level Input Voltage V VOH High-Level Output Voltage V IOZ VI= VIL or VIH VO=VCC or GND VI=0 V or VNN IO = 0 A 1.2 * - 0.5 - 5.0 - 10 A ICC * - 8.0 - 80.0 - 180.0 A . 3 IN74LV640 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH =t HL = 6.0 ns, RL=1 k? ) Symbol tPLH, t PHL Parameter Propagation Delay, A to B , B to A Test Conditions VIL=0 V VIH=VCC tLH = tHL =6.0 ns NL = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns NL = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns NL = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns NL = 50 pF VCC V 1.2 2.0 * 25C min max 100 23 14 Guaranteed Limit -40C / 85C min max 125 28 18 -40C / 125C min max 140 34 21 Unit ns tPLZ, t PHZ Propagation Delay , Direction or Output Enable to A or B Propagation Delay , Direction or Output Enable to A or B Output Transition Time, Any Output 1.2 2.0 * - 120 30 20 - 140 37 24 - 160 43 28 ns tPZL, t PZH 1.2 2.0 * - 120 28 17 - 140 35 21 - 160 43 26 ns tTLH, t THL 1.2 2.0 * - 60 16 10 - 75 20 13 - 90 24 15 ns CI Input Capacitance (Pin 1 or Pin 19) Input Capacitance (Pin 2-9 or Pin 11-18) VI=0 V or VNN 3.0 - 7.0 - - - - pF CI/O 3.0 - 20.0 - - - - pF CPD * - VCC=3.30.3V - 50 - - - - pF t HL 0.9 V1 0.1 0.9 V1 t LH VCC 0.1 PULSE GENERATOR VI VC C VO DEVICE UNDER TEST t PHL GND RT CL RL t PLH V CC 0.9 V1 V1 0.1 0.9 0.1 B (A) t THL t TLH Termination resistance RT - should be equal to ZOUT of pulse generators Figure 1. Switching Waveforms Figure 2. Test Circuit 4 IN74LV640 CHIP PAD DIAGRAM IZ74LV640 Chip marking EALV640 (X=2.010;Y=1.810) 18 19 20 17 16 15 14 13 12 11 1.99 +0.03 10 01 02 03 04 05 06 07 08 09 2.30 0.03 Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Symbol DIR A1 A2 A3 A4 A5 A6 A7 A8 GND B8 B7 B6 B5 B4 B3 B2 B1 X 0.140 0.140 0.370 0.790 1.000 1.200 1.417 1.833 2.060 2.060 2.060 2.060 1.833 1.415 1.000 0.790 0.580 0.370 0.140 0.140 Y 0.573 0.315 0.140 0.140 0.140 0.140 0.140 0.140 0.354 0.760 1.340 1.520 1.750 1.750 1.750 1.750 1.750 1.750 1.544 1.375 OE VCC 5 |
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