 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| D a t a S he et , R e v . 1 . 0 2 , D e c . 2 00 3 H Y S 7 2 D 2 5 6 5 2 0 G R -7 - A 184 Pi n Regi stere d Doubl e Dat a Ra te SDRAM Modules Reg DIMM DDR SDRAM L e a d C o nt a i n i n g M e m or y P r o du c t s Never stop thinking. Edition 2003-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. D a t a S he et , R e v . 1 . 0 2 , D e c . 2 00 3 H Y S 7 2 D 2 5 6 5 2 0 G R -7 - A 184 Pi n Regi stere d Doubl e Dat a Ra te SDRAM Modules Reg DIMM D D R S D R A M L e a d C on t a i n i n g M e m or y P r o du c t s Never stop thinking. HYS72D256520GR-7-A Revision History: Previous Version: All Page All 18 All 20 Previous Version: Rev. 1.02 Rev. 1.0 Rev. 0.9 2003-12 2003-12 2003-10 Editorial changes from the Review step Subjects (major changes since last revision) New template IDD Specification changed DDR 200 removed Package Outline changed We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Template: mp_a4_v2.2_2003-10-07.fm HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules 1 1.1 1.2 2 3 3.1 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Sheet 5 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Overview 1 1.1 * * * * * * * * * * * * Overview Features 184-pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for "1U" PC, Workstation and Server main memory applications Two ranks 256M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply Built with DDR SDRAMs in 66-Lead TSOPII package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Re-drive for all input signals using register and PLL devices. Serial Presence Detect with E2PROM Low Profile Modules form factor: 133.35 mm x 30.48 mm (1.2") x 6.80 mm with stacked components) Based on Jedec standard reference card layout RawCard "N" Gold plated contacts Performance -7 DDR266A PC2100 @CL2.5 @CL2 Unit - MHz MHz Table 1 Part Number Speed Code Speed Grade max. Clock Frequency fCK fCK 143 133 1.2 Description The HYS72D256520GR-7-A are low profile versions of the standard Registered DIMM modules with 1.2" inch (30,48 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as 256M x 72 (2GB). The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. Data Sheet 6 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Overview Table 2 Type Ordering Information1)2) Compliance Code2) Description SDRAM Technology Module height PC2100 (CL=2): HYS72D256520GR-7-A PC2100R-20330-N two ranks 2 GByte Reg. DIMM 512 MBit (x4) (stacked) 1.2" 1) All part numbers end with a place code (not shown), designating the silicon-die revision. Reference information available on request. Example: HYS72D32500GR-7-A, indicating Rev.A die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort for example "PC2100R", the latencies (for example "20330" means CAS latency = 2.5, tRCD latency = 3 and tRP latency =3 ) and the Raw Card used for this module Data Sheet 7 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Pin Configuration 2 Table 3 Symbol Pin Configuration Pin Definitions and Functions Type Function Address Inputs (A12 for 256Mb & 512Mb based modules) A0 - A11,A12 BA0, BA1 DQ0 - DQ63 CB0 - CB7 RAS CAS WE CKE0, CKE1 DQS0 - DQS8 CK0, CK0 DQS9 - DQS17 CS0 - CS1 Bank Selects Data Input/Output Check Bits (x72 organization only) Row Address Strobe Column Address Strobe Read/Write Input Clock Enable SDRAM low data strobes Differential Clock Input SDRAM low data mask/ high data strobes Chip Selects Power (+2.5 V) Ground I/O Driver power supply VDD Indentification flag EEPROM power supply I/O reference supply Serial bus clock Serial bus data line slave address select no connect don't use Reset pin (forces register inputs low)1) VDD VSS VDDQ VDDID VDDSPD VREF SCL SDA SA0 - SA2 NC DU RESET 1) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at the end of this datasheet Table 4 Density 2 GB Address Format Organization Memory SDRAMs Ranks 256M x 72 2 (512Mb) 128M x 4 # of # of row/bank/ SDRAMs column bits 36 13/2/12 (stacked) Refresh Period Interval 8k 64 ms 7.8 s Data Sheet 8 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Pin Configuration Table 5 PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Data Sheet Pin Configuration1) Symbol PIN# 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Symbol A0 CB2 PIN# 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 9 Symbol DQ4 DQ5 PIN# 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol A10 CB6 VREF DQ0 VSS DQ1 DQS0 DQ2 VSS CB3 BA1 KEY DQ32 VDDQ DQS9 DQ6 DQ7 VDDQ CB7 KEY VSS DQ36 DQ37 VDD DQ3 NC RESET VSS NC NC NC VDDQ DQ33 DQS4 DQ34 VDD DQS13 DQ38 DQ39 VSS DQ8 DQ9 DQS1 VDDQ DQ12 DQ13 DQS10 VSS BA0 DQ35 DQ40 VSS DQ44 RAS DQ45 VDDQ DU DU VDD DQ14 DQ15 CKE1 VDDQ WE DQ41 CAS VDDQ CS0 CS1 DQS14 VSS DQ10 DQ11 CKE0 VDDQ NC DQ20 NC / A12 VSS DQS5 DQ42 DQ43 VSS DQ46 DQ47 NC VDDQ DQ16 DQ17 DQS2 VSS DQ21 A11 DQS11 VDD NC DQ48 DQ49 VDDQ DQ52 DQ53 NC VSS A9 DQ18 A7 VDD DQ22 A8 DQ23 VSS DU DU VDD DQS15 DQ54 DQ55 VDDQ DQ19 A5 DQ24 VDDQ DQS6 DQ50 DQ51 VSS A6 DQ28 DQ29 VDDQ NC DQ60 DQ61 VSS DQ25 DQS3 A4 VSS VDDID DQ56 DQ57 VDDQ DQS12 A3 DQ30 VSS DQS16 DQ62 DQ63 VDD DQ26 DQ27 A2 VDD DQS7 DQ58 VSS DQ31 CB4 VDDQ Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Pin Configuration Table 5 PIN# 42 43 44 45 46 47 Pin Configuration1) (cont'd) Symbol PIN# 88 89 90 91 92 93 Symbol DQ59 PIN# 135 136 137 138 139 140 Symbol CB5 PIN# 181 182 183 184 - - Symbol SA0 SA1 SA2 VSS A1 CB0 CB1 VSS NC SDA SCL VDDQ CK0 CK0 VDDSPD - - VDD DQS8 VSS DQS17 VSS 1) A12 is used for 256Mbit and 512Mbit based modules only. Data Sheet 10 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Pin Configuration V SS RS1 RS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D0 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D18 DM DM0/DQS9 DQ4 DQ5 DQ6 DQ7 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D9 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS D27 DM DQS1 CS D1 DM CS D19 DM DQ8 DQ9 DQ10 DQ11 DM1/DQS10 CS D10 DQ12 DQ13 DQ14 DQ15 DM CS D28 DM DQS2 DQ16 DQ17 DQ18 DQ19 DM2/DQS11 CS D2 DM CS D20 DM DQ20 DQ21 DQ22 DQ23 CS D11 DM CS D29 DM DQS3 CS D3 DM CS D21 DM DM3/DQS12 CS D12 DM CS D30 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM DQS4 CS D4 DM CS D22 DQ32 DQ33 DQ34 DQ35 DM4/DQS13 DQ36 DQ37 DQ38 DQ39 CS D13 DM CS D31 DM DQS5 CS D5 DM CS D23 DM DM5/DQS14 DQ44 DQ45 DQ46 DQ47 S D14 S D32 DM DQS6 DQ40 DQ41 DQ42 DQ43 CS D6 DM CS D24 DM DM6/DQS15 DQ52 DQ53 DQ54 DQ55 CS D15 CS D33 DM DQ48 DQ49 DQ50 DQ51 DQS7 DQ56 DQ57 DQ58 DQ59 CS D7 DM CS D25 DM DM7/DQS16 DQ60 DQ61 DQ62 DQ63 CS D16 DM CS D34 DM DQS8 CB0 CB1 CB2 CB3 CS D8 DM CS D26 DM DM8/DQS17 CB4 CB5 CB6 CB7 Serial PD CS D17 DM CS D35 DM CK0, CK 0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE PC K PC K R E G I S T E R RS0 -> CS : SDRAMs D0-D17 RS1 -> CS : SDRAMs D18 -D35 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35 RA0-RA12 -> A0-A12: SDRAMs D0 - D35 RRAS -> RAS : SDRAMs D0 - D35 RCAS -> CAS : SDRAMs D0 - D35 RCKE0 -> CKE: SDRAMs D0 - D17 RCKE1 -> CKE: SDRAMs D18 - D35 RWE -> WE : SDRAMs D0 - D35 RESET V DDSPD SDA EEPROM SCL A0 A1 A2 VDD, VDDQ VREF V SS V DDID D0 - D35 D0 - D35 D0 - D35 Strap: see Note 4 SA0 SA1 SA2 Notes: 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, Adress and control resistors: 22 Ohms. 4. VDDID strap connections STRAP OUT (OPEN): VDD = VDDQ 5. SDRAM placement alternates between the back and front of the DIMM. Figure 1 Block Diagram: Two Ranks 256M x 72 DDR SDRAM DIMM Modules (x4 comp.) HYS72D256520GR on Raw Card N Data Sheet 11 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Electrical Characteristics 3 3.1 Table 6 Parameter Electrical Characteristics Operating Conditions Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. -0.5 -1 -1 -1 0 -55 - - Unit Note/ Test Condition V V V V C C W mA - - - - - - - - Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT VDDQ + 0.5 +3.6 +3.6 +3.6 +70 +150 - - Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 7 Parameter Device Supply Voltage Output Supply Voltage Electrical Characteristics and DC Operating Conditions Symbol Min. Values Typ. 2.5 2.5 2.5 Max. 2.7 2.7 3.6 0 V V V V 2) Unit Note/Test Condition 1) VDD 2.3 2.3 2.3 0 VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ Input Reference Voltage VREF I/O Termination Voltage VTT (System) Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current -- -- 3) 4) 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 0.71 VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6 1.4 V -- 7) 7) 7) VIN(DC) VID(DC) VIRatio 7)5) 6) II -2 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 7)8) Data Sheet 12 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Electrical Characteristics Table 7 Parameter Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver 1) 0 C TA 70 C 2) Under all conditions, VDDQ must be less than or equal to VDD. 3) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 4) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 5) VID is the magnitude of the difference between the input level on CK and the input level on CK. 6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 7) Inputs are not recognized as valid until VREF stabilizes. 8) Values are shown per DDR SDRAM component Electrical Characteristics and DC Operating Conditions (cont'd) Symbol Min. Values Typ. Max. 5 -16.2 -- A mA mA DQs are disabled; 0 V VOUT VDDQ -5 -- 16.2 Unit Note/Test Condition 1) IOZ IOH IOL VOUT = 1.95 V VOUT = 0.35 V Table 8 Parameter IDD Conditions Symbol Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VILMAX; tCK = IDD0 IDD1 IDD2P tCKMIN Precharge Floating Standby Current: CS VIHMIN, all banks idle; IDD2F CKE VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: CS VIHMIN, all banks idle; CKE VIHMIN; tCK = tCKMIN, address and other control inputs stable at VIHMIN or VILMAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down mode; CKE VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM. IDD2Q IDD3P Active Standby Current: one bank active; CS VIHMIN; CKE VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, IDD3N DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs IDD4R changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs IDD4W changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN Data Sheet 13 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Electrical Characteristics Table 8 Parameter Auto-Refresh Current: tRC = tRFCMIN, burst refresh Self-Refresh Current: CKE 0.2 V; external clock on; tCK = tCKMIN Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test conditions. Table 9 IDD Conditions Symbol IDD5 IDD6 IDD7 IDD Specifications HYS72D256520GR-7-A 2GB x72 2 Ranks -7 typ. max. 4908 5088 880 2176 1384 1024 2896 5448 5358 7428 556 8688 mA mA mA mA mA mA mA mA mA mA mA mA 1)4) 1)3)4) 2)4) 2)4) 2)4) 2)4) 2)4) 1)3)4) 1)4) 1)4) 2)4) 1)3)4)5) Product Type & Organisation Unit Note/ Test Conditions5) IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 4008 4188 736 1816 740 880 2356 4548 3198 6168 466 7248 1) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank) 3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4) DRAM component currents only: module currents IDD will be measured differently depending upon register and PLL operation 5) Test condition for maximum values: VDD = 2.7 V, TA = 10 C Data Sheet 14 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Electrical Characteristics Table 10 Electrical Characteristics & AC Timing for DDR components (for reference only) 70 C TA 70 C; VDDQ = 2.5 V 0.2 V; VDD = 2.5 V 0.2 V Symbol DDR266A -7 min. DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedence time from CK/CK Data-out low-impedence time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (for DQS & associated DQ signals) Data hold skew factor Data Output hold time from DQS DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) CL = 2.5 CL = 2.0 max. +0.75 +0.75 0.55 0.55 12 12 - - - - +0.8 +0.8 1.25 +0.5 +0.75 - - - - - 0.60 - - - - - 1.1 0.60 ns ns ns ns ns ns 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1)10) 1) to 4)11) Parameter Unit Notes tAC tDQSCK tCH tCL tHP tCK tCK tDH tDS tIPW tDIPW tHZ tLZ tDQSS tDQSQ -0.75 -0.75 0.45 0.45 7 7.5 0.5 0.5 2.2 1.75 - -0.8 0.75 - - 0.35 0.2 0.2 14 0 0.40 0.25 0.9 1.0 0.9 1.0 tCK tCK ns ns ns ns ns ns ns ns ns min. (tCL,tCH) 1) to 4)5) 1) to 4)5) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4) tCK ns ns ns tQHS tQH tDQSL,H (tHP-tQHS) tCK tCK tCK ns ns tDSS DQS falling edge hold time from CK (write cycle) tDSH Mode register set command cycle time tMRD Write preamble setup time tWPRES Write postamble tWPST Write preamble tWPRE Address and control input setup time fast slew rate tIS slow slew rate Address and control input hold time fast slew rate tIH slow slew rate Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Data Sheet 15 1) to 4) 1) to 4) 1) to 4) 1) to 4)7) 1) to 4)6) 1) to 4) 2) to 4)10)11) tCK tRPRES tRPST tRAS tRC tRFC 0.9 0.40 45 65 75 tCK tCK 1) to 4)3) 1) to 4)4) 1) to 4)5) 120,00 ns 0 - - ns ns 1) to 4)6) 1) to 4)7) Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Electrical Characteristics Table 10 Electrical Characteristics & AC Timing for DDR components (for reference only) 70 C TA 70 C; VDDQ = 2.5 V 0.2 V; VDD = 2.5 V 0.2 V Symbol DDR266A -7 min. Active to Read or Write delay Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval 1) Input slew rate >=1V/ns for DDR266. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns. 3) Inputs are not recognized as valid until VREF stabilizes. 4) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 8) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 10) These parameters guarantee device timing, but they are not necessarily tested on each device 11) Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, measured between VOH(ac) and VOL(ac) Parameter Unit Notes max. - - - - ns ns ns ns 1) to 4)8) 1) to 4)9) 1) to 4)10) 1) to 4)11) 1) to 4)9) tRCD tRP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI 20 20 15 15 (tWR/tCK) + (tRP/tCK) 1 75 200 - - - - 7.8 tCK tCK ns 1) to 4) 1) to 4) 1) to 4) 1) to 4)8) tCK s 512 Mbit based Data Sheet 16 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules SPD Contents 4 Table 11 SPD Contents SPD Codes for Product Type & Organization HYS72D256520GR-7-A 2 GByte x72 2 Ranks Label Code Jedec SPD Revision PC2100R-20330 Rev 0.0 HEX 80 08 07 0D 0C 02 48 00 04 70 75 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 75 00 00 50 3C 50 2D 01 18 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Data Sheet Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules SPD Contents Table 11 SPD Codes for Product Type & Organization HYS72D256520GR-7-A 2 GByte x72 2 Ranks Label Code Jedec SPD Revision Byte# 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Data Sheet Description tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 19 PC2100R-20330 Rev 0.0 HEX 90 90 50 50 00 41 4B 30 32 75 00 00 00 00 86 C1 49 4E 46 49 4E 45 4F xx 37 32 44 32 35 36 35 32 30 47 52 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules SPD Contents Table 11 SPD Codes for Product Type & Organization HYS72D256520GR-7-A 2 GByte x72 2 Ranks Label Code Jedec SPD Revision Byte# 84 85 86 87 88 89 90 91 92 93 94 95 - 98 99 - 127 Description Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) not used PC2100R-20330 Rev 0.0 HEX 37 42 20 20 20 20 20 xx xx xx xx xx 00 Data Sheet 20 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Package Outlines 5 0.1 A B C Package Outlines 133.35 128.95 6.81 MAX. A 1) 0.15 A B C 4 0.1 1 2.5 0.1 o0.1 A B C 6.62 2.175 6.35 92 30.48 0.13 BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184 3.8 0.13 10 3 MIN. Detail of contacts 1) 0.2 1.27 1 0.05 2.5 0.2 0.1 A B C 1) On ECC modules only Burr max. 0.4 allowed Figure 2 Package Outlines Raw Card N with stacked components Data Sheet 20 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 17.8 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Application Note 6 Application Note Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode. Table 12 RESET H H H H L The function for RESET is as follows:1) Register Outputs CK Rising Rising L or H High Z X or Hi-Z CK Falling Falling L or H High Z X or Hi-Z Data in (D) H L X X X or Hi-Z Data out (Q) H L Qo Illegal input conditions L Register Inputs 1) X : Don't care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK risning and CK falling As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2rank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM rank through the use of the RESET pin. Data Sheet 21 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Application Note Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs. 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence). Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). 1. The system applies Self Refresh entry command. (CKELow, CSLow, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. 3. The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address Data Sheet 22 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Application Note signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation. 4. The DIMM is in lowest power Self Refresh mode. Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. System enters Self Refresh entry command. (CKE Low, CS Low, RAS Low, CAS Low, WE High) Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. 3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. 4. The DIMM is in a low power, Self Refresh mode. Data Sheet 23 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 HYS72D256520GR-7-A Registered Double Data Rate SDRAM Modules Application Note Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case. Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result. Data Sheet 24 Rev. 1.02, 2003-12 10282003-P6EY-RWQ2 www.infineon.com Published by Infineon Technologies AG |
Price & Availability of HYS72D256520GR-7-A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |