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HUFA76404DK8T N-Channel Dual MOSFET
April 2005
HUFA76404DK8T N-Channel Dual MOSFET
62V, 3.2A, 132m Features
rDS(ON) = 110m (Typ.), VGS = 5V, ID = 3.2A Qg(tot) = 3.8nC (Typ.), VGS = 5V Low Miller Charge Low QRR Body Diode Optimized efficiency at high frequencies UIS Capability (Single Pulse and Repetitive Pulse) Internal RG = 100 Qualified to AEC Q101
Applications
Motor / Body Load Control ABS Systems Powertrain Management Injection Systems DC-DC converters and Off-line UPS Distributed Power Architectures and VRMs Primary Switch for 12V and 24V systems
Branding Dash
SOURCE 1 (1) GATE 1 (2) 5
DRAIN 1 (8) DRAIN 1 (7)
1 2 3 4
DRAIN 2 (6) SOURCE 2 (3) GATE 2 (4) DRAIN 2 (5)
SO-8
(c)2005 Fairchild Semiconductor Corporation HUFA76404DK8T Rev. B
1
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HUFA76404DK8T N-Channel Dual MOSFET
MOSFET Maximum Ratings TA = 25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TA = 25oC, VGS = 10V, RJA = 50oC/W) Continuous (TA = Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 25oC, VGS = 5V, RJA = 50oC/W) 3.6 3.2 Figure 4 128 2.5 20 -55 to 150 A A A mJ W mW/oC
oC
Ratings 62 20
Units V V
Thermal Characteristics
RJA RJA RJA Pad Area = 0.50 in2 (323 mm2) (Note 2) Pad Area = 0.027 in (17.4 mm ) (Note 3) Pad Area = 0.006 in2 (3.87 mm2) (Note 4)
2 2
50 170 183
o o
C/W C/W
oC/W
Package Marking and Ordering Information
Device Marking 76404DK8 Device HUFA76404DK8T Package SO-8 Reel Size 330mm Tape Width 12mm Quantity 2500 units
Electrical Characteristics TA = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 55V, VGS = 0V VDS = 50V, VGS = 0V, TA = 150oC VGS = 20V 62 1 250 100 A nA V
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 3.6A, VGS = 10V ID = 3.2A, VGS = 5V 1 0.088 0.110 3 0.110 0.132 V
Dynamic Characteristics
CISS COSS CRSS RG Qg(tot) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0.5V, f = 1MHz VGS = 0V to 5V VGS = 0V to 1V VDD = 30V ID = 3.6A Ig = 1.0mA 250 80 7 100 3.8 0.3 0.8 0.5 1.7 4.9 0.4 pF pF pF nC nC nC nC nC
2 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
(VGS = 10V) VDD = 30V, ID = 3.6A VGS = 10V, RGS = 47 13 26 145 53 65 330 ns ns ns ns ns ns
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 3.6A ISD = 1.8A ISD= 3.6A, dISD/dt= 100A/s ISD= 3.6A, dISD/dt= 100A/s 1.25 1.0 37 38 V V ns nC
Notes: 1: Starting TJ = 25C, L = 41mH, IAS = 2.5A, VDD = 62V, VGS = 10V. 2: 50oC/W measured using FR-4 board with 0.50 in2 (323 mm2) copper pad at 1 second. 3: 170oC/W measured using FR-4 board with 0.027 in2 (17.4 mm2) copper pad at 1000 seconds. 4: 183oC/W measured using FR-4 board with 0.006 in2 (3.87 mm2) copper pad at 1000 seconds.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
3 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
Typical Characteristics TA = 25C unless otherwise noted
1.2 POWER DISSIPATION MULTIPLIER 4
1.0 ID, DRAIN CURRENT (A) 3
VGS = 10V
0.8
0.6
2
VGS = 5V
0.4
1 RJA=50oC/W 0
0.2
0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
25
50
75
100
125
150
TA, AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 ZJA, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Ambient Temperature
RJA=50oC/W
PDM 0.1 t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 100 101 102 103
0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
200 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = 5V 10 VGS = 10V 3 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103 150 - TA 125
100 IDM, PEAK CURRENT (A)
Figure 4. Peak Current Capability
4 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
Typical Characteristics TA = 25C unless otherwise noted
100 10
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
STARTING TJ = 25oC
100s 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TA = 25oC 0.2 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 10ms
STARTING TJ = 150oC
1
RJA=50oC/W
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
15
15 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 10
VGS = 10V ID, DRAIN CURRENT (A) VGS = 5V 10
ID , DRAIN CURRENT (A)
VGS = 3.5V
5 TJ = 25oC
TJ = 150oC
5
VGS = 3V TA = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
TJ = 0 1.5 2.0 2.5
-55oC 0
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
VGS , GATE TO SOURCE VOLTAGE (V)
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
200 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0
Figure 8. Saturation Characteristics
rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
180
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
160 ID = 3.6A 140
1.5
120 ID = 1A
1.0
100 80 2
VGS = 10V, ID = 3.6A 0.5 4 6 8 10 -80 -40 0 40 80 120 160 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current
Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature
5 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
Typical Characteristics TA = 25C unless otherwise noted
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.2 ID = 250A
1.0
1.1
0.8
1.0
0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature
1000 CISS = CGS + CGD C, CAPACITANCE (pF)
Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 30V 8
6
100 CRSS = CGD COSS CDS + CGD
4
2
10 4 0.1 VGS = 0V, f = 1MHz 1 10 60
WAVEFORMS IN DESCENDING ORDER: ID = 3.6A ID = 1A 0 2 4 Qg, GATE CHARGE (nC) 6 8
0
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source Voltage
Figure 14. Gate Charge Waveforms for Constant Gate Currents
6 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
(T -T ) JM A P DM = -----------------------------R JA
maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. R JA = 79.9 + ------------------------------0.14 + Area
15
(EQ. 2)
(EQ. 1) The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
200 RJA = 79.9 + 15/(0.14+Area)
In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized
160 COPPER BOARD AREA - DESCENDING ORDER 0.020 in2 0.140 in2 0.257 in2 0.380 in2 0.493 in2
RJA (oC/W)
150
100
50 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) 10
Figure 21. Thermal Resistance vs Mounting Pad Area
IMPEDANCE (oC/W)
ZqJA, THERMAL
120
80
40
0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
Figure 22. Thermal Impedance vs Mounting Pad Area
7 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG VDD
+
BVDSS
VDS
VDD
IAS 0.01
0 tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS RL VDD VDS VGS Qg(TOT) VGS
VGS = 5V
+
VDD DUT Ig(REF) VGS = 1V 0
Qgs2
Qg(TH) Qgs Ig(REF) 0 Qgd
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
8 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
PSPICE Electrical Model
.SUBCKT HUFA76404DK8T 2 1 3 ; Ca 12 8 3.8e-10 Cb 15 14 3.8e-10 Cin 6 8 2.6e-10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 62.5 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 2.22e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 0.93e-9 RLgate 1 9 22.2 RLdrain 2 5 10 RLsource 3 7 9.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.4e-2 Rgate 9 20 103.3 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 5.4e-2 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*18),3.7))} .MODEL DbodyMOD D (IS=1.1E-12 N=1.03 RS=2.7e-2 TRS1=5.0e-4 TRS2=1.3e-6 + CJO=6.82e-10 M=0.85 TT=1.6e-8 XTI=4.0) .MODEL DbreakMOD D (RS=1.65 TRS1=1.0e-3 TRS2=-9e-6) .MODEL DplcapMOD D (CJO=1.7e-10 IS=1.0e-30 N=10 M=0.85) .MODEL MstroMOD NMOS (VTO=2.13 KP=19 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL MmedMOD NMOS (VTO=1.81 KP=1.08 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=103.3 T_ABS=25) .MODEL MweakMOD NMOS (VTO=1.59 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=103.3e1 RS=0.1 T_ABS=25) .MODEL RbreakMOD RES (TC1=1.12e-3 TC2=-3e-7) .MODEL RdrainMOD RES (TC1=1.0e-2 TC2=5e-5) .MODEL RSLCMOD RES (TC1=2.8e-3 TC2=1.9e-5) .MODEL RsourceMOD RES (TC1=4e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2.1e-3 TC2=-3.3e-6) .MODEL RvtempMOD RES (TC1=-1.6e-3 TC2=1.0e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-1) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-0.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
GATE 1 RLGATE CIN
rev March 2004
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2
RSLC2
5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 -
9 HUFA76404DK8T Rev. B
+
DBODY
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HUFA76404DK8T N-Channel Dual MOSFET
SABER Electrical Model
REV March 2004 template HUFA76404DK8T n2,n1,n3=m_temp number m_temp=25 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.1e-12,nl=1.03,rs=2.7e-2,trs1=5.0e-4,trs2=1.3e-6,cjo=6.82e-10,m=0.85,tt=1.6e-8,xti=4.0) dp..model dbreakmod = (rs=1.65,trs1=1.0e-3,trs2=-9e-6) dp..model dplcapmod = (cjo=1.7e-10,isl=10.0e-30,nl=10,m=0.85) m..model mstrongmod = (type=_n,vto=2.13,kp=19,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=1.81,kp=1.08,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.59,kp=0.04,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-1) DPLCAP 5 sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1,voff=-4) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.5) 10 RLDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-0.5) RSLC1 51 c.ca n12 n8 = 3.8e-10 RSLC2 c.cb n15 n14 = 3.8e-10 ISCL c.cin n6 n8 = 2.6e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 62.5GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 2.22e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 0.93e-9
CA 12 S1B 13 + EGS 6 8 EDS LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO CIN 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 DBREAK 11 DBODY
DRAIN 2
RLGATE
LSOURCE 7 RLSOURCE SOURCE 3
RSOURCE S1A 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19
res.rlgate n1 n9 = 22.2 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 9.3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp res.rbreak n17 n18 = 1, tc1=1.12e-3,tc2=-3e-7 res.rdrain n50 n16 = 2.4e-2, tc1=1.8e-2,tc2=5e-5 res.rgate n9 n20 = 103.3 res.rslc1 n5 n51 = 1.0e-6, tc1=2.8e-3,tc2=1.9e-5 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 5.4e-2, tc1=4e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.1e-3,tc2=-3.3e-6 res.rvtemp n18 n19 = 1, tc1=-1.6e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/18))** 3.7)) }
10 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
SPICE Thermal Model
REV March 2004 HUFA76404DK8T Copper Area =0.5 in2 CTHERM1 TH 8 1.2e-4 CTHERM2 8 7 4.6e-3 CTHERM3 7 6 5.0e-3 CTHERM4 6 5 1.6e-2 CTHERM5 5 4 4.5e-2 CTHERM6 4 3 1.3e-1 CTHERM7 3 2 6.7e-1 CTHERM8 2 TL 5.5 RTHERM1 TH 8 1.55 RTHERM2 8 7 1.9 RTHERM3 7 6 2.8 RTHERM4 6 5 9.8 RTHERM5 5 4 19 RTHERM6 4 3 22 RTHERM7 3 2 23 RTHERM8 2 TL 24
RTHERM1
th
JUNCTION
CTHERM1
8
RTHERM2
CTHERM2
7
RTHERM3
CTHERM3
6
RTHERM4
CTHERM4
SABER Thermal Model
Copper Area = 0.5 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =1.2e-4 ctherm.ctherm2 8 7 =4.6e-3 ctherm.ctherm3 7 6 =5.0e-3 ctherm.ctherm4 6 5 =1.6e-2 ctherm.ctherm5 5 4 =4.5e-2 ctherm.ctherm6 4 3 =1.3e-1 ctherm7 3 2 6.7e-1 ctherm8 2 tl 5.5 rtherm.rtherm1 th 8 =1.55 rtherm.rtherm2 8 7 =1.9 rtherm.rtherm3 7 6 =2.8 rtherm.rtherm4 6 5 =9.8 rtherm.rtherm5 5 4 =19 rtherm.rtherm6 4 3 =22 rtherm.rtherm7 3 2 =23 rtherm.rtherm8 2 tl =24 }
5 RTHERM5 CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
CTHERM7
2
RTHERM8
CTHERM8
tl
AMBIENT
Table 1. Thermal Models
COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.02 in2 9.0e-1 4.0e-1 1.4 39 42 48 0.14 in2 1.3e-1 6.0e-1 2.5 26 32 35 0.257 in2 1.5e-1 4.5e-1 2.2 20 31 38 0.38 in2 1.5e-1 6.5e-1 3.0 20 29 31 0.493 in2 1.3e-1 6.7e-1 5.5 22 23 24
11 HUFA76404DK8T Rev. B
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HUFA76404DK8T N-Channel Dual MOSFET
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I15
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
12 HUFA76404DK8T Rev. B
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