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| Preliminary Features * * * * * * * * HTG1390 4-bit Microcontroller * * * * * * * * Operating voltage: 1.2V~1.8V 7 input lines 3 output lines Halt feature reduces power consumption Up to 16s instruction cycle with 256kHz system clock at VDD=1.5V All instructions in 1 or 2 machine cycles 4Kx8 program ROM Data memory RAM size 128x4 bits 27x3 segment LCD driver 8-bit table read instruction 5 working registers Internal timer overflow interrupt One level subroutine nesting RC oscillator for system clock 8-bit timer with internal clock source Sound effect circuit General Description The HTG1390 is the processor from Holtek's 4-bit stand alone single chip microcontroller range specifically designed for LCD product applications. The device is ideally suited for multiple LCD low power applications among which are calculators, scales, and hand held LCD products. 1 17th Nov '98 Preliminary Block Diagram HTG1390 Notes: ACC: Accumulator PC: Program counter R0~R4: Working registers PA: Output port PS,PP: Input ports 2 17th Nov '98 Preliminary Pad Assignment HTG1390 Chip size: 1960 x 2300 (m)2 * The IC substrate should be connected to VSS in the PCB layout artwork. 3 17th Nov '98 Preliminary Pad Coordinates Pad No. 1 2 3* 4* 5 6 7 8 9* 10* 11 12 13 14 15 16 17 18 19* 20* 21* 22* 23 24 25 26 Unit: m HTG1390 X -843.74 -843.74 -843.74 -843.74 -843.74 -843.74 -843.74 -843.74 -843.74 -843.74 -843.74 -843.74 -843.74 -798.04 -668.04 -415.94 -287.94 -154.74 -25.94 107.26 236.26 398.66 518.66 638.66 853.56 853.56 Y 866.29 674.39 554.39 434.39 314.39 194.39 74.39 -45.61 -165.61 -285.61 -405.61 -525.61 -645.61 -856.71 -882.11 -809.01 -853.41 -853.41 -853.41 -853.41 -853.41 -940.91 -940.91 -940.91 -884.11 -764.11 Pad No. 27* 28* 29* 30* 31* 32* 33 34* 35* 36* 37* 38* 39* 40* 41* 42* 43* 44* 45* 46* 47* 48* 49* 50* 51* 52* X 853.56 853.56 853.56 853.56 853.56 853.56 853.56 853.56 853.56 853.56 853.56 853.56 838.76 718.76 598.76 478.76 358.76 238.76 118.76 -1.24 -121.24 -241.24 -361.24 -481.24 -601.24 -721.24 Y -644.11 -524.11 -404.11 -284.11 -164.11 -44.11 75.89 195.89 315.89 435.89 555.89 675.89 935.39 935.39 935.39 935.39 935.39 935.39 935.39 935.39 935.39 935.39 935.39 935.39 935.39 935.39 These pins must be bonded out for functional testing. 4 17th Nov '98 Preliminary Pad Description Pad No. 17, 18 8 9 5~7 10~13 16 15 14 19~21 HTG1390 Pad Name BZ,BZ TEST1 TEST2 COM2~COM0 PS3~PS0 VSS OSCI OSCO PA2~PA0 I/O Mask Option O I I O I I I O O Note 1 Function Sound effect outputs For test mode only TEST1 and TEST2 are left open when the HTG1390 is in normal operation (with an internal pull high resistor). Output for LCD panel common plate -- Note 2 Pull-high or 4-bit port for input only None. Note 3 -- -- CMOS or NMOS Open Drain Negative power supply, GND OSCI,OSCO are connected to an external resistor for an internal system clock 3-bit latch port for output only 22~24 25 26~52 1 4 2, 3 PP0~PP2 RES SEG0~SEG26 VDD V3 C1, C2 I I O I I I Pull-high or 3-bit port for input only None. Note 2 -- -- -- -- -- Input to reset an internal LSI Reset is active on logical low level LCD driver outputs for LCD panel segment Positive power supply LCD system power 1/2 bias generated LCD system voltage booster condensor connecting terminal Notes: The system clock provides 6 different sources selectable by mask option to drive the sound effect clock. If the Holtek sound library is used only 128K and 64K are acceptable. Each bit of ports PS and PP can be a trigger source of the HALT interrupt, selectable by mask option. Absolute Maximum Ratings* Supply Voltage ................................. -0.3V~5.5V Storage Temperature.................... -50C~125C Input Voltage.....................VSS-0.3V~VDD+0.3V Operating Temperature...................... 0C~70C *Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. 5 17th Nov '98 Preliminary D.C. Characteristics Symbol VDD IDD ISTB VIL VIH IOL1 IOH1 IOL2 IOH2 RPH HTG1390 Ta=25C Parameter VDD Operating Voltage Operating Current Standby Current Input Low Voltage Input High Voltage -- 1.5V 1.5V 1.5V 1.5V Test Conditions Conditions -- No load, fSYS=256kHz No load, HALT mode -- -- Min. Typ. 1.2 -- -- 0 1.0 95 600 100 -20 30 1.5 20 -- -- -- 100 700 150 -40 -- Max. Unit 1.8 -- 1 0.4 1.5 -- -- -- -- 300 V A A V V A A A A Port A, BZ & BZ Output Sink V =1.5V, 1.5V DD Current VOL=0.15V Port A, BZ & BZ Output Source Current Segment Output Sink Current Segment Output Source Current Pull-high Resistance 1.5V VDD=1.5V, VOH=1.35V 1.5V VLCD=3V, VOL=0.3V 1.5V VLCD=3V, VOH=2.7V 1.5V PS, PP, RES k Ta=25C A.C. Characteristics Symbol fSYS fLCD tCOM tCY tRES fSOUND Parameter System Clock LCD Clock LCD Common Period Cycle Time Reset Pulse Width Sound Effect Clock Test Conditions VDD Conditions Min. 38 -- -- -- 5 -- Typ. -- 128* (1/fLCD)x3 16 -- 64 or 128 ** Max. 400 -- -- -- -- -- Unit kHz Hz s s 1.5V R:36k~2M 1.5V -- -- -- -- -- 1/3 duty fSYS=256kHz -- -- ms kHz Notes: * In general, fLCD is selected and optimized by Holtek depending upon fSYS and the operating voltage. ** Only these two clocking signal frequencies are supported by the Holtek sound library. 6 17th Nov '98 Preliminary System Architecture Program counter - PC HTG1390 This counter addresses the program ROM and is arranged as an 12-bit binary counter from PC0 to PC11 whose contents specify a maximum of 4096 addresses. The program counter counts with an increment of 1 or 2 with each execution of an instruction. When executing the jump instruction (JMP, JNZ, JC, JTMR,...), a subroutine call, initial reset, internal interrupt, external interrupt or returning from a subroutine, the program counter is loaded with the corresponding instruction data as shown in the table. Notes: P0~P11: Instruction code @: PC11 keeps current value S0~S11: Stack register bits Program memory - ROM Program memory * Location 8 Activating the PS or PP input pins of the processor with the interrupts enabled during Halt mode causes the program to jump to this location. * Locations n00H to nFFH The program memory is the executable memory and is arranged in a 4096x8 bit format. The address is specified by the program counter (PC). Four special locations are reserved as described as follows. * Location 0 Activating the processor RES pin causes the first instruction to be fetched from location 0. * Location 4 Contains the timer interrupt resulting from a TIMER overflow. If the interrupts are enabled it causes the program to jump to this subroutine. These are the 256 bytes of each page in program memory. This area from n00H to nFFH and F00H to FFFH can be used as a look-up table. Instructions such as READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or to ACC and a data memory address specified by the register pair R1,R0. However as R1,R0 can only store 8 bits, these instructions cannot fully specify the full 12 bit program memory address. For this reason a jump instruction should be first used to place the program counter in the right page. The above instructions can then be used to read the look up table data. Mode Initial reset Internal interrupt External interrupt Jump, call instruction Conditional branch Return from subroutine Program Counter PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 0 0 P11 @ S11 0 0 0 P10 P10 S10 0 0 0 P9 P9 S9 0 0 0 P8 P8 S8 0 0 0 P7 P7 S7 0 0 0 P6 P6 S6 0 0 0 P5 P5 S5 0 0 0 P4 P4 S4 0 0 1 P3 P3 S3 0 1 0 P2 P2 S2 0 0 0 P1 P1 S1 0 0 0 P0 P0 S0 Program memory 7 17th Nov '98 Preliminary Note that the page number n must be greater than zero as some locations in page 0 are reserved for specific usage as mentioned. This area may function as normal program memory as required. The program memory mapping is shown in the diagram. In the execution of an instruction the program counter is added before the execution phase, so careful manipulation of READ MR0A and READ R4A is needed in the page margin. Stack register HTG1390 There are two areas in the data memory, the temporary data area and the display data area. Access to the temporary data area is from 00H to 7FH. Locations E0H to FAH represent the display data area. The locations between the temporary and display data areas are undefined and cannot be used. When data is written into the display data area it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. The stack register is a group of registers used to save the contents of the program counter (PC) and is arranged in 13 bitsx1 level. One bit is used to store the carry flag. An interrupt will force the contents of the PC and the carry flag onto the stack register. A subroutine call will also cause the PC contents to be pushed onto the stack; however the carry flag will not be stored. At the end of a subroutine or an interrupt (indicated by a return instruction RET or RETI), the contents of the stack register are returned to the PC. Executing "RETI" instruction will restore the carry flag from stack register, but "RET" doesn't. Working registers - R0,R1,R2,R3,R4 Data memory Accumulator - ACC There are 5 working registers (R0,R1,R2,R3, R4) usually used to store the frequently accessed intermediate results. Using the instructions INC Rn and DEC Rn the working registers can increment (+1) or decrement (-1). The JNZ Rn (n=0,1,4) instruction makes efficient use of the working registers as a program loop counter. Also the register pairs R0,R1 and R2,R3 are used as a data memory pointer when the memory transfer instruction is executed. Data memory - RAM The accumulator is the most important data register in the processor. It is one of the sources of input to the ALU and the destination of the results of the operations performed in the ALU. Data to and from the I/O ports and memory also passes through the accumulator. Arithmetic and logic unit - ALU This circuit performs the following arithmetic and logical operations ... * Add with or without carry * Subtract with or without carry * AND, OR, Exclusive-OR * Rotate right, left through carry * BCD decimal adjust for addition * Increment, decrement * Data transfers * Branch decisions The static data memory (RAM) is arranged in 256x4 bit format and is used to store data. All of the data memory locations are indirectly addressable through the register pair R1,R0 or R3,R2; for example MOV A,[R3R2] or MOV [R3R2],A. 8 The ALU not only outputs the results of data operations, but also sets the status of the carry flag (CF) in some instructions. 17th Nov '98 Preliminary Timer HTG1390 The HTG1390 contains a programmable 8-bit countup counter which can be used as a clock to generate an accurate time base. The Timer may be set and read with software instructions and stopped by a hardware reset or a TIMER OFF instruction. To restart the timer load the counter with the value XXH and then issue a TIMER ON instruction. Note that XX is the desired start count immediate value of the 8 bits. Once the Timer/Counter is started it increments to a maximum count of FFH and then overflows to zero (00H). It then continues to count until stopped by a TIMER OFF instruction or a reset. The increment from the maximum count of FFH to a zero (00H) triggers a timer flag TF and an internal interrupt request. The interrupt may be enabled or disabled by executing the EI and DI instruction. If the interrupt is enabled the timer overflow will cause a subroutine call to location 4. The state of the timer flag is also testable with the conditional jump instruction JTMR. The timer flag is cleared after the interrupt or the JTMR instruction is executed. If an internal source is used the frequency is determined by the system clock and the parameter n as defined in the equation. The frequency of the internal frequency source can be selected by mask option. Frequency of TIMER clock = system clock 2n where n=0,1,2 ...13 selectable by mask option. Note that n cannot have the value of 6, which is reserved for internal use. Interrupt Likewise when the timer flag is set in the enable interrupt mode and the program is not within a CALL subroutine the internal interrupt is activated. This causes a subroutine call to location 4 and resets the timer flag. When running under a CALL subroutine or DI the interrupt acknowledge is on hold until the RET or EI instruction is invoked. The CALL instruction should not be used within an interrupt routine as unpredictable behaviour may occur. If within a CALL subroutine internal interrupt occur, the internal interrupt will be serviced after leaving the CALL subroutine. The interrupts are disabled by a hardware reset or a DI instruction. They remain disabled until the EI instruction is executed. Each input port pin can be programmed by mask option to have an external interrupt function in the HALT mode. Initial reset The HTG1390 provides an RES pin for system initialization. This pin is equipped with an internal pull high resistor and in combination with an external 0.1~1F capacitor, provides an internal reset pulse of sufficient length to guarantee a reset to all internal circuits. If the reset pulse is generated externally, the RES pin must be held low for at least 5ms. Normal circuit operation will not commence until the RES pin returns high. The reset performs the following functions: PC TIMER Time flag Stop 000H Reset (Low) Sound off and one sing mode high (or floating state) Disabled Low level The HTG1390 provides both internal and external interrupt modes. The DI and EI instructions are used to disable and enable the interrupts. During Halt mode, if the PP or PS input pin is triggered on a high to low transition in the enable interrupt mode and the program is not within a CALL subroutine, the external interrupt is actived. This causes a subroutine call to location 8 and resets the interrupt latch. 9 SOUND Output Port A Interrupt BZ and BZ output 17th Nov '98 Preliminary Halt HTG1390 system clock 2m This is a special feature of the HTG1390. It will stop the chip's normal operation and reduce power consumption. When the instruction "HALT" is executed, then * The system clock will be stopped * The contents of the on-chip RAM and regis- Frequency of sound effect circuit = ...where m=0,1,2,3,4,5. Holtek's sound library supports only sound clock frequencies of 128K or 64K. To use Holtek's sound library the proper system clock and mask option should be selected. LCD display memory ters remain unchanged * LCD segments and commons keep 2VDD volt- age (i.e. LCD becomes blank) The system can escape HALT mode by ways of initial reset or external interrupt and wake-up from the following entry of program counter value. * Initial reset: 000H. * Interrupt (enabled): 008H * Interrupt (disabled): next address of HALT As mentioned in the data memory section the LCD display memory is embedded in the data memory. It can be read and written to in the same way as normal data memory. The figures show the mapping between the display memory and LCD pattern for the HTG1390. To turn the display on or off a 1/0 is written to the corresponding bit of the display memory. The LCD display module may have any form as long as the number of commons does not exceed 3 and the number of segments does not exceed 27. instruction. In HALT mode, each bit of port PS, PP0~PP2, can be used as external interrupt by mask option to wake-up system. This signal is active in low-going transition. Sound effects The HTG1390 includes sound effect circuitry which offers up to 16 sounds with 3 tone, boom and noise effects. Holtek supports a sound library which has melodies, alarms, machine guns etc.. Whenever the instruction "SOUND n" or "SOUND A" is executed, the specified sound will begin. Whenever "SOUND OFF" is executed, it terminates the singing sound immediately. There are two singing modes, SONE mode and SLOOP mode activated by SOUND ONE and SOUND LOOP. In SONE mode the specified sound plays just once. In SLOOP mode the specified sound keeps re-playing. Since sounds 0~11 contain 32 notes and sounds 12~15 contain 64 notes the latter possesses better sound than the former. The frequency of the sound effect circuit can be selected by mask option. LCD display memory 10 17th Nov '98 Preliminary LCD driver output Interfacing HTG1390 All LCD segments are random after an initial clear. The bias voltage circuits of the LCD display is built-in and no external resistor is needed. The output number of the HTG1390 LCD driver is 27x3 which can directly drive an LCD with 1/3 duty cycle and 1/2 bias. The frequency of the LCD driving clock is fixed at about 128Hz. This is set by Holtek according to the application and cannot be changed. The HTG1390 microcontroller communicate with the outside world through 4-bit input port PS, 3-bit input port PP and one 4-bit output port PA. Input ports - PP, PS All ports can have internal pull high resistors determined by mask option. Every bit of the input ports PP and PS can be specified to be a trigger source to wake up the HALT interrupt by mask option . A high to low transition on one of these pins will wake up the device from a HALT status. LCD driver output Note: VLCD is produced by double voltage circuit, therefore its value is double by VDD. Oscillator Input ports PP and PS Output port - PA Only one external resistor is needed for the HTG1390 oscillator circuit. The system clock is also used as the reference signal of the LCD driving clock, sound effect clock and internal frequency source of TIMER. One HTG1390 machine cycle consists of a sequence of 4 states numbered T1 to T4. Each state lasts for one oscillator period. The machine cycle is 16s if the system frequency is up to 256kHz. A mask option is available to select whether the output is a CMOS or open drain NMOS type. After an initial clear the output port PA defaults to be high for CMOS or floating for NMOS. Output port PA RC oscillator 11 17th Nov '98 Preliminary Mask options HTG1390 * 8-bit programmable timer with external clock The following either/or options are available by mask option which the user must select prior to manufacture. * 4-bit input ports PP and PS with or without or internal frequency source. Thirteen internal frequency sources are available to provide an internal clock. Note that a value of n=6 cannot be used for the devices. * Six kinds of sound clock frequency: pull high resistors * Each bit of PP and PS can wake up the proc- fSYS/2m, m=0, 1, 2, 3, 4, 5 essor from a HALT state * Output Port PA to be CMOS or open drain NMOS Application Circuits R*: Depends on the required system clock frequency. (R=36k~2M, at VDD=1.5V) 12 17th Nov '98 Preliminary Instruction Set Summary Mnemonic Arithmetic ADD A,[R1R0] ADC A,[R1R0] SUB A,[R1R0] SBC A,[R1R0] ADD A,XH SUB A,XH DAA Logic Operation AND A,[R1R0] OR A,[R1R0] XOR A,[R1R0] AND [R1R0],A OR [R1R0],A XOR [R1R0],A AND A,XH OR A,XH XOR A,XH Increment & Decrement INC A INC Rn INC [R1R0] INC [R3R2] DEC A DEC Rn DEC [R1R0] DEC [R3R2] Data Move MOV A,Rn MOV Rn,A MOV A,[R1R0] MOV A,[R3R2] MOV [R1R0],A MOV [R3R2],A MOV A,XH MOV R1R0,XXH MOV R3R2,XXH MOV R4,XH Move register to ACC, n=0~4 Move ACC to register, n=0~4 Move data memory to ACC Move data memory to ACC Move ACC to data memory Move ACC to data memory Move immediate data to ACC Move immediate data to R1 and R0 Move immediate data to R3 and R2 Move immediate data to R4 1 1 1 1 1 1 1 2 2 2 Increment ACC Increment register, n=0~4 Increment data memory Increment data memory Decrement ACC Decrement register, n=0~4 Decrement data memory Decrement data memory 1 1 1 1 1 1 1 1 AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC 1 1 1 1 1 1 2 2 2 Add data memory to ACC Add data memory with carry to ACC Subtract data memory from ACC Subtract data memory from ACC with borrow Add immediate data to ACC Subtract immediate data from ACC Decimal adjust ACC for addition 1 1 1 1 2 2 1 HTG1390 Description Byte Cycle CF 1 1 1 1 2 2 1 1 1 1 1 1 1 2 2 2 -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 2 2 2 -- -- -- -- -- -- -- -- -- -- 13 17th Nov '98 Preliminary Mnemonic Rotate RL A RLC A RR A RRC A Input & Output IN A,Pi OUT PA,A Branch JMP addr JC addr JNC addr JTMR addr JAn addr JZ A,addr JNZ A,addr JNZ Rn,addr Subroutine CALL addr RET RETI Flag CLC STC EI DI NOP Timer TIMER XXH TIMER ON TIMER OFF MOV A,TMRL MOV A,TMRH MOV TMRL,A MOV TMRH,A Set 8 bits immediate data to TIMER Set TIMER start counting Set TIMER stop counting Move low nibble of TIMER to ACC Move high nibble of TIMER to ACC Move ACC to low nibble of TIMER Move ACC to hight nibble of TIMER 2 1 1 1 1 1 1 Clear carry flag Set carry flag Enable interrupt Disable interrupt No operation 1 1 1 1 1 Subroutine call Return from subroutine or interrupt Return from interrupt service routine 2 1 1 Jump unconditionally Jump on carry=1 Jump on carry=0 Jump on timer overflow Jump on ACC bit n=1 Jump on ACC is zero Jump on ACC is not zero Jump on register Rn not zero, n=0,1,4 2 2 2 2 2 2 2 2 Input port-i to ACC ,port-i=PS,PP Output ACC to port-A 1 1 Rotate ACC left Rotate ACC left through the carry Rotate ACC right Rotate ACC right through the carry 1 1 1 1 HTG1390 Byte Cycle CF Description 1 1 1 1 1 1 -- -- 2 2 2 2 2 2 2 2 -- -- -- -- -- -- -- -- 2 1 1 -- -- 1 1 1 1 1 0 1 -- -- -- 2 1 1 1 1 1 1 -- -- -- -- -- -- -- 14 17th Nov '98 Preliminary Mnemonic Table Read READ R4A READ MR0A READF R4A READF MR0A Sound Control SOUND n SOUND A SOUND ONE SOUND LOOP SOUND OFF Miscellaneous HALT Enter power down mode 2 Activate SOUND channel n Activate SOUND channel with ACC Turn on SOUND one cycle Turn on SOUND repeat cycle Turn off SOUND 2 1 1 1 1 Read ROM code of current page to R4 & ACC Read ROM code of current page to M(R1,R0), ACC Read ROM code of page F to R4 & ACC Read ROM code of page F to M(R1,R0),ACC 1 1 1 1 HTG1390 Byte Cycle CF Description 2 2 2 2 -- -- -- -- 2 1 1 1 1 -- -- -- -- -- 2 -- 15 17th Nov '98 Preliminary Instruction Definitions ADC A,[R1R0] HTG1390 Add data memory contents and carry to accumulator 00001000 The contents of the data memory addressed by the register pair "R1,R0" and the carry are added to the accumulator. Carry is affected. ACC ACC+M(R1,R0)+CF Add immediate data to accumulator 01000000 0000dddd The specified data is added to the accumulator. Carry is affected. ACC ACC+XH Add data memory contents to accumulator 00001001 The contents of the data memory addressed by the register pair "R1,R0" is added to the accumulator. Carry is affected. ACC ACC+M(R1,R0) Logical AND immediate data to accumulator 01000010 0000dddd Data in the accumulator is logically ANDed with the immediate data specified by the code. ACC ACC "AND" XH Logical AND accumulator with data memory 00011010 Data in the accumulator is logically ANDed with the data memory addressed by the register pair "R1,R0". ACC ACC "AND" M(R1,R0) Logical AND data memory with accumulator 00011101 Data in the data memory addressed by the register pair "R1,R0" is logically ANDed with the accumulator M(R1,R0) M(R1,R0) "AND" ACC Machine code Description Operation ADD A,XH Machine code Description Operation ADD A,[R1R0] Machine code Description Operation AND A,XH Machine code Description Operation AND A,[R1R0] Machine code Description Operation AND [R1R0],A Machine code Description Operation 16 17th Nov '98 Preliminary CALL address HTG1390 Subroutine call 1111aaaa aaaaaaaa The program counter bits 0~11 are saved in the stack and the specified address loaded into the program counter. Stack PC+2 PC address Clear carry flag 00101010 The carry flag is reset to zero. CF 0 Decimal-Adjust accumulator 00110110 The accumulator value is adjusted to BCD (Binary Code Decimal), if the contents of the accumulator is greater than 9 or CF (Carry flag) is one. If ACC>9 or CF=1 then ACC ACC+6, CF 1 else ACC ACC, CF CF Decrement accumulator 00111111 Data in the accumulator is decremented by one. Carry flag is not affected. ACC ACC-1 Decrement register 0001nnn1 Data in the working register "Rn" is decremented by one. Carry flag is not affected. Rn Rn-1; Rn=R0,R1,R2,R3,R4, for nnn=0,1,2,3,4 Decrement data memory 00001101 Data in the data memory specified by the register pair "R1,R0" is decremented by one. Carry flag is not affected. M(R1,R0) M(R1,R0)-1 Machine code Description Operation CLC Machine code Description Operation DAA Machine code Description Operation DEC A Machine code Description Operation DEC Rn Machine code Description Operation DEC [R1R0] Machine code Description Operation 17 17th Nov '98 Preliminary DEC [R3R2] HTG1390 Decrement data memory 00001111 Data in the data memory specified by the register pair "R3,R2" is decremented by one. Carry flag is not affected. M(R3,R2) M(R3,R2)-1 Disable interrupt 00101101 Internal time-out interrupt and external interrupt are disabled. Enable interrupt 00101100 Internal time-out interrupt and external interrupt are enabled. Halt system clock 00110111 PC PC+2 Input port to accumulator PS PP 00110011 00110100 00111110 Turn off system clock, and enter power down mode. Machine code Description Operation DI Machine code Description EI Machine code Description HALT Machine code Description Operation IN A,Pi Machine code Description Operation INC A The data on port "Pi" is transferred to the accumulator. ACC Pi; Pi=PS or PP Increment accumulator 00110001 Data in the accumulator is incremented by one. Carry flag is not affected. ACC ACC+1 Increment register 0001nnn0 Data in the working register "Rn" is incremented by one. Carry flag is not affected. Rn Rn+1; Rn=R0~R4 for nnn=0~4 Machine code Description Operation INC Rn Machine code Description Operation 18 17th Nov '98 Preliminary INC [R1R0] HTG1390 Increment data memory 00001100 Data in the data memory specified by the register pair "R1,R0" is incremented by one. Carry flag is not affected. M(R1,R0) M(R1,R0)+1 Increment data memory 00001110 Data memory specified by the register pair "R3,R2" is incremented by one. Carry flag is not affacted. M(R3,R2) M(R3,R2)+1 Jump if accumulator bit n is set 100nnaaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if accumulator bit n is set to one. PC (bit 0~10) address, if ACC bit n=1(n=0~3) PC PC+2, if ACC bit n=0 Jump if carry is set 11000aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the CF (Carry flag) is set to one. PC (bit 0~10) address, if CF=1 PC PC+2, if CF=0 Direct jump 1110aaaa aaaaaaaa Bits 0~11 of the program counter are replaced with the directly-specified address. PC address Jump if carry is not set 11001aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address and bit 11 of the program counter is unaffected, if the CF (Carry flag) is set to zero. PC (bit 0~10) address, if CF=0 PC PC+2, if CF=1 Machine code Description Operation INC [R3R2] Machine code Description Operation JAn address Machine code Description Operation JC address Machine code Description Operation JMP address Machine code Description Operation JNC address Machine code Description Operation 19 17th Nov '98 Preliminary JNZ A,address HTG1390 Jump if accumulator is not zero 10111aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the accumulator is not zero. PC (bit 0~10) address, if ACC0 PC PC+2, if ACC=0 Jump if register is not zero R0 R1 R4 10100aaa 10101aaa 11011aaa aaaaaaaa aaaaaaaa aaaaaaaa Machine code Description Operation JNZ Rn,address Machine code Description Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the register is not zero. PC (bit 0~10) address, if Rn0; Rn=R0,R1,R4 PC PC+2, if Rn=0 Jump if time-out 11010aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the TF (Timer flag) is set to one. PC (bit 0~10) address, if TF=1 PC PC+2, if TF=0 Jump if accumulator is zero 10110aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address but bit 11 of the program counter is unaffected, if the accumulator is zero. PC (bit 0~10) address, if ACC=0 PC PC+2, if ACC0 Move register to accumulator 0010nnn1 Data in the working register "Rn" is moved to the accumulator. ACC Rn; Rn=R0~R4, for nnn=0~4 Operation JTMR address Machine code Description Operation JZ A,address Machine code Description Operation MOV A,Rn Machine code Description Operation 20 17th Nov '98 Preliminary MOV A,TMRH HTG1390 Move timer high nibble to accumulator 00111011 The high nibble data of the timer counter is loaded to the accumulator. ACC TIMER (high nibble) Move timer low nibble to accumulator 00111010 The low nibble data of the timer counter is loaded to the accumulator. ACC TIMER (low nibble) Move immediate data to accumulator 0111dddd The 4-bit data specified by the code is loaded to the accumulator. ACC XH Move data memory to accumulator 00000100 Data in the data memory specified by the register pair "R1,R0" is moved to the accumulator. ACC M(R1,R0) Move data memory to accumulator 00000110 Data in the data memory specified by the register pair "R3,R2" is moved to the accumulator. ACC M(R3,R2) Move immediate data to R1 and R0 0101dddd 0000dddd The 8-bit data specified by the code is loaded to the working registers R1 and R0, the high nibble of the data is loaded to R1, and the low nibble to R0. R1 XH (high nibble) R0 XH (low nibble) Move immediate data to R3 and R2 0110dddd 0000dddd The 8-bit data specified by the code is loaded to the working registers R3 and R2, the high nibble of the data is loaded to R3, and the low nibble to R2. R3 XH (high nibble) R2 XH (low nibble) 21 17th Nov '98 Machine code Description Operation MOV A,TMRL Machine code Description Operation MOV A,XH Machine code Description Operation MOV A,[R1R0] Machine code Description Operation MOV A,[R3R2] Machine code Description Operation MOV R1R0,XXH Machine code Description Operation MOV R3R2,XXH Machine code Description Operation Preliminary MOV R4,XH HTG1390 Move immediate data to R4 01000110 R4 XH Move accumulator to register 0010nnn0 Data in the accumulator is moved to the working register "Rn". Rn ACC; Rn=R0~R4, for nnn=0~4 Move accumulator to timer high nibble 00111101 The contents of the accumulator is loaded to the high nibble of the timer counter. TIMER(high nibble) ACC Move accumulator to timer low nibble 00111100 The contents of the accumulator is loaded to the low nibble of the timer counter. TIMER(low nibble) ACC Move accumulator to data memory 00000101 Data in the accumulator is moved to the data memory specified by the register pair "R1,R0". M(R1,R0) ACC Move accumulator to data memory 00000111 Data in the accumulator is moved to the data memory specified by the register pair "R3,R2". M(R3,R2) ACC No operation 00111110 Do nothing, but one instruction cycle is delayed. 0000dddd The 4-bit data specified by the code is loaded to the working register R4. Machine code Description Operation MOV Rn,A Machine code Description Operation MOV TMRH,A Machine code Description Operation MOV TMRL,A Machine code Description Operation MOV [R1R0],A Machine code Description Operation MOV [R3R2],A Machine code Description Operation NOP Machine code Description 22 17th Nov '98 Preliminary OR A,XH HTG1390 Logical OR immediate data to accumulator 01000100 0000dddd Data in the accumulator is logically ORed with the immediate data specified by the code. ACC ACC "OR" XH Logical OR accumulator with data memory 00011100 Data in the accumulator is logically ORed with the data memory addressed by the register pair "R1,R0". ACC ACC "OR" M(R1,R0) Logically OR data memory with accumulator 00011111 Data in the data memory addressed by the register pair "R1,R0" is logically ORed with the accumulator. M(R1,R0) M(R1,R0) "OR" ACC Output accumulator data to port A 00110000 The data in the accumulator is transferred to port PA and latched. PA ACC Read ROM code of current page to M(R1,R0) and ACC 01001110 The 8-bit ROM code (current page) addressed by ACC and R4 is moved to the data memory M(R1,R0) and the accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code is specified as below: Current page ROM code address bit 11~8 ACC ROM code address bit 7~4 R4 ROM code address bit 3~0 M(R1,R0) ROM code (high nibble) ACC ROM code (low nibble) Machine code Description Operation OR A,[R1R0] Machine code Description Operation OR [R1R0],A Machine code Description Operation OUT PA,A Machine code Description Operation READ MR0A Machine code Description Operation 23 17th Nov '98 Preliminary READ R4A HTG1390 Read ROM code of current page to R4 and accumulator 01001100 The 8-bit ROM code (current page) addressed by ACC and M(R1,R0) is moved to the working register R4 and the accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code is specified as below: Current page ROM code address bit 11~8 ACC ROM code address bit 7~4 M(R1,R0) ROM code address bit 3~0 R4 ROM code (high nibble) ACC ROM code (low nibble) Read ROM Code of page F to M(R1,R0) and ACC 01001111 The 8-bit ROM code (page F) addressed by ACC and R4 is moved to the data memory M(R1,R0) and the accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. Page F ROM code address bit 11~8 are "1111" ACC ROM code address bit 7~4 R4 ROM code address bit 3~0 M(R1,R0) high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Read ROM code of page F to R4 and accumulator 01001101 The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) is moved to the working register R4 and the accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. Page F ROM code address bit 11~8 are "1111" ACC ROM code address bit 7~4 M(R1,R0) ROM code address bit 3~0 R4 high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Return from subroutine or interrupt 00101110 The program counter bits 0~11 are restored from the stack. PC Stack Machine code Description Operation READF MR0A Machine code Description Operation READF R4A Machine code Description Operation RET Machine code Description Operation 24 17th Nov '98 Preliminary RETI HTG1390 Return from interrupt subroutine 00101111 The program counter bits 0~11 are restored from the stack. The carry flag before entering the interrupt service routine is restored. PC Stack CF CF (before interrupt service routine) Rotate accumulator left 00000001 The contents of the accumulator are rotated left one bit. Bit 3 is rotated to both bit 0 and the carry flag. An+1 An, An: accumulator bit n (n=0,1,2) A0 A3 CF A3 Rotate accumulator left through carry 00000011 The contents of the accumulator are rotated left one bit. Bit 3 replaces the carry bit, which is rotated into the bit 0 position. An+1 An, An: Accumulator bit n (n=0,1,2) A0 CF CF A3 Rotate accumulator right 00000000 The contents of the accumulator are rotated right one bit. Bit 0 is rotated to both bit 3 and the carry flag. An An+1, An: Accumulator bit n (n=0,1,2) A3 A0 CF A0 Rotate accumulator right through carry 00000010 The contents of the accumulator are rotated right one bit. Bit 0 replaces the carry bit, which bit is rotated into the bit 3 position. An An+1, An: Accumulator bit n (n=0,1,2) A3 CF CF A0 Machine code Decription Operation RL A Machine code Description Operation RLC A Machine code Description Operation RR A Machine code Description Operation RRC A Machine code Description Operation 25 17th Nov '98 Preliminary SBC A,[R1R0] HTG1390 Subtract data memory contents and carry from ACC 00001010 The contents of the data memory addressed by the register pair "R1,R0" and the complement of the carry are subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+M(R1,R0)+CF Activate SOUND channel with accumulator 01001011 The activated sound begins playing in accordance with the contents of accumulator when the specified sound channel is matched. Turn on sound repeat cycle 01001001 The activated sound plays repeatedly. Turn off sound 01001010 The activated sound will terminate immediately. Turn on sound one cycle 01001000 The activated sound plays once. Activate SOUND channel n 01000101 0000nnnn The specified sound begins playing and overwrites the previous activated sound. (nnnn=0~15) Set carry flag 00101011 The carry flag is set to one. CF 1 Subtract immediate data from accumulator 01000001 0000dddd The specified data is subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+XH+1 Machine code Description Operation SOUND A Machine code Description SOUND LOOP Machine code Description SOUND OFF Machine code Description SOUND ONE Machine code Description SOUND n Machine code Description STC Machine code Description Operation SUB A,XH Machine code Description Operation 26 17th Nov '98 Preliminary SUB A,[R1R0] HTG1390 Subtract data memory contents from accumulator 00001011 The contents of the data memory addressed by the register pair "R1,R0" is subtracted from the accumulator. Carry is set if a borrow does not take place in subtraction; otherwise carry is cleared. ACC ACC+M(R1,R0)+1 Set timer stop counting 00111001 The timer stops counting, when the "TIMER OFF" instruction is executed. Set timer start counting 00111000 The timer starts counting, when the "TIMER ON" instruction is executed. Set immediate data to timer counter 01000111 TIMER XXH Logical XOR immediate data to accumulator 01000011 0000dddd Data in the accumulator is Exclusive-ORed with the immediate data specified by the code. ACC ACC "XOR" XH Logical XOR accumulator with data memory 00011011 Data in the accumulator is Exclusive-ORed with the data memory addressed by the register pair "R1,R0". ACC ACC "XOR" M(R1,R0) Logical XOR data memory with accumulator 00011110 Data in the data memory addressed by the register pair "R1,R0" is logically Exclusive-ORed with the accumulator. M(R1,R0) M(R1,R0) "XOR" ACC dddddddd The 8-bit data specified by the code is loaded to the timer counter. Machine code Description Operation TIMER OFF Machine code Description TIMER ON Machine code Description TIMER XXH Machine code Description Operation XOR A,XH Machine code Description Operation XOR A,[R1R0] Machine code Description Operation XOR [R1R0],A Machine code Description Operation 27 17th Nov '98 |
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