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August 1997
Features
S IG N DES NEW at F OR D nter N D E I3 0 5 0 t C e /t s c E or OM M See H al Supp il.com REC ic ers c hn w w . i nt N OT r Te t ou I L or w c RS onta or c 8-INTE - 88 1
(R)
HI2307
Triple 10-Bit, 50 MSPS, RGB, 3-Channel D/A Converter
Description
The HI2307 is a triple 10-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 10-bit, pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. Each channel clock input can be controlled individually, or connected together as one. The HI2307 also has BLANK video control signal.
* Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 10-Bit * Maximum Conversion Speed . . . . . . . . . . . . . . . 50MHz * RGB 3-Channel Input/Output * Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB * Low Power Consumption . . . . . . . . . . . . .300mW (Max) * Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V * Low Glitch * Direct Replacement for Sony CXD2307
Ordering Information
PART NUMBER HI2307JCQ TEMP. RANGE ( oC) -20 to 75 PACKAGE 64 Ld MQFP PKG. NO. Q64.10x10-S
Applications
* Digital TV * Graphics Display * High Resolution Color Graphics * Video Reconstruction * Instrumentation * Image Processing * I/Q Modulation
Pinout
HI2307 (MQFP) TOP VIEW
R1 RO (LSB) DVDD AVDD AVDD BO BO AVDD AVDD GO GO AVDD AVDD RO RO AVSS 6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49 R2 R3 R4 R5 R6 R7 R8 R9 G0 (LSB) G1 G2 G3 G4 G5 G6 G7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VGB ROB VGG ROG VGR ROR VRB VRG VRR IRB IRG IRR AVSS VB DVSS BCK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 G8 G9 B0 (LSB) B1 B2 B3 B4 B5 B6 B7 B8 B9 BLK CE RCK GCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 10-1
File Number
4117.1
HI2307 Functional Block Diagram
62 DVDD (LSB) R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 (LSB) G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 (LSB) B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DECODER DECODER LATCHES 6 MSBs CURRENT CELLS DECODER DECODER CLOCK GENERATOR CURRENT CELLS FOR FULL SCALE 4 LSBs CURRENT CELLS LATCHES 6 MSBs CURRENT CELLS DECODER LATCHES DECODER CLOCK GENERATOR CURRENT CELLS FOR FULL SCALE 4 LSBs CURRENT CELLS + 6 MSBs CURRENT CELLS 4 LSBs CURRENT CELLS 60 AVDD 61 AVDD 44 VGR 50 RO 51 RO 31 RCK
43 ROR
-
40 VRR 37 IRR 56 AVDD 57 AVDD 46 VGG 54 GO 55 GO 32 GCK
45 ROG +
-
41 VRG 38 IRG 52 AVDD 54 AVDD 48 VGB 58 BO 59 BO 33 BCK
CLOCK GENERATOR CURRENT CELLS FOR FULL SCALE BIAS VOLTAGE GENERATOR +
47 ROB
-
42 VRB 39 IRB
BLK CE
29 30
35 VB 36 AVSS 49 AVSS 34 DVSS
10-2
HI2307 Pin Descriptions
NUMBER 63 to 8 9 to 18 19 to 28 SYMBOL R0 to R9 G0 to G9 B0 to B9
63
EQUIVALENT CIRCUIT
DVDD
DESCRIPTION Digital Input.
28 DVSS
29
BLK
DVDD
Blanking pin. No signal for High (0V output). Output generated for Low.
29
DVSS
35
VB
DVDD DVDD
Connect to DVSS with a capacitor of approximately 0.1F.
35
+ -
DVSS
31 32 33
RCK GCK BCK
31 32 33
DVDD
Clock pins. All input pins are TTL compatible.
DVSS
34 36, 49 30
DVSS AVSS CE
DVDD
Digital GND. Analog GND. Chip Enable pin. No signal for High (0V output) to minimize power consumption.
30
DVSS
52, 53, 56, 57, 60, 61
AVDD
Analog VDD .
10-3
HI2307 Pin Descriptions
NUMBER 43 45 47 44 46 48 37 38 39 40 41 42 SYMBOL ROR ROG ROB VGR VGG VGB IRR IRG IRB VRR VRG VRB
43 45 47
(Continued) EQUIVALENT CIRCUIT
AVDD
DESCRIPTION Connect to VGR, VGG, and VGB with the control method of output amplitude. See Application Circuit. Connect a capacitor of approximately 0.1F.
Connect to AVSS with a resistance of 3.3k.
AVSS AVDD 44 46 48 AVSS AVDD 37 38 39 AVSS
Set output fullscale value (2.0V).
+ -
AVDD 40 41 42 AVSS
50 54 58 51 55 59
RO GO BO RO GO BO
50 54 58
AVDD
Current output pins. Output can be retrieved by connecting a resistance of 200 to AVSS.
Reverse current output pins. Normally connect to AVSS.
AVSS AVDD
51 55 59
AVSS
62
DVDD
Digital VDD .
10-4
HI2307
Absolute Maximum Ratings TA = 25oC
Supply Voltage, V DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (for Each Channel), lOUT . . . . . . . . . . . . . 0 to 15mA
Thermal Information
Thermal Resistance (Typical, Note 7)
JA (oC/W)
Operating Conditions
Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DV DD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V Reference Input Voltage, VREF . . . . . . . . . . . . . . . . . . .0.5V to 2.0V Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Min) Temperature Range, TOPR . . . . . . . . . . . . . . . . . . . . -20oC to 75oC
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Resolution Maximum Conversion Speed Linearity Error Differential Linearity Error Output Full Scale Voltage Output Full Scale Ratio (Note 8) Output Full Scale Current Output Offset Voltage Supply Current Digital Input Current High Level Low Level
TA = 25oC, fCLK = 50MHz, VDD = 5V, ROUT = 200, VREF = 2.0V SYMBOL n fMAX EL ED VFS FSR IFS VOS IDD IIH IIL VOC tS tH tPD GE CT For 10MHz Sinewave Output For the Equal Gain TEST CONDITIONS MIN 50 -2.0 -0.5 1.8 0 -5 1.8 TYP 10 1.9 1.5 9.5 55 1.9 MAX 2.0 0.5 2.0 3 10 1 60 5 2.0 UNITS Bit MHz LSB LSB V % mA mV mA A A V
Precision Guaranteed Output Voltage Range Setup Time Hold Time Propagation Delay Time Glitch Energy Cross Talk NOTE:
-
5 1 10 100 54
7 3 -
ns ns ns pV-s dB
Full scale voltage of channel 2. Output Full Scale Ratio = ------------------------------------------------------------------------------------------------------------------------------ ( - 1 ) x 100(%) . Average of the full scale voltage of the channels
10-5
HI2307 I/O Correspondence Table
MSB
(Output Full Scale Voltage: 2.0V)
INPUT CODE LSB 2.0V OUTPUT VOLTAGE
1111111111 * * * 1000000000 * * * 0000000000
1.0V
0V
Timing Diagram
tPW1 tPW0
CLK tS tH tS tH tS tH
DATA
tPD 100%
D/ A OUT tPD tPD
50%
0%
Test Circuits
10 10-BIT COUNTER WITH LATCH 10 10 R0 TO R9 63 TO 8 G0 TO G9 9 TO 18 B0 TO B9 9 TO 28 GO GO HI2307 29 BLK 0.1 30 CE 35 VB DVSS CLK 50MHz SQUARE WAVE VGR TO VGB 44, 46, 48 ROR TO ROB 43, 45, 47 VRR TO VRB 40 TO 42 IRR TO IRB 37 TO 39 BO BO 60 61 AVDD 200 AVSS 56 57 AVSS RO RO 52 53 AVSS OSCILLOSCOPE 200 200
0.1
31 RCK 32 GCK 33 BCK
2V
3.3K
FIGURE 1. MAXIMUM CONVERSION RATE
10-6
HI2307 Test Circuits
(Continued)
10 10-BIT COUNTER WITH LATCH 10 10 R0 TO R9 63 TO 8 G0 TO G9 9 TO 18 B0 TO B9 9 TO 28 GO GO 56 57 AVSS 29 BLK DELAY CONTROLLER 0.1 30 CE 35 VB DVSS CLK 50MHz SQUARE WAVE DELAY CONTROLLER VGR TO VGB 44, 46, 48 ROR TO ROB 43, 45, 47 VRR TO VRB 40 TO 42 IRR TO IRB 37 TO 39 HI2307 BO BO 60 61 AVDD 200 AVSS
RO RO
52 53
200
AVSS OSCILLOSCOPE 200
0.1
31 RCK 32 GCK 33 BCK
2V
3.3K
FIGURE 2. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT
10-7
HI2307 Test Circuits
(Continued)
ALL "1" 10 DIGITAL WAVEFORM GENERATOR 10 10
R0 TO R9 63 TO 8 G0 TO G9 9 TO 18 B0 TO B9 9 TO 28
RO RO
50 51
200
AVSS GO GO 54 55 AVSS OSCILLOSCOPE 200
29 BLK 0.1 30 CE 35 VB DVSS CLK 50MHz SQUARE WAVE
HI2307
BO BO
58 59 AVDD 200 AVSS
31 RCK 32 GCK 33 BCK
VGR TO VGB 44, 46, 48 ROR TO ROB 43, 45, 47 VRR TO VRB 40 TO 42 IRR TO IRB 37 TO 39 3.3K 2V
0.1
FIGURE 3. CROSS TALK TEST CIRCUIT
Typical Performance Curves
80 CURRENT CONSUMPTION (mA) 60
CROSS TALK (dB)
70
60
50 VDD = 5.0V TA = 25 oC 40 100K 1M OUTPUT FREQUENCY (Hz) 10M
VDD = 5.0V fCLK = 50MHz VREF = 2.0V 50
-20
0
25
50
75
AMBIENT TEMPERATURE (oC)
FIGURE 4. OUTPUT FREQUENCY vs CROSS TALK
FIGURE 5. CURRENT CONSUMPTION vs AMBIENT TEMPERATURE
10-8
HI2307 Typical Performance Curves
1.9 FULLSCALE VOLTAGE (V)
(Continued)
VDD = 5.0V VREF = 2.0V 1.8
-20
0
25
50
75
AMBIENT TEMPERATURE (oC)
FIGURE 6. FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
Application Circuits
1k 0.1F NC 48 49 ROUT 200 50 51 52 53 GOUT 54 200 55 56 57 BOUT 200 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 HI2307 47 46 NC 45 44 43 42 41 40 NC NC 39 38
3.3k 0.1F
37
36 35
34
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DVDD DVSS
CLOCK INPUT
B CHANNEL INPUT
AVDD AVSS
12
13 14
15
16
R CHANNEL INPUT
G CHANNEL INPUT
FIGURE 7. GAIN EQUAL
10-9
HI2307 Application Circuits
(Continued)
3.3k 0.1F NC 48 49 ROUT 200 50 51 52 53 GOUT 54 200 55 56 57 BOUT 200 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HI2307 47 46 NC 45 44 43 42 41 40 1k 0.1F
NC NC 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DVDD DVSS
CLOCK INPUT
B CHANNEL INPUT
AVDD AVSS
R CHANNEL INPUT
G CHANNEL INPUT
FIGURE 8. GAIN INDEPENDENTLY
10-10

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