 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 2W POWER PHEMT * FEATURES 32.5 dBm Linear Output Power at 12 GHz 6.5 dB Power Gain at 12 GHz 8 dB Maximum Stable Gain at 12 GHz 42 dBm Output IP3 30% Power-Added Efficiency DRAIN BOND PAD (4X) SOURCE BOND PAD (2x) FPD3000 GATE BOND PAD (4X) * DESCRIPTION AND APPLICATIONS DIE SIZE (m): 830 x 470 DIE THICKNESS: 75 m BONDING PADS (m): >75 x 60 The FPD3000 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (PHEMT), featuring a 0.25 m by 3000 m Schottky barrier gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable high-power applications. The FPD3000 also features Si3N4 passivation and is available in a P100 flanged ceramic package and in the low cost plastic SOT89 plastic package. Typical applications include commercial and other narrowband and broadband high-performance amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. * ELECTRICAL SPECIFICATIONS AT 22C Parameter Power at 1dB Gain Compression Maximum Stable Gain (S21/S12) Power Gain at P1dB Power-Added Efficiency Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (see Notes) IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| JC Symbol P1dB SSG G1dB PAE IP3 Test Conditions VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS VDS = 8 V; IDS = 50% IDSS; POUT = P1dB VDS = 8V; IDS = 50% IDSS Matched for optimal power Tuned for best IP3 VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 3 mA IGS = 3 mA IGD = 3 mA VDS > 6V 12.0 14.5 750 42 44 930 1.5 800 10 1.0 14.0 16.0 20 1100 mA A mS A V V V C/W dBm Min 31.5 7.0 6.0 Typ 32.5 8.0 6.5 30 Max Units dBm dB dB % RF SPECIFICATIONS MEASURED AT f = 12 GHz USING CW SIGNAL Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 11/17/04 Email: sales@filcsi.com 2W POWER PHEMT * ABSOLUTE MAXIMUM RATINGS1 Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power 2 FPD3000 Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp. 3 2 Test Conditions -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions 2 or more Max. Limits Min Max 8 -3 IDSS 25 600 175 Units V V mA mA mW C C W dB % Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression Simultaneous Combination of Limits 1 3 -40 150 7.3 5 80 Users should avoid exceeding 80% of 2 or more Limits simultaneously TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 Notes: * Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. * Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. * Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Absolute Maximum Power Dissipation to be de-rated as follows above 22C: PTOT= 7.3W - (0.05W/C) x THS where THS = heatsink or ambient temperature above 22C Example: For a 85C heatsink temperature: PTOT = 7.3W - (0.05 x (85 - 22)) = 4.2W * HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. ASSEMBLY INSTRUCTIONS The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260C. APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. All information and specifications are subject to change without notice. * * Phone: +1 408 850-5790 Fax: +1 408 850-5766 http://www.filtronic.co.uk/semis Revised: 11/17/04 Email: sales@filcsi.com |
Price & Availability of FPD3000
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |