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Multiformat 216 MHz Video Encoder with Six NSV(R) 12-Bit DACs ADV7320/ADV7321
FEATURES
High definition input formats 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb Fully compliant with: SMPTE 274M (1080i, 1080p @ 74.25 MHz) SMPTE 296M (720p) SMPTE 240M (1035i) RGB in 3- x 10-bit 4:4:4 input format HDTV RGB supported: RGB, RGBHV Other high definition formats using async timing mode Enhanced definition input formats 8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb SMPTE 293M (525p) BTA T-1004 EDTV2 (525p) ITU-R BT.1358 (625p/525p) ITU-R BT.1362 (625p/525p) RGB in 3- x 10-bit 4:4:4 input format Standard definition input formats CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input High definition output formats YPrPb HDTV (EIA 770.3) RGB, RGBHV CGMS-A (720p/1080i) Enhanced definition output formats Macrovision Rev 1.2 (525p/625p) (ADV7320 only) CGMS-A (525p/625p) YPrPb progressive scan (EIA-770.1, EIA-770.2) RGB, RGBHV Standard definition output formats Composite NTSC M/N Composite PAL M/N/B/D/G/H/I, PAL-60 SMPTE 170M NTSC-compatible composite video ITU-R BT.470 PAL-compatible composite video S-video (Y/C) EuroScart RGB Component YPrPb (Betacam, MII, SMPTE/EBU N10) Macrovision Rev 7.1.L1 (ADV7320 only) CGMS/WSS Closed captioning Programmable DAC gain control Sync outputs in all modes On-board voltage reference Six 12-bit NSV (noise shaped video) precision video DACs 2-wire serial I2C(R) interface, open-drain configuration Dual I/O supply 2.5 V/3.3 V operation Analog and digital supply 2.5 V On-board PLL 64-lead LQFP package Lead (Pb) free product
APPLICATIONS
EVD players (enhanced versatile disk) High end /SD/PS DVD recorders/players SD/progressive scan/HDTV display devices SD/HDTV set top boxes Professional video systems
STANDARD DEFINITION CONTROL BLOCK COLOR CONTROL BRIGHTNESS DNR GAMMA PROGRAMMABLE FILTERS SD TEST PATTERN D E M U X
ADV7320/ ADV7321
12-BIT DAC O V E R S A M P L I N G 12-BIT DAC 12-BIT DAC 12-BIT DAC 12-BIT DAC 12-BIT DAC
Y9-Y0 C9-C0 S9-S0
PROGRAMMABLE RGB MATRIX
HIGH DEFINITION CONTROL BLOCK HD TEST PATTERN HSYNC VSYNC BLANK CLKIN_A CLKIN_B TIMING GENERATOR COLOR CONTROL ADAPTIVE FILTER CTRL SHARPNESS FILTER
PLL
Figure 1. Simplified Functional Block Diagram
GENERAL DESCRIPTION
The ADV(R)7320/ADV7321 are high speed, digital-to-analog encoders on single monolithic chips. They include six high speed NSV video D/A converters with TTL compatible inputs. They have separate 8-/10-, 16-/20-, and 24-/30-bit input ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical, and blanking signals or EAV/SAV timing codes control the insertion of appropriate synchronization signals into the digital data stream and, therefore, the output signal.
GENERAL FEATURES
Simultaneous SD/HD, PS/SD inputs and outputs Oversampling up to 216 MHz
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
05067-001
I2C INTERFACE
ADV7320/ADV7321 TABLE OF CONTENTS
Specifications..................................................................................... 6 Dynamic Specifications ................................................................... 7 Timing Specifications....................................................................... 8 Timing Diagrams.............................................................................. 9 Absolute Maximum Ratings.......................................................... 16 Thermal Characteristics ............................................................ 16 ESD Caution................................................................................ 16 Pin Configuration and Function Descriptions........................... 17 Typical Performance Characteristics ........................................... 19 MPU Port Description................................................................... 23 Register Access................................................................................ 25 Register Programming............................................................... 25 Subaddress Register (SR7 to SR0) ............................................ 25 Input Configuration ....................................................................... 38 Standard Definition Only.......................................................... 38 Progressive Scan Only or HDTV Only ................................... 38 Simultaneous Standard Definition and Progressive Scan or HDTV ....................................................... 38 Progressive Scan at 27 MHz (Dual Edge) or 54 MHz ........... 39 Features ............................................................................................ 41 Output Configuration................................................................ 41 HD Async Timing Mode........................................................... 42 HD Timing Reset........................................................................ 43 SD Real-Time Control, Subcarrier Reset, and Timing Reset ............................................................................... 43 Reset Sequence............................................................................ 45 Function of CGMS Bits ............................................................. 65 SD VCR FF/RW Sync................................................................. 45 CGMS Functionality.................................................................. 65 Vertical Blanking Interval ......................................................... 46 Appendix 2--SD Wide Screen Signaling .................................... 68 Subcarrier Frequency Registers ................................................ 46 Appendix 3--SD Closed Captioning ........................................... 69 Square Pixel Timing Mode........................................................ 47 Appendix 4--Test Patterns............................................................ 70 Filters............................................................................................ 48 Appendix 5--SD Timing Modes .................................................. 73 Color Controls and RGB Matrix .............................................. 49 Programmable DAC Gain Control .......................................... 53 Gamma Correction .................................................................... 53 HD Sharpness Filter and Adaptive Filter Controls................ 55 HD Sharpness Filter and Adaptive Filter Application Examples ................................................................ 56 SD Digital Noise Reduction...................................................... 57 Coring Gain Border ................................................................... 58 Coring Gain Data ....................................................................... 58 DNR Threshold .......................................................................... 58 Border Area................................................................................. 58 Block Size Control...................................................................... 58 DNR Input Select Control......................................................... 58 DNR Mode Control ................................................................... 59 Block Offset Control .................................................................. 59 SD Active Video Edge................................................................ 59 SAV/EAV Step Edge Control .................................................... 59 HSYNC/VSYNC Output Control ............................................ 61 Board Design and Layout.............................................................. 62 DAC Termination and Layout Considerations ...................... 62 Video Output Buffer and Optional Output Filter.................. 62 PCB Board Layout...................................................................... 63 Appendix 1--Copy Generation Management System .............. 65 PS CGMS..................................................................................... 65 HD CGMS................................................................................... 65 SD CGMS .................................................................................... 65
Rev. 0 | Page 2 of 88
ADV7320/ADV7321
Mode 0 (CCIR-656)--Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0) ............................73 Mode 0 (CCIR-656)--Master Option (Timing Register 0 TR0 = X X X X X 0 0 1) ............................74 Mode 1--Slave Option (Timing Register 0 TR0 = X X X X X 0 1 0) ............................76 Mode 1--Master Option (Timing Register 0 TR0 = X X X X X 0 1 1) ............................77 Mode 2-- Slave Option (Timing Register 0 TR0 = X X X X X 1 0 0) ............................78 Mode 2--Master Option (Timing Register 0 TR0 = X X X X X 1 0 1) ............................79 Mode 3--Master/Slave Option (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) .......................................................................................................80 Appendix 6--HD Timing ..............................................................81 Appendix 7--Video Output Levels...............................................82 HD YPrPb Output Levels ..........................................................82 RGB Output Levels .....................................................................83 YPrPb Levels--SMPTE/EBU N10............................................84 Appendix 8--Video Standards ......................................................86 Outline Dimensions........................................................................88 Ordering Guide ...........................................................................88
REVISION HISTORY
10/04--Revision 0: Initial Version
Rev. 0 | Page 3 of 88
ADV7320/ADV7321
DETAILED FEATURES
High definition programmable features (720p/1080i/1035i) 2x oversampling (148.5 MHz) Internal test pattern generator Color hatch, black bar, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS-A (720p/1080i) Enhanced definition programmable features (525p/625p) 8x oversampling (216 MHz output) Internal test pattern generator Color hatch, black bar, flat frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) (ADV7320 only) CGMS-A (525p/625p) Standard definition programmable features 16x oversampling (216 MHz) Internal test pattern generator Color bars, black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAFTM filter with programmable gain/attenuation PrPb SSAFTM Separate pedestal control on component and composite/S-video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 (ADV7320 only) CGMS/WSS Closed captioning
Table 1. Standards Directly Supported1
Interlace/ Prog. I I I Frame Rate (Hz) 29.97 25 29.97 Clk Input (MHz) 27 27 24.54
Resolution 720 x 480 720 x 576 720 x 480
720 x 576 720 x 483 720 x 483 720 x 483 720 x 576 720 x 483 720 x 576 1920 x 1035 1280 x 720
I P P P P P P I P
25 59.94 59.94 59.94 50 59.94 50 30 29.97 60, 50, 30, 25, 24, 23.97, 59.94, 29.97 30, 25 29.97 30, 25, 24 23.98, 29.97,
29.5 27 27 27 27 27 27 74.25 74.1758 74.25,
Standard ITU-R BT.656 ITU-R BT.656 NTSC Square Pixel PAL Square Pixel SMPTE 293M BTA T-1004 ITU-R BT.1358 ITU-R BT.1358 ITU-R BT.1362 ITU-R BT.1362 SMPTE 240M SMPTE 296M
74.1758
1920 x 1080 1920 x 1080
I P
74.25 74.1758 74.25 74.1758
SMPTE 274M SMPTE 274M
1
Other standards are supported in async timing mode.
Rev. 0 | Page 4 of 88
ADV7320/ADV7321
HD PIXEL INPUT CLKIN_B P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC S_BLANK CLKIN_A SD PIXEL INPUT DEINTER- CR LEAVE Y CB Y DEINTER- CR LEAVE CB TEST PATTERN SHARPNESS AND ADAPTIVE FILTER CONTROL Y COLOR CR COLOR CB COLOR 4:2:2 TO 4:4:4 PS 8x HDTV 2x DAC DAC TIMING GENERATOR CLOCK CONTROL AND PLL DAC U V UV SSAF RGB MATRIX SD 16x TEST PATTERN DNR GAMMA COLOR CONTROL SYNC INSERTION LUMA AND CHROMA FILTERS 2x OVERSAMPLING FSC MODULATION CGMS WSS DAC DAC DAC
TIMING GENERATOR
Figure 2. Detailed Functional Block Diagram
TERMINOLOGY
SD: standard definition video, conforming to ITU-R BT.601/ITU-R BT.656. HD: high definition video, i.e., 720p/1080i/1035i. EDTV: enhanced definition television (525p/625p) PS: progressive scan video, conforming to SMPTE 293M, ITU-R BT.1358, BTAT-1004EDTV2, or ITU-R BT.13621362.
HDTV: high definition television video, conforming to SMPTE 274M, or SMPTE 296M and SMPTE240M. YCrCb SD, PS, or HD component: digital video. YPrPb SD, PS, or HD component: analog video.
Rev. 0 | Page 5 of 88
05067-002
ADV7320/ADV7321 SPECIFICATIONS
VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 , RLOAD = 300 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted. Table 2.
Parameter STATIC PERFORMANCE1 Resolution Integral Nonlinearity Differential Nonlinearity,2 +ve Differential Nonlinearity,2 -ve DIGITAL OUTPUTS Output Low Voltage, VOL Output High Voltage, VOH Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current Input Capacitance, CIN ANALOG OUTPUTS Full-Scale Output Current Output Current Range DAC to DAC Matching Output Compliance Range, VOC Output Capacitance, COUT VOLTAGE REFERENCE Internal Reference Range, VREF External Reference Range, VREF VREF Current4 POWER REQUIREMENTS Normal Power Mode IDD5 Min Typ 12 1.5 0.25 1.5 0.4 [0.4]3 2.4 [2.0]3 1.0 2 2 0.8 10 2 4.1 4.1 0 4.33 4.33 1.0 1.0 7 1.235 1.235 10 4.6 4.6 1.4 Max Unit Bits LSB LSB LSB V V A pF V V A pF mA mA % V pF V V A ISINK = 3.2 mA ISOURCE = 400 A VIN = 0.4 V, 2.4 V Test Conditions
VIN = 2.4 V
1.15 1.15
1.3 1.3
IDD_IO IAA7, 8 Sleep Mode IDD IAA IDD_IO POWER SUPPLY REJECTION RATIO
137 78 73 140 1.0 37 80 7 250 0.01
1906 45
mA mA mA mA mA mA A A A %/%
SD only (16x) PS only (8x) HDTV only (2x) SD (16x, 10 bit) + PS (8x, 20 bit)
1 2
Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios. DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for -ve DNL, the actual step value lies below the ideal step value. 3 Value in brackets for VDD_IO = 2.375 V to 2.75 V. 4 External current required to overdrive internal VREF. 5 IDD, the circuit current, is the continuous current required to drive the digital core. 6 Guaranteed maximum by characterization. 7 All DACs on. 8 IAA is the total current required to supply all DACs including the VREF circuitry and the PLL circuitry.
Rev. 0 | Page 6 of 88
ADV7320/ADV7321 DYNAMIC SPECIFICATIONS
VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 , RLOAD = 300 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted. Table 3.
Parameter PROGRESSIVE SCAN MODE Luma Bandwidth Chroma Bandwidth SNR HDTV MODE Luma Bandwidth Chroma Bandwidth STANDARD DEFINITION MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermodulation Chroma/Luma Gain Inequality Chroma/Luma Delay Inequality Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Differential Gain Differential Phase SNR Min Typ 12.5 5.8 65.6 72 30 13.75 0.2 0.20 0.84 -0.2 0 96.7 -1.0 0.2 84 75.3 0.25 0.2 63.5 77.7 Max Unit MHz MHz dB dB MHz MHz Degrees % % Degrees % % ns % dB dB % Degrees dB dB Test Conditions
Luma ramp unweighted Flat field full bandwidth
Referenced to 40 IRE
NTSC NTSC Luma ramp Flat field full bandwidth
Rev. 0 | Page 7 of 88
ADV7320/ADV7321 TIMING SPECIFICATIONS
VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 , RLOAD = 300 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted. Table 4.
Parameter MPU PORT1 SCLOCK Frequency SCLOCK High Pulse Width, t1 SCLOCK Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 RESET Low Time ANALOG OUTPUTS Analog Output Delay2 Output Skew CLOCK CONTROL AND PIXEL PORT3 fCLK fCLK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t111 Data Hold Time, t121 SD Output Access Time, t13 SD Output Hold Time, t14 HD Output Access Time, t13 HD Output Hold Time, t14 PIPELINE DELAY4 Min 0 0.6 1.3 0.6 0.6 100 300 300 0.6 100 7 1 29.5 81 40 40 2.0 2.0 15 5.0 14 5.0 63 76 35 41 36 Typ Max 400 Unit kHz s s s s ns ns ns s ns ns ns MHz MHz % of one clk cycle % of one clk cycle ns ns ns ns ns ns clk cycles clk cycles clk cycles clk cycles clk cycles SD PAL square pixel mode PS/HD async mode Test Conditions
First clock generated after this period relevant for repeated start condition
SD (2x, 16x) SD component mode (16x) PS (1x) PS (8x) HD (2x, 1x)
1 2
Guaranteed by characterization. Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3 Data: C[9:0]; Y[9:0], S[9:0] Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK 4 SD, PS = 27 MHz, HD = 74.25 MHz.
Rev. 0 | Page 8 of 88
ADV7320/ADV7321 TIMING DIAGRAMS
CLKIN_A
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9-C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CONTROL OUTPUTS
t13
t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
Figure 3. HD Only 4:2:2 Input Mode (Input Mode 010); PS Only 4:2:2 Input Mode (Input Mode 001)
CLKIN_A
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9-C0
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
t11
S9-S0 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5
CONTROL OUTPUTS
t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME t13
05067-004
Figure 4. HD Only 4:4:4 Input Mode (Input Mode 010); PS Only 4:4:4 Input Mode (Input Mode 001)
Rev. 0 | Page 9 of 88
05067-003
ADV7320/ADV7321
CLKIN_A
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
G0
G1
G2
G3
G4
G5
C9-C0
B0
B1
B2
B3
B4
B5
t11
S9-S0 R0 R1 R2 R3 R4 R5
CONTROL OUTPUTS
t14
05067-005
t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
t13
Figure 5. HD RGB 4:4:4 Input Mode (Input Mode 010)
CLKIN_B*
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y9-Y0 Cb0 Y0
t10
Cr0
Y1
Crxxx
Yxxx
t12 t11
CONTROL OUTPUTS
t12 t11 t13
t14
05067-006
t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
*CLKIN_B MUST BE USED IN THIS PS MODE.
Figure 6. PS 4:2:2 10-Bit Interleaved at 27 MHz HSYNC/VSYNC Input Mode (Input Mode 100)
CLKIN_A
t9
CONTROL INPUTS P_VSYNC, P_HSYNC, P_BLANK Y9-Y0 Cb0
t10
Y0
Cr0
Y1
Crxxx
Yxxx
t11
CONTROL OUTPUTS
t12
t13 t14
Figure 7. PS 4:2:2 10-Bit Interleaved at 54 MHz HSYNC /VSYNC Input Mode (Input Mode 111)
Rev. 0 | Page 10 of 88
05067-007
t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
ADV7320/ADV7321
CLKIN_B*
t9
t10
Y9-Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
t12 t11
CONTROL OUTPUTS
t12 t11 t13
*CLKIN_B USED IN THIS PS ONLY MODE.
Figure 8. PS Only 4:2:2 10-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100)
CLKIN_A
t9
t10
Y9-Y0
3FF
00
05067-008
t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
t14
00
XY
Cb0
Y0
Cr0
Y1
t11
CONTROL OUTPUTS
t12
t13 t14
NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT-1
Figure 9. PS Only 4:2:2 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 111)
CLKIN_B
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
Y0
Y1
Y2
Y3
Y4
Y5
HD INPUT
C9-C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CLKIN_A
CONTROL INPUTS
S_HSYNC, S_VSYNC, S_BLANK S9-S0
t9
t10
t12
SD INPUT
t11
Figure 10. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode (Input Mode 101: SD Oversampled) (Input Mode 110: HD Oversampled)
Rev. 0 | Page 11 of 88
05067-010
Cb0
Y0
Cr0
Y1
Cb1
Y2
05067-009
t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
ADV7320/ADV7321
CLKIN_B
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
PS INPUT Y9-Y0 Cb0 Y0 Cr0 Y1 Crxxx Yxxx
t12 t11 t11
t12
CLKIN_A
CONTROL INPUTS
S_HSYNC, S_VSYNC, S_BLANK S9-S0
t9
t10
t12
SD INPUT
05067-012
Cb0
Y0
Cr0
Y1
Cb1
Y2
t11
Figure 11. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode (Input Mode 011)
CLKIN_B
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
PS INPUT Y9-Y0 Cb0 Y0 Cr0 Y1 Crxxx Yxxx
t12 t11 t11
t12
CLKIN_A
CONTROL INPUTS
S_HSYNC, S_VSYNC, S_BLANK S9-S0
t9
t10
t12
SD INPUT
05067-012
Cb0
Y0
Cr0
Y1
Cb1
Y2
t11
Figure 12. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode (Input Mode 100)
Rev. 0 | Page 12 of 88
ADV7320/ADV7321
CLKIN_A
t9
CONTROL INPUTS S_HSYNC, S_VSYNC, S_BLANK
t10
t12
IN SLAVE MODE
S9-S0/Y9-Y0*
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CONTROL OUTPUTS
t13
IN MASTER/SLAVE MODE
05067-013
t14
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 13. 10-/8-Bit SD Only Pixel Input Mode (Input Mode 000)
CLKIN_A
t9
CONTROL INPUTS S_HSYNC, S_VSYNC, S_BLANK S9-S0/Y9-Y0*
t10
t12
IN SLAVE MODE
Y0
Y1
Y2
Y3
C9-C0
Cb0
Cr0
Cb2
Cr2
t11
CONTROL OUTPUTS
t13
IN MASTER/SLAVE MODE
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 14. 20-/16-Bit SD Only Pixel Input Mode (Input Mode 000)
Rev. 0 | Page 13 of 88
05067-014
t14
ADV7320/ADV7321
Y OUTPUT c
P_HSYNC
P_VSYNC
a
P_BLANK
Y9-Y0
Y0
Y1
Y2
Y3
C9-C0
Cb0
Cr0
Cr1
Cb1
b
a AND b AS PER RELEVANT STANDARD
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC IN TO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 15. HD 4:2:2 Input Timing Diagram
P_HSYNC
P_VSYNC
a P_BLANK
Y9-Y0
Cb
Y
Cr
b a = 32 CLKCYCLES FOR 525p a = 24 CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p
05067-016
Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram
Rev. 0 | Page 14 of 88
05067-015
Y
ADV7320/ADV7321
S_HSYNC
S_VSYNC
PAL = 24 CLK CYCLES NTSC = 32 CLK CYCLES
S_BLANK
S9-S0/Y9-Y0*
Cb
Y
Cr
Y
*SELECTED BY ADDRESS 0x01 BIT 7
PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES
Figure 17. SD Timing Input for Timing Mode 1
t3
SDA
t5
t3
t6
SCLK
t1
05067-018
t2
t7
t4
t8
Figure 18. MPU Port Timing Diagram
Rev. 0 | Page 15 of 88
05067-017
ADV7320/ADV7321 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter1 VAA to AGND VDD to DGND VDD_IO to GND_IO Digital Input Voltage to DGND VAA to VDD AGND to DGND DGND to GND_IO AGND to GND_IO Ambient Operating Temperature (TA) Storage Temperature (TS) Infrared Reflow Soldering (20 s) Value -0.3 V to +3.0 V -0.3 V to +3.0 V -0.3 V to +4.6 V -0.3 V to VDD_IO +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +0.3 V 0C to 70C -65C to +150C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
JC = 11C/W JA = 47C/W
1
Analog output short circuit to any power supply or common can be of an indefinite duration.
The ADV7320/ADV7321 is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and is able to withstand surface-mount soldering up to 255C (5C). In addition, it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220C to 235C.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 16 of 88
ADV7320/ADV7321 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
S_HSYNC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 S_BLANK PIN 1 47 RSET1 46 VREF 45 COMP1 44 DAC A
VDD_IO Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
1 2 3 4 5 6 7 8 9
S_VSYNC
43 DAC B 42 DAC C 41 VAA 40 AGND 39 DAC D 38 DAC E 37 DAC F 36 COMP2 35 RSET2 34 EXT_LF 33 RESET
CLKIN_B
GND_IO
DGND
VDD
S9
S8
S7
S6
S5
S4
S3
S2
S1
ADV7320/ADV7321
TOP VIEW (Not to Scale)
VDD 10 DGND 11 Y8 12 Y9 13 C0 14 C1 15 C2 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P_HSYNC
P_VSYNC
SCLK
ALSB
S0
RTC_SCR_TR
SDA
I2C
P_BLANK
CLKIN_A
C3
C4
C5
C6
C7
C8
C9
Figure 19. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 11, 57 40 32 63 45, 36 44 43 42 39 38 37 23 24 25 48 49 50 13,12, 9-2 30-26, 18-14 Mnemonic DGND AGND CLKIN_A CLKIN_B COMP1, COMP2 DAC A DAC B DAC C DAC D DAC E DAC F P_HSYNC P_VSYNC P_BLANK S_BLANK S_VSYNC S_HSYNC Y9 to Y0 C9 to C0 Input/Output G G I I O O O O O O O I I I I/O I/O I/O I I Description Digital Ground. Analog Ground. Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz). Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes. Compensation Pin for DACs. Connect 0.1 F capacitor from COMP pin to VAA. CVBS/Green/Y/Y Analog Output. Chroma/Blue/U/Pb Analog Output. Luma/Red/V/Pr Analog Output. In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Y/Green [HD] Analog Output. In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red Analog Output. In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pb/Blue [HD] Analog Output. Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Blanking Control Signal for SD Only. Video Vertical Sync Control Signal for SD Only. Video Horizontal Sync Control Signal for SD Only. SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2. Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB is set up on C2.
Rev. 0 | Page 17 of 88
05067-019
ADV7320/ADV7321
Pin No. 62-58, 55-51 33 47, 35 22 21 20 1 10, 56 41 46 34 31 19 64 Mnemonic S9 to S0 RESET RSET1, RSET2 SCLK SDA ALSB VDD_IO VDD VAA VREF EXT_LF RTC_SCR_TR I2C GND_IO Input/Output I I I I I/O I P P P I/O I I I Description SD or Progressive Scan/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2. This input resets the on-chip timing generator and sets the ADV7320/ADV7321 into default register setting. RESET is an active low signal. A 3040 resistor must be connected from this pin to AGND and is used to control the amplitudes of the DAC outputs. I2C Port Serial Interface Clock Input. I2C Port Serial Data Input/Output. TTL Address Input. This signal sets up the LSB of the I2C address. When this pin is tied low, the I2C filter is activated, which reduces noise on the I2C interface. Power Supply for Digital Inputs and Outputs. Digital Power Supply. Analog Power Supply. Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). External Loop Filter for the Internal PLL. Multifunctional Input. Real-time control (RTC) input, timing reset input, subcarrier reset input. This input pin must be tied high (VDD_IO) for the ADV7320/ADV7321 to interface over the I2C port. Digital Input/Output Ground.
Rev. 0 | Page 18 of 88
ADV7320/ADV7321 TYPICAL PERFORMANCE CHARACTERISTICS
PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0
1.0 0.5
Y PASS BAND IN PS OVERSAMPLING MODE
-10
0
-20
GAIN (dB)
GAIN (dB)
05067-045
-30 -40 -50 -60 -70 -80
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0
05067-048
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 20. PS--UV 8x Oversampling Filter (Linear)
PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 -10 -20
GAIN (dB)
Figure 23. PS--Y 8x Oversampling Filter (Pass Band)
Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE 0 -10 -20
GAIN (dB)
05067-046
-30 -40 -50 -60 -70 -80
-30 -40 -50 -60 -70 -80
05067-049
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
0
20
40
60 80 100 FREQUENCY (MHz)
120
140
Figure 21. PS--UV 8x Oversampling Filter (SSAF)
Y RESPONSE IN PS OVERSAMPLING MODE 0 -10 -20
GAIN (dB)
GAIN (dB)
Figure 24. HDTV--UV 2x Oversampling Filter
Y RESPONSE IN HDTV OVERSAMPLING MODE 0 -10 -20 -30 -40 -50 -60
05067-047
-30 -40 -50 -60 -70 -80
-70 -80
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
0
20
40
60 80 100 FREQUENCY (MHz)
120
140
Figure 22. PS--Y 8x Oversampling Filter
Figure 25. HDTV--Y 2x Oversampling Filter
Rev. 0 | Page 19 of 88
05067-050
ADV7320/ADV7321
0 -10 -20 -30 -40 -50
05067-051
0 -10 -20 -30 -40 -50
05067-054
MAGNITUDE (dB)
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
MAGNITUDE (dB)
12
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
12
Figure 26. Luma NTSC Low-Pass Filter
Figure 29. Luma PAL Notch Filter
Y RESPONSE IN SD OVERSAMPLING MODE
0 -10 -20 -30 -40 -50
0 -10 -20
MAGNITUDE (dB)
GAIN (dB)
05067-052
-30 -40 -50 -60 -70 -80
05067-055
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
12
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
Figure 27. Luma PAL Low-Pass Filter
Figure 30. Y--16x Oversampling Filter
0 -10 -20 -30 -40 -50
05067-053
0 -10 -20 -30 -40 -50
05067-056
MAGNITUDE (dB)
MAGNITUDE (dB)
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
12
12
Figure 28. Luma NTSC Notch Filter
Figure 31. Luma SSAF Filter up to 12 MHz
Rev. 0 | Page 20 of 88
ADV7320/ADV7321
4 2 0 0 -10 -20 -30 -40 -50
05067-057
MAGNITUDE (dB)
-2 -4 -6 -8 -10 -12 0 1 2 3 4 FREQUENCY (MHz) 5 6 7
MAGNITUDE (dB)
-70 0 2 4 8 6 FREQUENCY (MHz) 10
12
Figure 32. Luma SSAF Filter--Programmable Responses
Figure 35. Luma CIF Low-Pass Filter
5 0 4 -10 -20 -30 -40 -50
05067-058
MAGNITUDE (dB)
2
1
-1 0 1 2 3 4 FREQUENCY (MHz) 5 6 7
-70 0 2 4 6 8 FREQUENCY (MHz) 10
12
Figure 33. Luma SSAF Filter--Programmable Gain
1 0 0 -10 -20 -30 -40 -50
05067-059
Figure 36. Luma QCIF Low-Pass Filter
MAGNITUDE (dB)
-2
-3
-5 0 1 2 3 4 FREQUENCY (MHz) 5 6 7
-70 0 2 4 6 8 FREQUENCY (MHz) 10
12
Figure 34. Luma SSAF Filter--Programmable Attenuation
Figure 37. Chroma 3.0 MHz Low-Pass Filter
Rev. 0 | Page 21 of 88
05067-062
-4
MAGNITUDE (dB)
-1
-60
05067-061
0
MAGNITUDE (dB)
3
-60
05067-060
-60
ADV7320/ADV7321
0 -10 -20 -30 -40 -50
05067-063
0 -10 -20 -30 -40 -50
05067-066
MAGNITUDE (dB)
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
MAGNITUDE (dB)
12
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
12
Figure 38. Chroma 2.0 MHz Low-Pass Filter
Figure 41. Chroma 0.65 MHz Low-Pass Filter
0 -10 -20 -30 -40 -50
05067-064
0 -10 -20 -30 -40 -50
05067-067
MAGNITUDE (dB)
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
MAGNITUDE (dB)
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
12
12
Figure 39. Chroma 1.3 MHz Low-Pass Filter
Figure 42. Chroma CIF Low-Pass Filter
0 -10 -20 -30 -40 -50
05067-065
0 -10 -20 -30 -40 -50
05067-068
MAGNITUDE (dB)
-60 -70 0 2 4 6 8 FREQUENCY (MHz) 10
MAGNITUDE (dB)
-60 -70
12
0
2
4
6 8 FREQUENCY (MHz)
10
12
Figure 40. Chroma 1.0 MHz Low-Pass Filter
Figure 43. Chroma QCIF Low-Pass Filter
Rev. 0 | Page 22 of 88
ADV7320/ADV7321 MPU PORT DESCRIPTION
The ADV7320/ADV7321 support a 2-wire serial (I2Ccompatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV7320/ ADV7321. Each slave device is recognized by a unique address. The ADV7320/ADV7321 have four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 44. The LSB sets either a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. A1 is enabled by setting the ALSB pin of the ADV7320/ADV7321 to Logic 0 or Logic 1. When ALSB is set to 1, there is greater input bandwidth on the I2C lines, which allows high speed data transfers on this bus. When ALSB is set to 0, there is reduced input bandwidth on the I2C lines, which means that pulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems.
1 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ
05067-020
correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master will write information to the peripheral. Logic 1 on the LSB of the first byte means that the master will read information from the peripheral. The ADV7320/ADV7321 act as standard slave devices on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then they cause an immediate jump to the idle condition. During a given SCL high period, the user should only issue a start condition, a stop condition, or a stop condition followed by a start condition. If an invalid subaddress is issued by the user, the ADV7320/ADV7321 will not issue an acknowledge and will return to the idle condition. If the user utilizes the autoincrement method of addressing the encoder and exceeds the highest subaddress, the following actions are taken: * In read mode, the highest subaddress register contents are output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition is when the SDA line is not pulled low on the ninth pulse.
X
Figure 44. ADV7320 Slave Address = 0xD4
0 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ
05067-021
X
Figure 45. ADV7321 Slave Address = 0x54
* In write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7320/ADV7321, and the part returns to the idle condition. Before writing to the subcarrier frequency registers, it is required to reset ADV7320/ADV7321 at least once after power-up. The four subcarrier frequency registers must be updated, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3. The subcarrier frequency will only update after the last subcarrier frequency register byte has been received by the ADV7320/ADV7321. Figure 46 illustrates an example of data transfer for a write sequence and the start and stop conditions. Figure 47 shows bus write and read sequences.
To control the various devices on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-tolow transition on SDA while SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the
Rev. 0 | Page 23 of 88
ADV7320/ADV7321
SDATA
S 9 1-7 8 START ADRR R/W ACK
1-7 9 8 SUBADDRESS ACK
1-7 DATA
8
9 ACK
P STOP
Figure 46. Bus Data Transfer
WRITE SEQUENCE
S
SLAVE ADDR
A(S)
SUBADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
LSB = 0 READ SEQUENCE S SLAVE ADDR A(S) SUBADDR
A(S) S SLAVE ADDR
A(S)
DATA
A(M)
05067-022
SCLOCK
DATA
A(M) P
05067-023
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER
Figure 47. Read and Write Sequence
Rev. 0 | Page 24 of 88
ADV7320/ADV7321 REGISTER ACCESS
The MPU can write to or read from all registers of the ADV7320/ADV7321 except the subaddress registers, which are write only registers. The subaddress register determines which register the next read or write operation will access. All communication with the part through the bus starts with an access to the subaddress register. A read/write operation is then performed from/to the target address, which increments to the next address until a stop command is performed on the bus.
REGISTER PROGRAMMING
The following tables describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The communication register is an 8-bit write only register. After the encoder's bus is accessed and a read/write operation is selected, the subaddress is set up. The subaddress register determines to or from which register the operation takes place.
Reg. Reset Values (Shaded) 0xFC
Table 7. Registers 0x00 to 0x01
SR7- SR0 0x00 Register Power Mode Register Bit Description Sleep Mode. With this control enabled, the current consumption is reduced to A level. All DACs and the internal PLL cct are disabled. I2C registers can be read from and written to in sleep mode. PLL and Oversampling Control. This control allows the internal PLL cct to be powered down and the oversampling to be switched off. DAC F: Power On/Off. DAC E: Power On/Off. DAC D: Power On/Off. DAC C: Power On/Off. DAC B: Power On/Off. DAC A: Power On/Off. 0x01 Mode Select Register Reserved. Clock Edge. 0 1 Reserved. Clock Align. 0 0 1 Must be set if the phase delay between the two input clocks is <9.25 ns or >27.75 ns. SD input only. PS input only. HDTV input only. SD and PS (20-bit). SD and PS (10-bit). SD and HDTV (SD oversampled). SD and HDTV (HDTV oversampled). PS only (at 54 MHz). Allows data to be applied to data ports in various configurations (SD feature only). Only if two input clocks are used. 0x38 0 1 0 0 1 0 1 0 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 Register Setting Sleep mode off. Sleep mode on.
0 1
PLL on. PLL off.
0 1 0 1
DAC F off. DAC F on. DAC E off. DAC E on. DAC D off. DAC D on. DAC C off. DAC C on. DAC B off. DAC B on. DAC A off. DAC A on. Reserved. Cb clocked upon rising edge. Y clocked upon rising edge. Only for PS interleaved input at 27 MHz.
Input Mode.
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Y/C/S Bus Swap.
0 1
See Table 21.
Rev. 0 | Page 25 of 88
ADV7320/ADV7321
Table 8. Registers 0x02 to 0x0F
SR7- SR0 0x02 Register Mode Register 0 Bit Description Reserved Test Pattern Black Bar Manual RGB Matrix Adjust Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 Bit 0 0 Register Setting Zero must be written to these bits. Disabled. Enabled. Disable manual RGB matrix adjust. Enable manual RGB matrix adjust. No sync. Sync on all RGB outputs. RGB component outputs. YPrPb component outputs. No sync output. Output SD syncs on S_HSYNC, S_VSYNC, S_BLANK pins. No sync output. Output HD, ED, syncs on S_HSYNC, S_VSYNC. LSB for GY. LSB for RV. LSB for BU. LSB for GV. LSB for GU. Bits 9 to 2 for GY. Bits 9 to 2 for GU. Bits 9 to 2 for GV. Bits 9 to 2 for BU. Bits 9 to 2 for RV. 0% Reset Values 0x20 0x11, Bit 2 must also be enabled.
0 1 0 1
Sync on RGB1 RGB/YPrPb Output SD Sync 0 1 0 1
0 1
HD Sync
0 1 x x x x x x x x x x 0 x x x x x 0 x x x x x 0 x x x x x 0 x x x x x 0 x x x x x x 0 x x x x x x 0 x x x
0x03 0x04
RGB Matrix 0 RGB Matrix 1
0x03 0xF0
0x05 0x06 0x07 0x08 0x09 0x0A
RGB Matrix 2 RGB Matrix 3 RGB Matrix 4 RGB Matrix 5 RGB Matrix 6 DAC A, B, C Output Level2
Positive Gain to DAC Output Voltage
x x x x x 0
0x4E 0x0E 0x24 0x92 0x7C 0x00
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 1 1 0 0
Negative Gain to DAC Output Voltage
1 0 ... 1 0 0
+0.018% +0.036% ... +7.382% +7.5% -7.5%
1 1 1 0
1 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
0 1 1 0
0x0B
DAC D, E, F Output Level
Positive Gain to DAC Output Voltage
1 0 ... 1 0
-7.382% -7.364% ... -0.018% 0%
0x00
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 0 1 0 0
0 1 1 0 0
Negative Gain to DAC Output Voltage
1 0 ... 1 0 0
+0.018% +0.036% ... +7.382% +7.5% -7.5%
1 1 1 0x0C 0x0D 0x0E 0x0F Reserved Reserved Reserved Reserved
1 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 1 1
1 0 ... 1
-7.382% -7.364% ... -0.018% 0x00 0x00 0x00 0x00
1 2
For more detail, refer to Appendix 7. For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.
Rev. 0 | Page 26 of 88
ADV7320/ADV7321
Table 9. Registers 0x10 to 0x11
SR7- SR0 0x10 Register HD Mode Register 1 Bit Description HD Output Standard Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 1 1 Input Sync Format 0 1 HD/ED Input Mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 10010-11111 0x11 HD Mode Register 2 HD Pixel Data Valid 0 HD Test Pattern Enable HD Test Pattern Hatch/Field HD VBI Open HD Undershoot Limiter 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit 0 0 1 0 1 Register Setting EIA770.2 output EIA770.1 output Output levels for full input range Reserved HSYNC, VSYNC, BLANK EAV/SAV codes SMPTE 293M, ITUBT 1358 Async mode BTA-1004, ITUBT 1362 ITU-BT 1358 ITU-BT 1362 SMPTE 296M-1, 2 SMPTE 296M-3 SMPTE 296M-4, 5 SMPTE 296M-6 SMPTE 296M-7, 8 SMPTE 240M Reserved Reserved SMPTE 274M-4, 5 SMPTE 274M-6 SMPTE 274M-7, 8 SMPTE 274M-9 SMPTE 274M10, 11 Reserved Pixel data valid off Pixel data valid on Reserved HD test pattern off HD test pattern on Hatch Field/frame Disabled Enabled Disabled -11 IRE -6 IRE -1.5 IRE Disabled Enabled 525p @ 59.94 Hz 525p @ 59.94 Hz 625p @ 50 Hz 625p @ 50 Hz 720p @ 60/59.94 Hz 720p @ 50 Hz 720p @ 30/29.97 Hz 720p @ 25 Hz 720p @ 24/23.98 Hz 1035i @ 60/59.94 Hz Note Reset Values 0x00
1080i @ 30/29.97 Hz 1080i @ 25 Hz 1080p @ 30/29.97 Hz 1080p @ 25 Hz 1080p @ 24/23.98 Hz 0x00
Only available in EDTV (525p/625p)
HD Sharpness Filter
Rev. 0 | Page 27 of 88
ADV7320/ADV7321
Table 10. Register 0x12
SR7- SR0 0x12 Register HD Mode Register 3 Bit Description HD Y Delay with Respect to Falling Edge of HSYNC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0 0 0 0 1 Bit 1 0 0 1 1 0 Bit 0 0 1 0 1 0 Register Setting 0 clk cycles 1 clk cycles 2 clk cycles 3 clk cycles 4 clk cycles 0 clk cycles 1 clk cycle 2 clk cycles 3 clk cycles 4 clk cycles Disabled Enabled Disabled Enabled Reset Values 0x00
HD Color Delay with Respect to Falling Edge of HSYNC
0 0 0 0 1 0 1 0 1
0 0 1 1 0
0 1 0 1 0
HD CGMS HD CGMS CRC
Table 11. Registers 0x13 to 0x14
SR7- SR0 0x13 Register HD Mode Register 4 Bit Description HD Cr/Cb Sequence Reserved HD Input Format Sinc Filter on DAC D, E, F Reserved HD Chroma SSAF HD Chroma Input HD Double Buffering 0x14 HD Mode Register 5 HD Timing Reset 0 1 x 0 1 0 0 1 0 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 0 1 Register Setting Cb after falling edge of HSYNC. Cr after falling edge of HSYNC. 0 must be written to this bit. 8-bit input. 10-bit input. Disabled. Enabled. 0 must be written to this bit. Disabled. Enabled. 4:4:4 4:2:2 Disabled. Enabled. A low-high-low transition resets the internal HD timing counters. Refer to the / Output Control section. BLANK active high. BLANK active low. Macrovision disabled. Macrovision enabled. 0 must be written to these bits. 0 = field input. 1 = VSYNC input. Update field/line counter. Field/line counter free running. Reset Values 0x4C
0x00
HD Hsync Generation1 HD Vsync Generation1 HD Blank Polarity HD Macrovision for 525p and 625p Reserved HD VSYNC/Field Input Horizontal/Vertical Counters2 0 1 0 1 0 0 1 0 1 0 1
0 1
1 2
Used in conjunction with HD_SYNC in Register 0x02, Bit 7 set to 1. When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Rev. 0 | Page 28 of 88
ADV7320/ADV7321
Table 12. Register 0x15
SR7- SR0 0x15 Register HD Mode Register 6 Bit Description Reserved HD RGB Input HD Sync on PrPb HD Color DAC Swap HD Gamma Curve A/B HD Gamma Curve Enable HD Adaptive Filter Mode HD Adaptive Filter Enable 0 1 0 1 0 1 0 1 0 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 1 0 1 Bit 0 0 Register Setting 0 must be written to this bit. Disabled. Enabled. Disabled. Enabled. DAC E = Pb; DAC F = Pr. DAC E = Pr; DAC F = Pb. Gamma Curve A. Gamma Curve B. Disabled. Enabled. Mode A. Mode B. Disabled. Enabled. Reset Values 0x00
Rev. 0 | Page 29 of 88
ADV7320/ADV7321
Table 13. Registers 0x16 to 0x37
SR7- SR0 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 Register HD Y Level1 HD Cr Level1 HD Cb Level1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved HD Sharpness Filter Gain Value A Bit Description Bit 7 x x x Bit 6 x x x Bit 5 x x x Bit 4 x x x Bit 3 x x x Bit 2 x x x Bit 1 x x x Bit 0 x x x Register Setting Y level value Cr level value Cb level value Reset Values 0xA0 0x80 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
HD Sharpness Filter Gain
0 0 ... 0 1 ... 1 0 0 ... 0 1 ... 1 0 C15 C7 x x x x x x x x x x x x x x x x x x x x 0 0 ... 1 0 ... 1 0 C14 C6 x x x x x x x x x x x x x x x x x x x x 0 0 ... 1 0 ... 1 0 C13 C5 x x x x x x x x x x x x x x x x x x x x 0 1 ... 1 0 ... 1 0 C12 C4 x x x x x x x x x x x x x x x x x x x x
0 0 ... 1 0 ... 1
0 0 ... 1 0 ... 1
0 1 ... 1 0 ... 1
HD Sharpness Filter Gain Value B
0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37
HD CGMS Data 0 HD CGMS Data 1 HD CGMS Data 2 HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B
HD CGMS Data Bits HD CGMS Data Bits HD CGMS Data Bits HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points
C19 C11 C3 x x x x x x x x x x x x x x x x x x x x
C18 C10 C2 x x x x x x x x x x x x x x x x x x x x
C17 C9 C1 x x x x x x x x x x x x x x x x x x x x
C16 C8 C0 x x x x x x x x x x x x x x x x x x x x
Gain A = 0 Gain A = +1 ... Gain A = +7 Gain A = -8 ... Gain A = -1 Gain B = 0 Gain B = +1 ... Gain B = +7 Gain B = -8 ... Gain B = -1 CGMS 19 to 16 CGMS 15 to 8 CGMS 7 to 0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1
For use with internal test pattern only.
Rev. 0 | Page 30 of 88
ADV7320/ADV7321
Table 14. Registers 0x38 to 0x3D
SR7- SR0 0x38 Register HD Adaptive Filter Gain 1 Bit Description HD Adaptive Filter Gain 1 Value A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 0 ... 0 1 ... 1 Bit 2 0 0 ... 1 0 ... 1 Bit 1 0 0 ... 1 0 ... 1 Bit 0 0 1 ... 1 0 ... 1 Register Setting Gain A = 0 Gain A = +1 ... Gain A = +7 Gain A = -8 ... Gain A = -1 Gain B = 0 Gain B = +1 ... Gain B = +7 Gain B = -8 ... Gain B = -1 Gain A = 0 Gain A = +1 ... Gain A = +7 Gain A = -8 ... Gain A = -1 Gain B = 0 Gain B = +1 ... Gain B = +7 Gain B = -8 ... Gain B = -1 Gain A = 0 Gain A = +1 ... Gain A = +7 Gain A = -8 ... Gain A = -1 Gain B = 0 Gain B = +1 ... Gain B = +7 Gain B = -8 ... Gain B = -1 Threshold A Threshold B Threshold C Reset Values 0x00
HD Adaptive Filter Gain 1 Value B
0 0 ... 0 1 ... 1
0 0 ... 1 0 ... 1
0 0 ... 1 0 ... 1
0 1 ... 1 0 ... 1 0 0 ... 0 1 ... 1 0 0 ... 1 0 ... 1 0 0 ... 1 0 ... 1 0 1 ... 1 0 ... 1
0x39
HD Adaptive Filter Gain 2
HD Adaptive Filter Gain 2 Value A
0x00
HD Adaptive Filter Gain 2 Value B
0 0 ... 0 1 ... 1
0 0 ... 1 0 ... 1
0 0 ... 1 0 ... 1
0 1 ... 1 0 ... 1 0 0 ... 0 1 ... 1 0 0 ... 1 0 ... 1 0 0 ... 1 0 ... 1 0 1 ... 1 0 ... 1
0x3A
HD Adaptive Filter Gain 3
HD Adaptive Filter Gain 3 Value A
0x00
HD Adaptive Filter Gain 3 Value B
0x3B 0x3C 0x3D
HD Adaptive Filter Threshold A HD Adaptive Filter Threshold B HD Adaptive Filter Threshold C
HD Adaptive Filter Threshold A HD Adaptive Filter Threshold B HD Adaptive Filter Threshold C
0 0 ... 0 1 ... 1 x x x
0 0 ... 1 0 ... 1 x x x
0 0 ... 1 0 ... 1 x x x
0 1 ... 1 0 ... 1 x x x
x x x
x x x
x x x
x x x
0x00 0x00 0x00
Rev. 0 | Page 31 of 88
ADV7320/ADV7321
Table 15. Registers 0x3E to 0x43
SR7- SR0 0x3E 0x3F 0x40 Register Bit Description Reserved Reserved SD Standard Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values 0x00 0x00 0x00
SD Mode Register 0
0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 1 0 1
SD Luma Filter
SD Chroma Filter
NTSC PAL B, D, G, H, I PAL M PAL N LPF NTSC LPF PAL Notch NTSC Notch PAL SSAF luma Luma CIF Luma QCIF Reserved 1.3 MHz 0.65 MHz 1.0 MHz 2.0 MHz Reserved Chroma CIF Chroma QCIF 3.0 MHz Disabled Enabled Refer to output configuration section Refer to output configuration section Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled No pedestal on YUV 7.5 IRE pedestal on YUV Y = 700 mV/300 mV Y = 714 mV/286 mV 700 mV p-p (PAL); 1000 mV p-p (NTSC) 700 mV p-p 1000 mV p-p 648 mV p-p Disabled Enabled CC disabled CC on odd field only CC on even field only CC on both fields Reserved
0x41 0x42
SD Mode Register 1
Reserved SD PrPb SSAF SD DAC Output 1 0 1 SD DAC Output 2 0 1 SD Pedestal SD Square Pixel SD VCR FF/RW Sync SD Pixel Data Valid SD SAV/EAV Step Edge Control SD Pedestal YPrPb Output SD Output Levels Y SD Output Levels PrPb 0 1 0 1 0 1 0 1 0 1
0 1
0x00 0x08
0x43
SD Mode Register 2
0 1 0 1 0 0 1 1 0 1 0 1
0x00
SD VBI Open SD CC Field Control 0 0 1 1 0 0 1 0 1
0 1
Reserved
Rev. 0 | Page 32 of 88
ADV7320/ADV7321
Table 16. Registers 0x44 to 0x49
SR7- SR0 0x44 Register SD Mode Register 3 Bit Description SD VSYNC-3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 Register Setting Disabled VSYNC= 2.5 lines (PAL), VSYNC= 3 lines (NTSC) Genlock disabled Subcarrier Reset Timing Reset RTC enabled 720 pixels 710 (NTSC)/702 (PAL) Chroma enabled Chroma disabled Enabled Disabled Disabled Enabled DAC A = luma, DAC B = chroma DAC A = chroma, DAC B = luma 5.17 s 5.31 s (default) 5.59 s (must be set for Macrovision compliance) Reserved Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 0 must be written to this bit 0 must be written to this bit 0 must be written to this bit 0 must be written to this bit Disabled Enabled 8-bit input 16-bit input 10-bit input 20-bit input Disabled Enabled Disabled Enabled Gamma Curve A Gamma Curve B Disabled -11 IRE -6 IRE -1.5 IRE 0 must be written to this bit Disabled Enabled Disabled 4 clk cycles 8 clk cycles Reserved 0 must be written to this bit 0 must be written to this bit Reset Values 0x00
SD RTC/TR/SCR
0 0 1 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1
SD Active Video Length SD Chroma SD Burst SD Color Bars SD DAC Swap 0x45 0x46 Reserved SD Mode Register 4
NTSC Color Subcarrier Adjust (Falling Edge of HS to Start of Color Burst)1 SD PrPb Scale SD Y Scale SD Hue Adjust SD Brightness SD Luma SSAF Gain Reserved Reserved Reserved Reserved Reserved SD Double Buffering SD Input Format 0 0 0 0 1 0 1 0 1
0 0 1 1
0 1 0 1 0 1
0x00 0x01
0x47
SD Mode Register 5
0x00
0 1
0x48
SD Mode Register 6
0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1
0x00
SD Digital Noise Reduction SD Gamma Control SD Gamma Curve 0x49 SD Mode Register 7 SD Undershoot Limiter
0x00
Reserved SD Black Burst Output on DAC Luma SD Chroma Delay
Reserved Reserved
1
NTSC color bar adjust should be set to 10 b for macrovision compliance (ADV7320 only).
Rev. 0 | Page 33 of 88
ADV7320/ADV7321
Table 17. Registers 0x4A to 0x58
SR7- SR0 0x4A Register SD Timing Register 0 Bit Description SD Slave/Master Mode SD Timing Mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 Register Setting Slave mode. Master mode. Mode 0. Mode 1. Mode 2. Mode 3. Enabled. Disabled. No delay. 2 clk cycles. 4 clk cycles. 6 clk cycles. -40 IRE. -7.5 IRE. A low-high-low transition will reset the internal SD timing counters. Ta = 1 clk cycle. Ta = 4 clk cycles. Ta = 16 clk cycles. Ta = 128 clk cycles. Tb = 0 clk cycle. Tb = 4 clk cycles. Tb = 8 clk cycles. Tb = 18 clk cycles. Tc = Tb. Tc = Tb + 32 s. 1 clk cycle. 4 clk cycles. 16 clk cycles. 128 clk cycles. 0 clk cycles. 1 clk cycle. 2 clk cycles. 3 clk cycles. Subcarrier Frequency Bits 7 to 0. Subcarrier Frequency Bits 15 to 8. Subcarrier Frequency Bits 23 to 16. Subcarrier Frequency Bits 31 to 24. Subcarrier Phase Bits 9 to 2. Extended Data Bits 7 to 0. Extended Data Bits 15 to 8. Data Bits 7 to 0. Data Bits 15 to 8. Setting any of these bits to 1 will disable pedestal on the line number indicated by the bit settings. Reset Value 0x08
0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 1
0 1 0 1
SD BLANK Input SD Luma Delay
SD Min. Luma Value SD Timing Reset
x
0
0
0
0
0
0
0x4B
SD Timing Register 1
SD HSYNC Width
0 0 1 1 0 0 1 1 x x 0 0 1 1 0 0 1 1 x x x x x x x x x 17 0 1 0 1 x x x x x x x x x 16 0 1 0 1 0 1 0 1 0 1
0 1 0 1
0x00
SD HSYNCto VSYNC Delay
SD HSYNC to VSYNC Rising Edge Delay (Mode 1 Only) VSYNC Width (Mode 2 Only)
HSYNC to Pixel Data Adjust
0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55
SD FSC Register 01 SD FSC Register 1 SD FSC Register 2 SD FSC Register 3 SD FSC Phase SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Pedestal Register 0 SD Pedestal Register 1 SD Pedestal Register 2 SD Pedestal Register 3
Extended Data on Even Fields Extended Data on Even Fields Data on Odd Fields Data on Odd Fields Pedestal on Odd Fields Pedestal on Odd Fields Pedestal on Even Fields Pedestal on Even Fields
x x x x x x x x x 15
x x x x x x x x x 14
x x x x x x x x x 13
x x x x x x x x x 12
x x x x x x x x x 11
x x x x x x x x x 10
0x1E1 0x7C 0xF0 0x21 0x00 0x00 0x00 0x00 0x00 0x00
0x56 0x57 0x58
25 17 25
24 16 24
23 15 23
22 14 22
21 13 21
20 12 20
19 11 19
18 10 18
0x00 0x00 0x00
1
For precise NTSC Fsc, this register should be programmed to 0x1F.
LINE 1 HSYNC LINE 313 LINE 314
tA tB tC
05067-024
VSYNC
Figure 48. Timing Register 1 in PAL Mode
Rev. 0 | Page 34 of 88
ADV7320/ADV7321
Table 18. Registers 0x59 to 0x64
SR7- SR0 0x59 Register SD CGMS/WSS 0 Bit Description SD CGMS Data SD CGMS CRC SD CGMS on Odd Fields SD CGMS on Even Fields SD WSS 0x5A SD CGMS/WSS 1 SD CGMS/WSS Data 15 7 14 6 Bit 7 Bit 6 Bit 5 Bit 4 0 1 0 1 0 1 0 1 13 12 11 10 9 8 Bit 3 19 Bit 2 18 Bit 1 17 Bit 0 16 Register Setting CGMS Data Bits C19 to C16 Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled CGMS Data Bits C13 to C8, or WSS Data Bits C13 to C8 CGMS Data Bits C15 to C14 CGMS/WSS Data Bits C7 to C0 SD Y Scale Bits 1 to 0 SD Cb Scale Bits 1 to 0 SD Cr Scale Bits 1 to 0 Subcarrier Phase Bits 1 to 0 SD Y Scale Bits 7 to 2 SD Cb Scale Bits 7 to 2 SD Cr Scale Bits 7 to 2 SD Hue Adjust Bits 7 to 0 SD Brightness Bits 6 to 0 Disabled Enabled -4 dB 0 dB +4 dB No gain +1/16 [-1/8] +2/16 [-2/8] +3/16 [-3/8] +4/16 [-4/8] +5/16 [-5/8] +6/16 [-6/8] +7/16 [-7/8] +8/16 [-1] No gain +1/16 [-1/8] +2/16 [-2/8] +3/16 [-3/8] +4/16 [-4/8] +5/16 [-5/8] +6/16 [-6/8] +7/16 [-7/8] +8/16 [-1] 0 1 ... 62 63 2 pixels 4 pixels 8 pixels 16 pixels Reset Values 0x00
0x00 0x00 0x00
0x5B 0x5C
SD CGMS/WSS 2 SD LSB Register
SD CGMS/WSS Data SD LSB for Y Scale Value SD LSB for Cb Scale Value SD LSB for Cr Scale Value SD LSB for FSC Phase SD Y Scale Value SD Cb Scale Value SD Cr Scale Value SD Hue Adjust Value SD Brightness Value SD Blank WSS Data SD Luma SSAF Gain/Attenuation Coring Gain Border
5
4
3
2
1 x
0 x
x x x x x x x 0 1 0 0 0 x x x x x x x
x
0x5D 0x5E 0x5F 0x60 0x61
SD Y Scale Register SD Cb Scale Register SD Cr Scale Register SD Hue Register SD Brightness/ WSS SD Luma SSAF
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
0x00 0x00 0x00 0x00 0x00 Line 23 0x00
0x62
0 0 0
0 0 0
0 0 0
0x63
SD DNR 0
0 0 1 0 0 0 0 0 0 0 0 1
0 1 1 0 0 0 0 1 1 1 1 0
0 1 0 0 0 1 1 0 0 1 1 0
0 0 0 0 1 0 1 0 1 0 1 0
0x00 In DNR mode, the values in brackets apply.
Coring Gain Data
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 0
0x64
SD DNR 1
DNR Threshold
0 0 1 1 0 0 1 1 0 0 0 ... 1 1
0 1 0 1 0 1 0 1 0 0 0 ... 1 1
0 0 ... 1 1
0 0 ... 1 1
0 0 ... 1 1
0 1 ... 0 1
0x00
Border Area Block Size Control 0 1
0 1
Rev. 0 | Page 35 of 88
ADV7320/ADV7321
Table 19. Registers 0x65 to 0x7C
SR7- SR0 0x65 Register SD DNR 2 Bit Description DNR Input Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0 0 0 1 Bit 1 0 1 1 0 Bit 0 1 0 1 0 Register Setting Filter A Filter B Filter C Filter D DNR mode DNR sharpness mode 0 pixel offset 1 pixel offset ... 14 pixel offset 15 pixel offset A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Read only Read only Reserved Reserved Reserved Read only Reserved Reset Values 0x00
DNR Mode DNR Block Offset 0 0 ... 1 1 x x x x x x x x x x x x x x x x x x x x x 0 0 ... 1 1 x x x x x x x x x x x x x x x x x x x x x 0 0 ... 1 1 x x x x x x x x x x x x x x x x x x x x x
0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B
SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Brightness Detect Field Count Register
SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Brightness Value Field Count Reserved Reserved Reserved Revision Code Reserved
0 1 0 1 ... 0 1 x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x8x
0 0 0 1 0
0x7C
0x00
Rev. 0 | Page 36 of 88
ADV7320/ADV7321
Table 20. Registers 0x7D to 0x91
SR7SR0 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 Register Reserved Reserved Reserved Macrovision1 Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values
MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bit
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x x
0 must be written to these bits
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1
Macrovision registers only on the ADV7320.
Rev. 0 | Page 37 of 88
ADV7320/ADV7321 INPUT CONFIGURATION
When 10-bit input data is applied, the following bits must be set to 1: Address 0x13, Bit 2 (HD 10-bit enable) Address 0x48, Bit 4 (SD 10-bit enable) Note that the ADV7320 defaults to simultaneous standard definition and progressive scan upon power-up (Address[0x01]: Input Mode = 011).
PROGRESSIVE SCAN ONLY OR HDTV ONLY
Address[0x01]: Input Mode = 001 or 010, Respectively YCrCb progressive scan, HDTV, or any other HD YCrCb data can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data is input on Pins Y9 to Y0 and the CrCb data is input on Pins C9 to C0. In 4:4:4 input mode, Y data is input on Pins Y9 to Y0, Cb data is input on Pins C9 to C0, and Cr data is input on Pins S9 to S0. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004/1362, the async timing mode must be used. RGB data can only be input in 4:4:4 format in PS or HDTV input modes when HD RGB input is enabled. G data is input on Pins Y9 to Y0, R data is input on Pins S9 to S0, and B data is input on Pins C9 to C0. The clock signal must be input on Pin CLKIN_A.
MPEG2 DECODER 27MHz YCrCb Cb 10 Cr 10 INTERLACED TO PROGRESSIVE Y 10 3 CLKIN_A C[9:0] S[9:0] Y[9:0]
05067-026
STANDARD DEFINITION ONLY
Address[0x01]: Input Mode = 000 The 8-/10-bit, multiplexed input data is input on Pins S9 to S0 (or Pins Y9 to Y0, depending on Register Address 0x01, Bit 7), with S0 being the LSB in 10-bit input mode (see Table 21). Input standards supported are ITU-R BT.601/656. In 16-/20-bit input mode, the Y pixel data is input on Pins S9 to S2 and CrCb data is input on Pins Y9 to Y2 (see Table 21).
16-/20-Bit Mode Operation
When Register 0x01 Bit 7 = 0, CrCb data is input on the Y bus and Y data is input on the S bus. When Register 0x01 Bit 7 = 1, CrCb data is input on the C bus and Y data is input on Y bus. The 27 MHz clock input must be input on Pin CLKIN_A. Input sync signals are input on the S_VSYNC, S_HSYNC, and S_BLANK pins. Table 21. SD 8-/10-Bit and 16-/20-Bit Configuration
Parameter Register 0x01, Bit 7 = 0 Y Bus S Bus C Bus Register 0x01, Bit 7 = 1 Y Bus S Bus C Bus Configuration 8-/10-Bit Mode 16-/20-Bit Mode CrCb Y
ADV7320/ ADV7321
P_VSYNC, P_HSYNC, P_BLANK
Figure 50. Progressive Scan Input Mode
SIMULTANEOUS STANDARD DEFINITION AND PROGRESSIVE SCAN OR HDTV
Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit) or 101 (SD and HD, SD Oversampled), 110 (SD and HD, HD Oversampled), Respectively YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2 input mode, the HD Y data is input on Pins Y9 to Y0 and the HD CrCb data is input on Pins C9 to C0. If PS 4:2:2 data is interleaved onto a single 10-bit bus, Pins Y9 to Y0 are used for the input port. The input data is to be input at 27 MHz, with the data being clocked upon the rising and falling edges of the input clock. The input mode register at Address 0x01 is set accordingly. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004, the async timing mode must be used. The 8- or 10-bit standard definition data must be compliant with ITU-R BT.601/656 in 4:2:2 format. Standard definition data is input on Pins S9 to S0, with S0 being the LSB. Using 8-bit input format, the data is input on Pins S9 to S2. The clock input for SD must be input on CLKIN_A, and the clock input for HD must be input on CLKIN_B. Synchronization signals are
656/601, YCrCb
656/601, YCrCb
Y CrCb
ADV7320/ ADV7321
3 MPEG2 DECODER 27MHz S_VSYNC, S_HSYNC, S_BLANK CLKIN_A
YCrCb
10
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 49. SD Only Input Mode
05067-025
S[9:0] OR Y[9:0]*
Rev. 0 | Page 38 of 88
ADV7320/ADV7321
optional. SD syncs are input on Pins S_VSYNC, S_HSYNC, and S_BLANK. HD syncs are input on Pins P_VSYNC, P_HSYNC, and P_BLANK.
ADV7320/ ADV7321
MPEG2 DECODER 3 27MHz YCrCb 10 S_VSYNC, S_HSYNC, S_BLANK CLKIN_A S[9:0]
PROGRESSIVE SCAN AT 27 MHZ (DUAL EDGE) OR 54 MHZ
Address[0x01]: Input Mode 100 or 111, Respectively YCrCb progressive scan data can be input at 27 MHz or 54 MHz. The input data is interleaved onto a single 8-/10-bit bus and is input on Pins Y9 to Y0. When a 27 MHz clock is supplied, the data is clocked in upon the rising and falling edges of the input clock, and the clock edge bit [Address 0x01, Bit 1] must be set accordingly. Table 22 provides an overview of all possible input configurations. Figure 54, Figure 55, and Figure 56 show the possible conditions: Cb data on the rising edge, and Y data on the rising edge.
CrCb 10 INTERLACED TO 10 PROGRESSIVE Y 3 27MHz
C[9:0] Y[9:0] P_VSYNC, P_HSYNC, P_BLANK CLKIN_B
05067-027
CLKIN_B
Figure 51. Simultaneous PS and SD Input
Y9-Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
05067-030
05067-032 05067-031
ADV7320/ ADV7321
3 SDTV DECODER 27MHz YCrCb 10 HDTV DECODER 1080i OR 720p OR 1035i S_VSYNC, S_HSYNC, S_BLANK CLKIN_A S[9:0]
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
CLKIN_B
Y9-Y0
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
CrCb 10 Y 10 3 74.25MHz
C[9:0] Y[9:0] P_VSYNC, P_HSYNC, P_BLANK CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
05067-028
Figure 52. Simultaneous HD and SD Input
CLKIN_B
In simultaneous SD/HD input mode, if the two clock phases differ by less than 9.25 ns or more than 27.75 ns, the clock align bit [Address 0x01, Bit 3] must be set accordingly. If the application uses the same clock source for both SD and PS, the clock align bit must be set because the phase difference between both inputs is less than 9.25 ns.
CLKIN_A
PIXEL INPUT DATA
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
Figure 56. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
MPEG2 DECODER YCrCb 27MHz OR 54MHz
ADV7320/ ADV7321
CLKIN_A
CLKIN_B tDELAY < 9.25ns OR tDELAY > 27.75ns
05067-029
Figure 53. Clock Phase with Two Input Clocks
INTERLACED TO PROGRESSIVE
YCrCb
10 3
Y[9:0]
05067-033
P_VSYNC, P_HSYNC, P_BLANK
Figure 57. 10-Bit PS at 27 MHz or 54 MHz
Rev. 0 | Page 39 of 88
ADV7320/ADV7321
Table 22. Input Configurations
Input Format ITU-R BT.656 (See Table 21) Total Bits 8 10 16 20 8 10 PS Only 8 (27 MHz clock) 10 (27 MHz clock) 8 (54 MHz clock) 10 (54 MHz clock) 16 20 24 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:4:4 Input Video YCrCb YCrCb Y CrCb Y CrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb Y CrCb Y CrCb Y Cb Cr Y Cb Cr Y CrCb Y CrCb Y Cb Cr Y Cb Cr G B R G B R YCrCb YCrCb YCrCb YCrCb YCrCb Y CrCb YCrCb Y CrCb Input Pins S9 to S2 (MSB = S9) S9 to S0 (MSB = S9) S9 to S2 (MSB = S9) Y9 to Y2 (MSB = Y9) S9 to S0 (MSB = S9) Y9 to Y0 (MSB = Y9) Y9 to Y2 (MSB = Y9) Y9 to Y0 (MSB = Y9) Y9 to Y2 (MSB = Y9) Y9 to Y0 (MSB = Y9) Y9 to Y2 (MSB = Y9) Y9 to Y0 (MSB = Y9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) S9 to S2 (MSB = S9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) S9 to S0 (MSB = S9) Y9 to Y2 (MSB = Y9) C9 to Y2 (MSB = C9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) S9 to S2 (MSB = S9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) S9 to S0 (MSB = S9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) S9 to S2 (MSB = S9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) S9 to S0 (MSB = S9) S9 to S2 (MSB = S9) Y9 to Y2 (MSB = Y9) S9 to S0 (MSB = S9) Y9 to Y0 (MSB = Y9) S9 to S2 (MSB = S9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) S9 to S0 (MSB = S9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) Subaddress 0x01 0x48 0x01 0x48 0x01 0x48 0x01 0x48 0x01 0x48 0x01 0x48 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x15 0x01 0x13 0x15 0x01 0x13 0x48 0x01 0x13 0x48 0x01 0x13 0x48 0x01 0x13 0x48 Register Setting 0x00 0x00 0x00 0x10 0x00 0x08 0x00 0x18 0x80 0x00 0x80 0x10 0x10 0x40 0x10 0x44 0x70 0x40 0x70 0x44 0x10 0x40 0x10 0x44 0x10 0x00 0x10 0x04 0x20 0x40 0x20 0x44 0x20 0x00 0x20 0x04 0x10 or 0x20 0x00 0x02 0x10 or 0x20 0x04 0x02 0x40 0x40 0x00 0x40 0x44 0x10 0x30, 0x50, or 0x60 0x40 0x00 0x30, 0x50, or 0x60 0x44 0x10
30
4:4:4
HDTV Only
16 20 24
4:2:2 4:2:2 4:4:4
30
4:4:4
HD RGB
24
4:4:4
30
4:4:4
ITU-R BT.656 and PS
8 (SD) 8 (PS) 10 (SD) 10 (PS) 8 16 10 20
4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2
ITU-R BT.656 and PS
ITU-R BT.656 and PS or HDTV
ITU-R BT.656 and PS or HDTV
Rev. 0 | Page 40 of 88
ADV7320/ADV7321 FEATURES
OUTPUT CONFIGURATION
Table 23, Table 24, and Table 25 demonstrate what output signals are assigned to the DACs when the control bits are set accordingly. Table 23. Output Configuration in SD Only Mode
RGB/YUV Output 0x02, Bit 5 0 0 0 0 1 1 1 1 SD DAC Output 1 0x42, Bit 2 0 0 1 1 0 0 1 1 SD DAC Output 2 0x42, Bit 1 0 1 0 1 0 1 0 1 DAC A CVBS G G CVBS CVBS Y Y CVBS DAC B Luma B Luma B Luma U Luma U DAC C Chroma R Chroma R Chroma V Chroma V DAC D G CVBS CVBS G Y CVBS CVBS Y DAC E B Luma B Luma U Luma U Luma DAC F R Chroma R Chroma V Chroma V Chroma
Luma/Chroma Swap 0x44, Bit 7 0 Table as above 1 Table as above, but with all luma/chroma instances swapped
Table 24. Output Configuration in HD/PS Only Mode
HD/PS Input Format YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:4:4 YCrCb 4:4:4 YCrCb 4:4:4 YCrCb 4:4:4 RGB 4:4:4 RGB 4:4:4 RGB 4:4:4 RGB 4:4:4 HD/PS RGB Input 0x15, Bit 1 0 0 0 0 0 0 0 0 1 1 1 1 RGB/YPrPb Output 0x02, Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 HD/PS Color Swap 0x15, Bit 3 0 1 0 1 0 1 0 1 0 1 0 1 DAC A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A DAC B N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A DAC C N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A DAC D G G Y Y G G Y Y G G G G DAC E B R Pb Pr B R Pb Pr B R B R DAC F R B Pr Pb R B Pr Pb R B R B
Table 25. Output Configuration in Simultaneous SD and HD/PS Only Mode
Input Formats ITU-R.BT656 and HD YCrCb in 4:2:2 ITU-R.BT656 and HD YCrCb in 4:2:2 ITU-R.BT656 and HD YCrCb in 4:2:2 ITU-R.BT656 and HD YCrCb in 4:2:2 RGB/YPrPb Output 0x02, Bit 5 0 0 1 1 HD/PS Color Swap 0x15, Bit 3 0 1 0 1 DAC A CVBS CVBS CVBS CVBS DAC B Luma Luma Luma Luma DAC C Chroma Chroma Chroma Chroma DAC D G G Y Y DAC E B R Pb Pr DAC F R B Pr Pb
Rev. 0 | Page 41 of 88
ADV7320/ADV7321
HD ASYNC TIMING MODE
[Subaddress 0x10, Bits 3 and 2] For any input data that does not conform to the standards selectable in input mode, Subaddress 0x10, asynchronous timing mode can be used to interface to the ADV7320/ADV7321. Timing control signals for HSYNC, VSYNC, and BLANK must be programmed by the user. Macrovision and programmable oversampling rates are not available in async timing mode. Table 26. Async Timing Mode Truth Table
P_HSYNC 10 0 01 1 1 P_VSYNC 0 01 0 or 1 0 or 1 0 or 1 P_BLANK1 0 or 1 0 or 1 0 01 10 Reference 50% point of falling edge of trilevel horizontal sync signal 25% point of rising edge of trilevel horizontal sync signal 50% point of falling edge of trilevel horizontal sync signal 50% start of active video 50% end of active video Reference in Figure 58 and Figure 59 a b c d e
In async mode, the PLL must be turned off [Subaddress 0x00, Bit 1 = 1]. Register 0x10 should be programmed to 0x01. Figure 58 and Figure 59 show examples of how to program the ADV7320/ADV7321 to accept a high definition standard other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R BT.1358. Table 26 must be followed when programming the control signals in async timing mode. For standards that do not require a trisync level, P_BLANK must be tied low at all times.
1
When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low at Address 0x10, Bit 6.
CLK P_HSYNC P_VSYNC PROGRAMMABLE INPUT TIMING
P_BLANK SET ADDRESS 0x14, BIT 3 = 1 HORIZONTAL SYNC ACTIVE VIDEO
ANALOG OUTPUT
81 a
66 b
66 c
243 d
1920 e
Figure 58. Async Timing Mode--Programming Input Control Signals for SMPTE 295M Compatibility
CLK P_HSYNC 0 P_VSYNC 1 P_BLANK SET ADDRESS 0x14 BIT 3 = 1 HORIZONTAL SYNC
ACTIVE VIDEO
ANALOG OUTPUT
05067-035
a
b
c
d
e
Figure 59. Async Timing Mode--Programming Input Control Signals for Bilevel Sync Signal
Rev. 0 | Page 42 of 88
05067-034
ADV7320/ADV7321
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal and vertical counters remain reset. When this bit is set back to 0, the internal counters resume counting. The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the HD timing counters only. b. In subcarrier phase reset, a low-to-high transition on the RTC_SCR_TR pin (Pin 31) resets the subcarrier phase to zero on the field following the subcarrier phase reset when the SD RTC/TR/SCR control bits at Address 0x44 are set to 01. This reset signal must be held high for a minimum of one clock cycle. Because the field counter is not reset, it is recommended that the reset signal is applied in Field 7 (PAL) or Field 3 (NTSC). The reset of the phase will then occur on the next field, i.e., Field 1, lined up correctly with the internal counters. The field count register at Address 0x7B can be used to identify the number of the active field. c. In RTC mode, the ADV7320/ADV7321 can be used to lock to an external video source. The real-time control mode allows the ADV7320/ADV7321 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device, such as an ADV7183A video decoder (see Figure 62), that outputs a digital data stream in the RTC format, the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. Write 0x00 into all four subcarrier frequency registers when this mode is used.
SD REAL-TIME CONTROL, SUBCARRIER RESET, AND TIMING RESET
[Subaddress 0x44, Bits 2 and 1] Together with the RTC_SCR_TR pin and SD Mode Register 3 [Address 0x44, Bits 1 and 2], the ADV7320/ADV7321 can be used in (a) timing reset mode, (b) subcarrier phase reset mode, or (c) RTC mode. a. A timing reset is achieved in a low-to-high transition on the RTC_SCR_TR pin (Pin 31). In this state, the horizontal and vertical counters remain reset. Upon releasing this pin (set to low), the internal counters resume counting, starting with Field 1, and the subcarrier phase is reset. The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the SD timing counters only.
DISPLAY
START OF FIELD 4 OR 8
FSC PHASE = FIELD 4 OR 8
307
310
313
320
NO TIMING RESET APPLIED DISPLAY START OF FIELD 1 FSC PHASE = FIELD 1
307
1
2
3
4
5
6
7
21
TIMING RESET PULSE TIMING RESET APPLIED
Figure 60. Timing Reset Timing Diagram
Rev. 0 | Page 43 of 88
05067-036
ADV7320/ADV7321
DISPLAY START OF FIELD 4 OR 8 FSC PHASE = FIELD 4 OR 8
307 NO FSC RESET APPLIED
310
313
320
DISPLAY
START OF FIELD 4 OR 8
FSC PHASE = FIELD 1
307
310
313
320
FSC RESET APPLIED
Figure 61. Subcarrier Reset Timing Diagram
ADV7320/ ADV7321
CLKIN_A LCC1 COMPOSITE VIDEO1 DAC A DAC B GLL RTC_SCR_TR DAC C DAC D Y9-Y0/S9-S05 4 BITS RESERVED SEQUENCE BIT3 21 FSC PLL INCREMENT2 0 RESET BIT4 RESERVED DAC E DAC F 14 BITS H/L TRANSITION COUNT START SUBCARRIER PHASE LOW 128 13 0 RTC TIME SLOT 01 14 19 VALID INVALID SAMPLE SAMPLE 8/LINE LOCKED CLOCK 6768
ADV7183A P19-P10
VIDEO DECODER
Figure 62. RTC Timing and Connections
Rev. 0 | Page 44 of 88
05067-038
5 BITS RESERVED NOTES 1i.e., VCR OR CABLE 2F SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7320/ADV7321 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7320/ADV7321. 3SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 4RESET ADV7320/ADV7321 DDS 5SELECTED BY REGISTER ADDRESS 0x01 BIT 7
05067-037
FSC RESET PULSE
ADV7320/ADV7321
RESET SEQUENCE
A reset is activated with a high-to-low transition on the RESET pin (Pin 33) according to the timing specifications, and the ADV7320/ADV7321 reverts to the default output configuration. Figure 63 illustrates the RESET timing sequence. signal usually occurs after the total number of lines/fields are reached. Conventionally this means that the output video will have corrupted field signals, because one signal is generated by the incoming video and another is generated when the internal lines/field counters reach the end of a field. When the VCR FF/RW sync control is enabled [Subaddress 0x42, Bit 5], the lines/fields counters are updated according to the incoming VSYNC signal, and the analog output matches the incoming VSYNC signal. This control is available in all slave timing modes except Slave Mode 0.
SD VCR FF/RW SYNC
[Subaddress 0x42, Bit 5] In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, i.e., in fast forward or rewind modes. In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields are reached; in rewind mode, this sync
RESET DACs A, B, C
XXXXXX
OFF
VALID VIDEO
DIGITAL TIMING
XXXXXX
DIGITAL TIMING SIGNALS SUPPRESSED
TIMING ACTIVE
05067-039
PIXEL DATA VALID
Figure 63. RESET Timing Sequence
Rev. 0 | Page 45 of 88
ADV7320/ADV7321
VERTICAL BLANKING INTERVAL
The ADV7320/ADV7321 accepts input data that contains VBI data (such as CGMS, WSS, VITS) in SD and HD modes. For the SMPTE 293M (525p) standard, VBI data can be inserted on Lines 13 to 42 of each frame, or on Lines 6 to 43 for the ITU-R BT.1358 (625p) standard. This data can be present on Lines 10 to 20 for SD NTSC and on Lines 7 to 22 for PAL. If VBI is disabled [Address 0x11, Bit 4 for HD; Address 0x43, Bit 4 for SD], VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave modes. In Slave Mode 0, if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten. It is possible to use VBI in this timing mode as well. In Slave Mode 1 or 2, the BLANK control bit must be enabled [Address 0x4A, Bit 3] to allow VBI data to pass through the ADV7320/ADV7321. Otherwise, the ADV7320/ADV7321 automatically blanks the VBI to standard. If CGMS is enabled and VBI is disabled, the CGMS data will nevertheless be available at the output. See Appendix 1--Copy Generation Management System.
SUBCARRIER FREQUENCY REGISTERS
[Subaddresses 0x4C to 0x4F] Four 8-bit registers are used to set up the subcarrier frequency. The value of these registers is calculated using the equation
Subcarrier Frequency Register = Number of subcarrier periods in one video line Number of 27 MHz clk cycles in one video line where the sum is rounded to the nearest integer. For example, in NTSC mode 227.5 32 Subcarrier Register Value = x 2 = 569408543 1716 where: Subcarrier Register Value = 0x21F07C1F SD FSC Register 0: 0x1F SD FSC Register 1: 0x7C SD FSC Register 2: 0xF0 SD FSC Register 3: 0x21 See the MPU Port Description section for more details on accessing the subcarrier frequency registers. x 2 32
Programming the FSC
The subcarrier register value is divided into 4 FSC registers as shown above. To load the value into the encoder, users must write to the FSC registers in sequence, starting with FSC0. The value is not loaded until the FSC4 write is complete. Note that the ADV7320/ADV7321 power-up value for FSC0 is 0x1E. For precise NTSC FSC, write 0x1F to this register.
Rev. 0 | Page 46 of 88
ADV7320/ADV7321
SQUARE PIXEL TIMING MODE
[Address 0x42, Bit 4]
In square pixel mode, the following timing diagrams apply.
ANALOG VIDEO
EAV CODE INPUT PIXELS F00X818 1 C Y Y F00Y000 0 r 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 272 CLOCK 4 CLOCK 344 CLOCK END OF ACTIVE VIDEO LINE
SAV CODE C C 8 1 8 1 F 0 0X CY C YC Y rYb b r 0000F00Yb
NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz)
4 CLOCK
4 CLOCK 1280 CLOCK 4 CLOCK START OF ACTIVE VIDEO LINE
05067-040
1536 CLOCK
Figure 64. EAV/SAV Embedded Timing
HSYNC
FIELD
PAL = 44 CLOCK CYCLES NTSC = 44 CLOCK CYCLES
BLANK
PIXEL DATA
Cb
Y
Cr
Y
05067-041
PAL = 308 CLOCK CYCLES NTSC = 236 CLOCK CYCLES
Figure 65. Active Pixel Timing
Rev. 0 | Page 47 of 88
ADV7320/ADV7321
FILTERS
Table 27 shows an overview of the programmable filters available on the ADV7320/ADV7321.
Table 27. Selectable Filters
Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1.3 MHz SD Chroma 2.0 MHz SD Chroma 3.0 MHz SD Chroma CIF SD Chroma QCIF SD UV SSAF HD Chroma Input HD Sinc Filter HD Chroma SSAF Subaddress 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x42 0x13 0x13 0x13
-40 dB at 3.8 MHz, as shown in Figure 66. This filter can be controlled with Address 0x42, Bit 0.
EXTENDED UV FILTER MODE 0
-10
GAIN (dB)
-20
-30
-40
-60 0 1 2 3 4 FREQUENCY (MHz) 5 6
Figure 66. UV SSAF Filter
If this filter is disabled, one of the chroma filters shown in Table 28 can be selected and used for the CVBS or luma/ chroma signal.
Table 28. Internal Filter Specifications
Filter Luma LPF NTSC Luma LPF PAL Luma Notch NTSC Luma Notch PAL Luma SSAF Luma CIF Luma QCIF Chroma 0.65 MHz Chroma 1.0 MHz Chroma 1.3 MHz Chroma 2.0 MHz Chroma 3.0 MHz Chroma CIF Chroma QCIF Pass-Band Ripple1 (dB) 0.16 0.1 0.09 0.1 0.04 0.127 Monotonic Monotonic Monotonic 0.09 0.048 Monotonic Monotonic Monotonic 3 dB Bandwidth2 (MHz) 4.24 4.81 2.3/4.9/6.6 3.1/5.6/6.4 6.45 3.02 1.5 0.65 1 1.395 2.2 3.2 0.65 0.5
SD Internal Filter Response
[Subaddress 0x40 [7:2]; Subaddress 0x42, Bit 0]
The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. The UV filter supports several different frequency responses, including six low-pass responses, a CIF response, and a QCIF response, as shown in Figure 35 and Figure 36. If SD SSAF gain is enabled, there are 12 response options in the range -4 dB to +4 dB [Subaddress 0x47, Bit 4]. Choose the desired response by programming the correct value via the I2C [Subaddress 0x62]. The variation of frequency responses are shown in Figure 32 and Figure 33. In addition to the chroma filters listed in Table 27, the ADV7320/ADV7321 contains an SSAF filter specifically designed for the color difference component outputs, U and V. This filter has a cutoff frequency of about 2.7 MHz and a gain of
1
Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the -3 dB points. 2 3 dB bandwidth refers to the -3 dB cutoff frequency.
Rev. 0 | Page 48 of 88
05067-044
-50
ADV7320/ADV7321
PS/HD Sinc Filter
[Subaddress 0x13, Bit 3]
0.5 0.4 0.3 0.2
Table 29. Sample Color Values for EIA 770.2 Output Standard Selection
Sample Color White Black Red Green Blue Yellow Cyan Magenta Y Value 235 (EB) 16 (10) 81 (51) 145 (91) 41 (29) 210 (D2) 170 (AA) 106 (6A) Cr Value 128 (80) 128 (80) 240 (F0) 34 (22) 110 (6E) 146 (92) 16 (10) 222 (DE) Cb Value 128 (80) 128 (80) 90 (5A) 54 (36) 240 (F0) 16 (10) 166 (A6) 202 (CA)
GAIN (dB)
0.1 0 -0.1 -0.2 -0.3
05067-042
RGB Matrix
[Subaddresses 0x03 to 0x09]
-0.4 -0.5 0 5 10 15 20 FREQUENCY (MHz) 25
30
Figure 67. HD Sinc Filter Enabled
The internal RGB matrix automatically performs all YCrCb to RGB scaling according to the input standard programmed in the device as selected by input mode Register 0x01 [6:4]. Table 30 shows the options available in this Matrix. Note that it is not possible to do a color space conversion from RGB-in to YPrPb-out. Also, it is not possible to input SD RGB.
Table 30. Matrix Conversion Options
HDTV/SD/PS Reg 0x02,Bit 5 (YUV/RGB OUT) 1 0 0 Reg 0x15, Bit 1 (RGB IN/YCrCb IN, PS/HD Only) 0 0 1
0.5 0.4 0.3 0.2
GAIN (dB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5 10 15 20 FREQUENCY (MHz) 25 30
05067-043
Input YCrCb YCrCb RGB
Output YPrPb RGB RGB
Manual RGB Matrix Adjust Feature
Normally, there is no need to enable this feature in Register 0x02, Bit 3, because the RGB matrix automatically performs color space conversion depending on the input mode chosen (SD/PS, HD) and the polarity of RGB/YPrPb output in Register 0x02, Bit 5 (see Table 30). For this reason, the manual RGB matrix adjust feature is disabled by default. However, For HDTV YCrCb-to-RGB conversion, the RGB matrix must be enabled to invoke the correct coefficients for this color space. The coefficients do not need to be adjusted. The manual RGB matrix adjust feature provides custom coefficient manipulation and is used in progressive scan and high definition modes only. When the manual RGB matrix adjust feature is enabled, the default values in Registers 0x05 to 0x09 are correct for HDTV color space only. The color components are converted according to the 1080i and 720p standards (SMPTE 274M, SMPTE 296M):
Figure 68. HD Sinc Filter Disabled
COLOR CONTROLS AND RGB MATRIX
HD Y Level, HD Cr Level, HD Cb Level
[Subaddresses 0x16 to 0x18]
Three 8-bit registers at Addresses 0x16, 0x17, and 0x18 are used to program the output color of the internal HD test pattern generator, be it the lines of the cross hatch pattern or the uniform field test pattern. They are not functional as color controls for external pixel data input. For this purpose the RGB matrix is used. The values for Y and the color difference signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard. Table 29 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA 770.2.
Rev. 0 | Page 49 of 88
ADV7320/ADV7321
R = Y + 1.575Pr G = Y - 0.468Pr - 0.187Pb B = Y + 1.855Pb
If YPrPb output is selected, the following equations are used:
Y = GY x Y U = BU x Pb V = RV x Pr
This is reflected in the preprogrammed values for GY = 0x13B, GU = 0x3B, GV = 0x93, BU = 0x248, and RV = 0x1F0. If RGB matrix is enabled and another input standard (such as SD or PS) is used, the scale values for GY, GU, GV, BU, and RV must be adjusted according to this input standard color space. The user should consider that the color component conversion might use different scale values. For example, SMPTE 293M uses the following conversion:
R = Y + 1.402Pr G = Y - 0.714Pr - 0.344Pb B = Y + 1.773Pb
Upon power-up, the RGB matrix is programmed with the default values in Table 31.
Table 31. RGB Matrix Default Values
Address 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Default 0x03 0xF0 0x4E 0x0E 0x24 0x92 0x7C
The manual RGB matrix adjust feature can be used to control the HD output levels in cases where the video output does not conform to the standard due to altering the DAC output stages such as termination resistors. The programmable RGB matrix is used for external HD/PS data and is not functional when internal test patterns are enabled. To adjust Registers 0x05 to 0x09, the manual RGB matrix adjust must be enabled [Register 0x02, Bit 3 =1].
When the manual RGB matrix adjust feature is not enabled, the ADV7320/ADV7321 automatically scales YCrCb inputs to all standards supported by this part as selected by the input mode Register 0x01 [6:4].
SD Luma and Color Control
[Subaddresses 0x5C, 0x5D, 0x5E, 0x5F]
SD Y Scale, SD Cr Scale, and SD Cb Scale are three 10-bit-wide control registers that scale the Y, Cb, and Cr output levels. Each of these registers represents the value required to scale the Cb or Cr level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 of its initial level. The value of these 10 bits is calculated using the following equation:
Y, Cr, or Cb Scalar Value = Scale Factor x 512
Programming the RGB Matrix
If custom manipulation of coefficients is required, enable the RGB matrix in Address 0x02, Bit 3, set the output to RGB [Address 0x02, Bit 5], and disable sync on PrPb (default) [Address 0x15, Bit 2]. Enabling sync on RGB is optional [Address 0x02, Bit 4]. GY at Addresses 0x03 and 0x05 controls the green signal output levels. BU at Addresses 0x04 and 0x08 control the blue signal output levels, and RV at Addresses 0x04 and 0x09 control the red signal output levels. To control YPrPb output levels, enable the YUV output [Address 0x02, Bit 5]. In this case GY [Address 0x05; Address 0x03, Bits 0 and 1] is used for the Y output, RV [Address 0x09; Address 0x04, Bits 0 and 1] is used for the Pr output, and BU [Address 0x08; Address 0x04, Bits 2 and 3] is used for the Pb output. If RGB output is selected, the RGB matrix scaler uses the following equations:
G = GY x Y + GU x Pb + GV x Pr B = GY x Y + BU x Pb R = GY x Y + RV x Pr
For example,
Scale Factor = 1.18 Y, Cb, or Cr Scale Value = 1.18 x 512 = 665.6 Y, Cb, or Cr Scale Value = 665 (rounded to the nearest integer) Y, Cb, or Cr Scale Value = 1010 0110 01b
Address 0x5C, SD LSB Register = 0x15 Address 0x5D, SD Y Scale Register = 0xA6 Address 0x5E, SD Cb Scale Register = 0xA6 Address 0x5F, SD Cr Scale Register = 0xA6 Note that this feature affects all interlaced output signals, i.e., CVBS, Y-C, YPrPb, and RGB.
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ADV7320/ADV7321
SD Hue Adjust Value
[Subaddress 0x60]
For example, 1. To add +20 IRE brightness level to an NTSC signal with pedestal, write 0x28 to Address 0x61, SD brightness. 0x[SD Brightness Value] = 0x[IRE Value x 2.015631] = 0x[20 x 2.015631] = 0x[40.31262] = 0x28 2. To add -7 IRE brightness level to a PAL signal, write 0x72 to Address 0x61, SD brightness. [IRE Value| x 2.075631 [7 x 2.015631] = [14.109417] = 0001110b [0001110] into twos complement = [1110010]b = 0x72
Table 32. Brightness Control Values1
Setup Level In NTSC with Pedestal 22.5 IRE 15 IRE 7.5 IRE 0 IRE Setup Level In NTSC No Pedestal 15 IRE 7.5 IRE 0 IRE -7.5 IRE Setup Level In PAL 15 IRE 7.5 IRE 0 IRE -7.5 IRE SD Brightness 0x1E 0x0F 0x00 0x71
The hue adjust value is used to adjust the hue on the composite and chroma outputs. These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7320/ADV7321 provides a range of 22.5 increments of 0.17578125. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits (respectively) of adjustment attainable. Hue Adjust () = 0.17578125 (HCRd - 128) for positive hue adjust value. For example, to adjust the hue by +4, write 0x97 to the hue adjust value register: 4 + 128 = 105d = 0 x97 . 0.17578125 where the sum is rounded to the nearest integer. To adjust the hue by -4, write 0x69 to the hue adjust value register: -4 + 128 = 105d = 0 x69 0.17578125 where the sum is rounded to the nearest integer.
1
Values in the range of 0x3F to 0x44 might result in an invalid output signal.
SD Brightness Control
[Subaddress 0x61]
The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the scaled Y data. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and for PAL, the setup can vary from -7.5 IRE to +15 IRE. The brightness control register is an 8-bit register. Seven bits of this 8-bit register are used to control the brightness level, which can be a positive or negative value.
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ADV7320/ADV7321
SD Brightness Detect
[Subaddress 0x7A]
Double buffering can be activated on the following HD registers: HD gamma A and gamma B curves and HD CGMS registers. Double buffering can be activated on the following SD registers: SD gamma A and gamma B curves, SD Y scale, SD U scale, SD V scale, SD brightness, SD closed captioning, and SD Macrovision Bits 5 to 0.
The ADV7320/ADV7321 allow monitoring the brightness level of the incoming video data. Brightness detect is a read-only register.
Double Buffering
[Subaddress 0x13, Bit 7; Subaddress 0x48, Bit 2]
Double buffered registers are updated once per field upon the falling edge of the Vsync signal. Double buffering improves the overall performance because modifications to register settings will not be made during active video, but take effect upon the start of the active video.
NTSC WITHOUT PEDESTAL 100 IRE +7.5 IRE
0 IRE NO SETUP VALUE ADDED POSITIVE SETUP VALUE ADDED NEGATIVE SETUP VALUE ADDED
-7.5 IRE
05067-069
Figure 69. Examples of Brightness Control Values
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ADV7320/ADV7321
PROGRAMMABLE DAC GAIN CONTROL
DACs A, B, and C are controlled by REG 0A. DACs D, E, and F are controlled by REG 0B. The I2C control registers will adjust the output signal gain up or down from its absolute level.
CASE A GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0A, 0x0B 700mV
Table 33. DAC Gain Control
Reg 0x0A or 0x0B 0100 0000 (0x40) 0011 1111 (0x3F) 0011 1110 (0x3E) ... ... 0000 0010 (0x02) 0000 0001 (0x01) 0000 0000 (0x00) 1111 1111 (0xFF) 1111 1110 (0xFE) ... ... 1100 0010 (0xC2) 1100 0001 (0xC1) 1100 0000 (0xC0) DAC Current (mA) 4.658 4.653 4.648 ... ... 4.43 4.38 4.33 4.25 4.23 ... ... 4.018 4.013 4.008
% Gain 7.5000% 7.3820% 7.3640% ... ... 0.0360% 0.0180% 0.0000% -0.0180% -0.0360% ... ... -7.3640% -7.3820% -7.5000%
Note
(I2C Reset Value, Nominal)
300mV CASE B 700mV NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0x0A, 0x0B
GAMMA CORRECTION
[Subaddresses 0x24 to 0x37 for HD, Subaddresses 0x66 to 0x79 for SD]
300mV
05067-070
Figure 70. Programmable DAC Gain--Positive and Negative Gain
In case A, the video output signal is gained. The absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. The overall gain of the signal is increased from the reference signal. In case B, the video output signal is reduced. The absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. The overall gain of the signal is reduced from the reference signal. The range of this feature is specified for 7.5% of the nominal output from the DACs. For example, if the output current of the DAC is 4.33 mA, the DAC tune feature can change this output current from 4.008 mA (-7.5%) to 4.658 mA (+7.5%). The reset value of the vid_out_ctrl registers is 0x00; therefore, nominal DAC current is output. The following table is an example of how the output current of the DACs varies for a nominal 4.33 mA output current.
Gamma correction is available for SD and HD video. For each standard, there are twenty 8-bit-wide registers. They are used to program the Gamma Correction Curves A and B. HD Gamma Curve A is programmed at Addresses 0x24 to 0x2D, and HD Gamma Curve B is programmed at 0x2E to 0x7. SD Gamma Curve A is programmed at Addresses 0x66 to 0x6F, and SD Gamma Curve B is programmed at Addresses 0x70 to 0x79. Generally gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used. Gamma correction uses the function
Signal OUT = (Signal IN )
where = gamma power factor. Gamma correction is performed on the luma data only. The user may choose either of two curves, Curve A or Curve B. At any one time, only one of these curves can be used. The response of the curve is programmed at 10 predefined locations. In changing the values at these locations, the gamma curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed.
Rev. 0 | Page 53 of 88
ADV7320/ADV7321
For the length of 16 to 240, the gamma correction curve has to be calculated as follows:
y = x
GAMMA CORRECTED AMPLITUDE
300
GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
250 SIGNAL OUTPUT 200 0.5 150
where: y = gamma corrected output x = linear input signal = gamma power factor To program the gamma correction registers, calculate the seven values for y using the following formula:
x yn = (n -16) x (240 - 16) + 16 (240 - 16) where: x(n - 16) = Value for x along x axis at points n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224 yn = value for y along the y axis, which must be written into the gamma correction register For example, y24 = [(8/224)0.5 x 224] + 16 = 58 y32 = [(16/224)0.5 x 224] + 16 = 76 y48 = [(32/224)0.5 x 224] + 16 = 101 y64 = [(48/224)0.5 x 224] + 16 = 120 y80 = [(64/224)0.5 x 224] + 16 = 136 y96 = [(80/224)0.5 x 224] + 16 = 150 y128 = [(112/224)0.5 x 224] + 16 = 174 y160 = [(144/224)0.5 x 224] + 16 = 195 y192 = [(176/224)0.5 x 224] + 16 = 214 y224 = [(208/224)0.5 x 224] + 16 = 232 where the sum of each equation is rounded to the nearest integer. The gamma curves in Figure 71 and Figure 72 are examples only; any user-defined curve is acceptable in the range of 16 to 240.
100 SIGNAL INPUT
05067-071
50
0
0
50
100
150 LOCATION
200
250
Figure 71. Signal Input (Ramp) and Signal Output for Gamma 0.5
300
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
GAMMA CORRECTED AMPLITUDE
250 0.3 200 0.5 150
L NA IG PU IN T
1.5
100
S
1.8
05067-072
50
0
0
50
100
150 LOCATION
200
250
Figure 72. Signal Input (Ramp) and Selectable Output Curves
Rev. 0 | Page 54 of 88
ADV7320/ADV7321
HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS
[Subaddresses 0x20, 0x38 to 0x3D]
The derivative of the incoming signal is compared to the three programmable threshold values: HD Adaptive Filter Threshold A, B, and C. The recommended threshold range is from 16 to 235, although any value in the range of 0 to 255 can be used. The edges can then be attenuated with the settings in HD adaptive filter gain 1, 2, and 3 registers, and HD sharpness filter gain register. According to the settings of the HD adaptive filter mode control, there are two adaptive filter modes available: 1. Mode A is used when adaptive filter mode is set to 0. In this case, Filter B (LPF) will be used in the adaptive filter block. Also, only the programmed values for Gain B in the HD sharpness filter gain and HD Adaptive Filter Gain 1, 2, and 3 are applied when needed. The Gain A values are fixed and cannot be changed. Mode B is used when adaptive filter mode is set to 1. In this mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the HD sharpness filter gain and HD Adaptive Filter Gain 1, 2, and 3 become active when needed.
There are three filter modes available on the ADV7320/ ADV7321: sharpness filter mode and two adaptive filter modes.
HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges shown in Figure 73, the HD sharpness filter must be enabled and the HD adaptive filter enable must be disabled. To select one of the 256 individual responses, the corresponding gain values, which range from -8 to +7, for each filter must be programmed into the HD sharpness filter gain register at Address 0x20.
HD Adaptive Filter Mode
The HD adaptive filter threshold A, B, and C registers, the HD adaptive filter gain 1, 2, and 3 registers, and the HD sharpness gain register are used in adaptive filter mode. To activate the adaptive filter control, the HD sharpness filter and the HD adaptive filter must be enabled. 2.
1.4 1.3 1.2
1.4 1.3 1.2
MAGNITUDE RESPONSE (Linear Scale)
1.5
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK 1.5
1.6 1.5 1.4 1.3 1.2 1.1 1.0
MAGNITUDE
INPUT SIGNAL: STEP
1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka)
MAGNITUDE
1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER B RESPONSE (Gain Kb)
0
2
FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 73. Sharpness and Adaptive Filter Control Block
Rev. 0 | Page 55 of 88
05067-073
6 8 4 10 FREQUENCY (MHz)
12
ADV7320/ADV7321
HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES
HD Sharpness Filter Application
The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in Figure 74. Input data was generated by an external signal source.
Table 34. Sharpness Control
Address 0x00 0x01 0x02 0x10 0x11 0x20 0x20 0x20 0x20 0x20 0x20 Register Setting 0xFC 0x10 0x20 0x00 0x81 0x00 0x08 0x04 0x40 0x80 0x22 Reference1
a b c d e f
1
See Figure 74.
a
R2 1
d
b
R4 R1
e
c
f
1
R2
CH1 500mV REF A
500mV 4.00s
M 4.00s 9.99978ms 1
CH1 ALL FIELDS
CH1 500mV REF A
500mV 4.00s
1
M 4.00s 9.99978ms
CH1 ALL FIELDS
Figure 74. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Values
Rev. 0 | Page 56 of 88
05067-074
ADV7320/ADV7321
Adaptive Filter Control Application
Figure 75 and Figure 76 show typical signals to be processed by the adaptive filter control block. When changing the adaptive filter mode to Mode B [Address 0x15, Bit 6], the output shown in Figure 77 can be obtained.
05067-075
Figure 75. Input Signal to Adaptive Filter Control
Figure 77. Output Signal from Adaptive Filter Control
SD DIGITAL NOISE REDUCTION
[Subaddresses 0x63, 0x64, 0x65]
DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). There are two DNR modes available: DNR mode and DNR sharpness mode. In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal will be subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) will be added to the original signal to boost high frequency components and sharpen the video image. In MPEG systems, it is common to process the video information in blocks of 8 pixels x 8 pixels for MPEG2 systems, or 16 pixels x 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset. The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing.
05067-076
Figure 76. Output Signal after Adaptive Filter Control
The register settings in Table 35 were used to obtain the results shown in Figure 76, i.e., to remove the ringing on the Y signal. Input data was generated by an external signal source.
Table 35. Register Settings for Figure 76
Address 0x00 0x01 0x02 0x10 0x11 0x15 0x20 0x38 0x39 0x3A 0x3B 0x3C 0x3D Register Setting 0xFC 0x38 0x20 0x00 0x81 0x80 0x00 0xAC 0x9A 0x88 0x28 0x3F 0x64
Rev. 0 | Page 57 of 88
05067-077
ADV7320/ADV7321
DNR MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER
In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal.
APPLY DATA CORING GAIN APPLY BORDER CORING GAIN
NOISE SIGNAL PATH
INPUT FILTER BLOCK FILTER OUTPUT < THRESHOLD? - + DNR OUT MAIN SIGNAL PATH SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL
OXXXXXXOOXXXXXXO OFFSET CAUSED BY VARIATIONS IN INPUT TIMING
05067-079 05067-080
Y DATA INPUT
OXXXXXXOOXXXXXXO
FILTER OUTPUT > THRESHOLD
DNR27 - DNR24 = 0x01 O X X X X X X O O X X X X X X O
Figure 79. DNR Offset Control
DNR SHARPNESS MODE
DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER
DNR THRESHOLD
[Address 0x64, Bits 5 to 0]
These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value.
NOISE SIGNAL PATH
BORDER AREA
[Address 0x64, Bit 6]
ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL + DNR OUT
05067-078
INPUT FILTER BLOCK FILTER OUTPUT > THRESHOLD?
Y DATA INPUT
FILTER OUTPUT < THRESHOLD MAIN SIGNAL PATH
+
When this bit is set to Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.
720 x 485 PIXELS (NTSC) 2-PIXEL BORDER DATA
Figure 78. DNR Block Diagram
CORING GAIN BORDER
[Address 0x63, Bits 3 to 0]
These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal.
8 x 8 PIXEL BLOCK
8 x 8 PIXEL BLOCK
Figure 80. DNR Border Area
BLOCK SIZE CONTROL
[Address 0x64, Bit 7]
CORING GAIN DATA
[Address 0x63, Bits 7 to 4]
These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal.
This bit is used to select the size of the data blocks to be processed. Setting the block size control function to Logic 1 defines a 16 pixel x 16 pixel data block, and Logic 0 defines an 8 pixel x 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz.
DNR INPUT SELECT CONTROL
[Address 0x65, Bits 2 to 0]
Three bits are assigned to select the filter, which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that will be DNR processed. Figure 81 shows the filter responses selectable with this control.
Rev. 0 | Page 58 of 88
ADV7320/ADV7321
1.0 FILTER D 0.8
original signal, since this data is assumed to be valid data and not noise. The overall effect is that the signal will be boosted (similar to using Extended SSAF filter).
MAGNITUDE
FILTER C 0.6
BLOCK OFFSET CONTROL
[Address 0x65, Bits 7 to 4]
FILTER B
0.4
0.2 FILTER A 0
05067-081
Four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.
0
1
2
3 4 FREQUENCY (Hz)
5
6
SD ACTIVE VIDEO EDGE
[Subaddress 0x42, Bit 7]
Figure 81. DNR Input Select
DNR MODE CONTROL
[Address 0x65, Bit 4]
This bit controls the DNR mode selected. Logic 0 selects DNR mode; Logic 1 selects DNR sharpness mode. DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the
LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE
When the active video edge feature is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. The scaling factors are x1/8, x1/2, and x7/8. All other active video passes through unprocessed.
SAV/EAV STEP EDGE CONTROL
The ADV7320/ADV7321 have the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing. An algorithm monitors SAV and EAV and determines when the edges are rising or falling too fast. The result is reduced ringing at the start and end of active video for fast transitions. Subaddress 0x42, Bit 7 = 1, enables this feature.
LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED 100 IRE 87.5 IRE 50 IRE
Figure 82. Example of Active Video Edge Functionality
Rev. 0 | Page 59 of 88
05067-082
0 IRE
12.5 IRE 0 IRE
ADV7320/ADV7321
VOLTS IRE:FLT 100
0.5
50
0
0
-50 0 2 4 6
8
10
12
Figure 83. Address 0x42, Bit 7 = 0
VOLTS
IRE:FLT
100
0.5 50
0
0
-50 -2 0 2 4
6
8
10
12
Figure 84. Address 0x42, Bit 7 = 1
Rev. 0 | Page 60 of 88
05067-084
F2 L135
05067-083
F2 L135
ADV7320/ADV7321
HSYNC/VSYNC OUTPUT CONTROL
The ADV7320/21 has the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on P_HSYNC/P_VSYNC, outputting the respective signals on the P_HSYNC and P_VSYNC pins.
Table 36. Hsync Output Control1
HD/ED2 Slave Mode (0x10, bit 2) x x HD/ED Sync Out Enable (0x02, Bit 7) 0 0 SD Sync Out Enable (0x02, Bit 6) 0 1 I2C_HSYNC _gen_sel (0x14, Bit 1) x x
Signal on S_HSYNC Pin Tristate Pipelined SD HSYNC
External HSYNC & VSYNC/Field Mode EAV/SAV Mode x
1
x
0
Pipelined Ext HD/ED HSYNC
Duration - See Appendix 5--SD Timing Modes As per HSYNC timing Same as line blanking interval Same as embedded HSYNC
1 1
x x
0 1
Pipelined HD/ED HSYNC based on AV code H bit Pipelined HD/ED HSYNC based on horizontal counter
______________________________
1 2
In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video. ED = enhanced definition.
Table 37. VSYNC Output Control1
HD/ED2 Slave Mode (0x10, Bit 2) x x HD/ED Sync out Enable (0x02, Bit 7) 0 0 SD Sync Out Enable (0x02, Bit 6) 0 1 I2C_VSYNC _gen_sel (0x14, Bit 2) x x Video Standard x Interlaced Signal on S_VSYNC Pin Tristate Pipelined SD VSYNC/ field Pipelined EXT HD/ED VSYNC or field signal External pipelined field signal based on AV code F bit Pipelined VSYNC based on AV code V bit External pipelined HD/ED VSYNC based on vertical counter External pipelined HD/ED VSYNC based on vertical counter
External HSYNC & VSYNC/Field Mode EAV/SAV Mode
1
x
0
x
Duration See Appendix 5--SD Timing Modes As per Ext VSYNC or field signal Field
1
x
0
All HD interlace standards All HD/ED progressive standards All HD/ED standards except 525p 525p
EAV/SAV Mode
1
x
0
Vertical blanking interval Aligned with serration lines
x
1
x
1
x
1
x
1
Vertical blanking interval
1 2
In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video. ED = enhanced definition.
Rev. 0 | Page 61 of 88
ADV7320/ADV7321 BOARD DESIGN AND LAYOUT
DAC TERMINATION AND LAYOUT CONSIDERATIONS
The ADV7320/ADV7321 contain an on-board voltage reference. The ADV7320/ADV7321 can be used with an external VREF (AD1580). The RSET resistors are connected between the RSET pins and AGND and are used to control the full-scale output current and, therefore, the DAC voltage output levels. For full-scale output, RSET must have a value of 3040 . The RSET values should not be changed. RLOAD has a value of 300 for full-scale output.
GAIN (dB)
0 -10
MAGNITUDE (dB)
CIRCUIT FREQUENCY RESPONSE
0 24n -30 21n -60 18n -90 15n -120
-20 -30 -40
PHASE (Degrees)
-50
GROUP DELAY (Seconds)
12n -150 9n -180 6n -210 3n -240 0 1G
-60 -70 -80 1M
10M 100M FREQUENCY (Hz)
Output buffering on all six DACs is necessary to drive output devices, such as SD or HD monitors. Analog Devices produces a range of suitable op amps for this application, e.g., the AD8061. More information on line driver buffering circuits is given in the relevant op amps' data sheets. An optional analog reconstruction low-pass filter (LPF) may be required as an anti-imaging filter if the ADV7320/ADV7321 are connected to devices that require this filtering. The filter specifications vary with the application.
Figure 86. Filter Plot for Output Filter for SD, 16x Oversampling
4.7H DAC OUTPUT 6.8pF 600 6.8pF 600 4 560 560 3 75 1 BNC OUTPUT
Figure 87. Example of Output Filter for PS, 8x Oversampling
Table 38. External Filter Requirements
Cutoff Frequency (MHz) >6.5 >6.5 >12.5 >12.5 >30 >30 Attenuation -50 dB @ (MHz) 20.5 209.5 14.5 203.5 44.25 118.5
DAC OUTPUT 3 300 4 1 75 470nH 220nH 3 33pF 82pF 75 4 500 500 1 BNC OUTPUT
Application SD SD PS PS HDTV HDTV
Oversampling 2x 16x 1x 8x 1x 2x
Figure 88. Example of Output Filter for HDTV, 2x Oversampling
10H DAC OUTPUT 600 22pF 600 4 560 560 3 75 1 BNC OUTPUT
Table 39. Possible Output Rates from the ADV7320/ADV7321
Input Mode Address 0x01, Bits 6 to 4 SD Only PS Only HDTV Only PLL Address 0x00, Bit 1 Off On Off On Off On Output Rate (MHz) 27 (2x) 216 (16x) 27 (1x) 216 (8x) 74.25 (1x) 148.5 (2x)
Figure 85. Example of Output Filter for SD, 16x Oversampling
Rev. 0 | Page 62 of 88
05067-085
05067-088
05067-087
05067-086
VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER
ADV7320/ADV7321
0 -10 MAGNITUDE (dB) -20 -30
GAIN (dB)
CIRCUIT FREQUENCY RESPONSE
480 18n 400 16n 320 14n 240
There should be a separate analog ground plane and a separate digital ground plane. Power planes should encompass a digital power plane and an analog power plane. The analog power plane should contain the DACs and all associated circuitry, VREF circuitry. The digital power plane should contain all logic circuitry. The analog and digital power planes should be individually connected to the common power plane at a single point through a suitable filtering device, such as a ferrite bead. DAC output traces on a PCB should be treated as transmission lines. It is recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the DAC outputs and should overlay the PCB's ground plane. As well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry. To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the tracks of the individual DAC output pins. The addition of ground tracks between outputs is also recommended.
-40 -50 -60 -70 -80
GROUP DELAY (Seconds)
PHASE (Degrees)
12n 160 10n 80 8n 0 6n -80 4n -160
05067-089
-90 1M
10M 100M FREQUENCY (Hz)
2n -240 0 1G
Figure 89. Filter Plot for Output Filter for PS, 8x Oversampling
0
CIRCUIT FREQUENCY RESPONSE
480 18n
-10
MAGNITUDE (dB)
360 15n 240
-20
GROUP DELAY (Seconds) 120
12n
GAIN (dB)
-30
9n 0 6n PHASE (Degrees) -120 3n -240 0 1G
Supply Decoupling
Noise on the analog power plane can be further reduced by the use of decoupling capacitors. Optimum performance is achieved by the use of 10 nF and 0.1 F ceramic capacitors. Each group of VAA, VDD, or VDD_IO pins should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. A 1 F tantalum capacitor is recommended across the VAA supply in addition to 10 nF ceramic. See the circuit layout in Figure 91.
-40
-50
10M 100M FREQUENCY (Hz)
Figure 90. Filter Plot for Output Filter for HDTV, 2x Oversampling
PCB BOARD LAYOUT
The ADV7320/ADV7321 are optimally designed for lowest noise performance of both radiated and conducted noise. To complement the excellent noise performance of the ADV7320/ ADV7321, it is imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7320/ ADV7321 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and AGND, VDD and DGND, and VDD_IO and GND_IO pins should be kept as short as possible to minimized inductive ringing. It is recommended that a 4-layer printed circuit board is used, with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. Component placement should be carefully considered in order to separate noisy circuits, such as crystal clocks, high speed logic circuitry, and analog circuitry.
05067-090
-60 1M
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, avoid long clock lines to the ADV7320/ADV7321 to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane.
Analog Signal Interconnect
Locate the ADV7320/ADV7321 as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch.
Rev. 0 | Page 63 of 88
ADV7320/ADV7321
For optimum performance, the analog outputs should each be source- and load-terminated, as shown in Figure 91. The termination resistors should be as close as possible to the ADV7320/ADV7321 to minimize reflections. For optimum performance, it is recommended that all decoupling and external components relating to the ADV7320/ADV7321 are located on the same side of the PCB and as close as possible to the ADV7320/ADV7321. Any unused inputs should be tied to ground.
POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP VAA VAA 0.1F VDD_IO 10, 56 5k
45 36 41 1
+ 10nF 0.1F 10nF 0.1F 1F
VAA
VDD
VDD_IO 10nF 0.1F
VAA
COMP1, 2
19 I2C
VAA
VDD VDD_IO VREF 46 100nF DAC A 44 300
1.1k RECOMMENDED EXTERNAL AD1580 FOR OPTIMUM PERFORMANCE
ADV7320/ ADV7321
S0-S9
50 S_HSYNC 49 S_VSYNC 48 S_BLANK
DAC B 43 300 DAC C 42 300 DAC D 39 300
UNUSED INPUTS SHOULD BE GROUNDED
C0-C9
Y0-Y9
63 CLKIN_B 23 P_HSYNC
DAC E 38 300 DAC F 37 300 100 100 VDD_IO 5k 3040 RSET1 47 3040 SELECTION HERE DETERMINES DEVICE ADDRESS VDD_IO 5k VDD_IO 5k I2C BUS
VAA 4.7k +
24 P_VSYNC 25 P_BLANK 33 RESET
4.7F
32 CLKIN_A
SCLK 22 SDA 21
VAA
820pF
34 EXT_LF
ALSB 20 RSET2 35
680 3.9nF
GND_ IO
64
AGND DGND
40
11, 57
05067-091
ALL COMPONENTS IN DASHED BOXES MUST BE LOCATED ON THE SAME SIDE OF THE PCB AS THE ADV7320/21 AND AS CLOSE AS POSSIBLE TO THE ADV7320/21.
Figure 91. ADV7320/ADV7321 Circuit Layout
Rev. 0 | Page 64 of 88
ADV7320/ADV7321 APPENDIX 1--COPY GENERATION MANAGEMENT SYSTEM
PS CGMS
Data Registers 2 to 0
[Subaddresses 0x21, 0x22, 0x23] 525p
FUNCTION OF CGMS BITS
For Word 0 to 6 bits, Word 1 to 4 bits, and Word 2 to 6 bits CRC 6 bits, CRC Polynomial = x 6 + x + 1 where default is preset to 111111.
Using the vertical blanking interval 525p system, 525p CGMS conforms to the CGMS-A EIA-J CPR1204-1 (March 1998) transfer method of video identification information and to the IEC61880 (1998) 525p/60 video system's analog interface for the video and accompanying data. When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS data is inserted on Line 41. The 525p CGMS data registers are at Addresses 0x21, 0x22, and 0x23.
625p
720p System
CGMS data is applied to Line 24 of the luminance vertical blanking interval.
1080i System
CGMS data is applied to Line 19 and Line 582 of the luminance vertical blanking interval.
CGMS FUNCTIONALITY
If SD CGMS CRC [Address 0x59, Bit 4] or PS/HD CGMS CRC [Subaddress 0x12, Bit 7] is set to Logic 1, the last six bits, C19 to C14, which comprise the 6-bit CRC check sequence, are automatically calculated on the ADV7320/ADV7321. This calculation is based on the lower 14 bits (C0 to C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If SD CGMS CRC [Address 0x59, Bit 4] and PS/HD CGMS CRC [Address 0x12, Bit 7] are set to Logic 0, all 20 bits (C0 to C19) are output directly from the CGMS registers (CRC must be calculated by the user manually).
The 625p CGMS conforms to the IEC62375 (2004) 625p/50 video system's analog interface for the video and accompanying data using the vertical blanking interval. When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS data is inserted on Line 43. The 625p CGMS data registers are at Addresses 0x22, and 0x23.
HD CGMS
[Address 0x12, Bit 6]
The ADV7320/ADV7321 support copy generation management system (CGMS) in HDTV mode (720p and 1080i) in accordance with EIAJ CPR-1204-2. The HD CGMS data registers are found at Addresses 0x021, 0x22, and 0x23.
SD CGMS
Data Registers 2 to 0
[Subaddresses 0x59, 0x5A, 0x5B]
The ADV7320/ADV7321 support copy generation management system (CGMS), conforming to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether CGMS data is output on odd and even fields. CGMS data can be transmitted only when the ADV7320/ADV7321 is configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit; see Figure 94.
Rev. 0 | Page 65 of 88
ADV7320/ADV7321
CRC SEQUENCE +700mV 70% 10% REF
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV -300mV 5.8s 0.15s 6T 21.2s 0.22s 22T
05067-092
T = 1/(fH x 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T 30ns
Figure 92. Progressive Scan 525p CGMS Waveform (Line 41)
PEAK WHITE
R = RUN-IN S = START CODE
500mV 25mV
R
S
C0 C1 LSB
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 MSB
SYNC LEVEL
13.7s
05067-093
5.5s 0.125s
Figure 93. Progressive Scan 625p CGMS-A Waveform (Line 43)
+100 IRE REF +70 IRE CRC SEQUENCE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE -40 IRE 11.2s
2.235s 20ns
Figure 94. Standard Definition CGMS Waveform
Rev. 0 | Page 66 of 88
05067-094
49.1s 0.5s
ADV7320/ADV7321
+700mV 70% 10% REF CRC SEQUENCE
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV -300mV 4T 3.128s 90ns
T 30ns 17.2s 160ns 22T T = 1/(fH x 1650/58) = 781.93ns fH = HORIZONTAL SCAN FREQUENCY 1H
Figure 95. HDTV 720p CGMS Waveform
+700mV 70% 10% REF
CRC SEQUENCE
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV -300mV 4T 4.15s 60ns
T 30ns 22.84s 210ns 22T T = 1/(fH x 2200/77) = 1.038s fH = HORIZONTAL SCAN FREQUENCY 1H
Figure 96. HDTV 1080i CGMS Waveform
Rev. 0 | Page 67 of 88
05067-096
05067-095
ADV7320/ADV7321 APPENDIX 2--SD WIDE SCREEN SIGNALING
[Subaddresses 0x59, 0x5A, 0x5B]
The ADV7320/ADV7321 support wide screen signaling (WSS) conforming to the ETS 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long, and the function of each of these bits is shown in Table 40.
Table 40. Function of WSS Bits
Bit Bit 0 to Bit 2 Bit 3 B0 0 1 0 1 0 1 0 1 1 B4 0 1 B5 0 1 B6 0 1 B7 B9 0 1 0 1 B11 0 1 B12 B13
The WSS data is preceded by a run-in sequence and a start code; see Figure 97. If SD WSS [Address 0x59, Bit 7] is set to Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 s from the falling edge of HSYNC) is available for the insertion of video. It is possible to blank the WSS portion of Line 23 with Subaddress 0x61, Bit 7.
B1 0 0 1 1 0 0 1 1 1
B2 0 0 0 0 1 1 1 1 1
B3 1 0 0 1 0 1 1 0 0
Description Aspect Ratio/Format/Position Odd Parity Check of Bit 0 to Bit 2 Aspect Ratio 4:3 14:9 14:9 16:9 16:9 >16:9 14:9 16:9 16:9 Camera Mode Film Mode Standard Coding Motion Adaptive Color Plus No Helper Modulated Helper Reserved
Format Full Format Letterbox Letterbox Letterbox Letterbox Letterbox Full Format N/A
Position N/A Center Top Center Top Center Center N/A
B10 0 0 1 1
No Open Subtitles Subtitles in Active Image Area Subtitles out of Active Image Area Reserved No Surround Sound Information Surround Sound Mode Reserved Reserved
500mV RUN-IN START SEQUENCE CODE W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 ACTIVE VIDEO
11.0s
05067-097
38.4s 42.5s
Figure 97. WSS Waveform Diagram
Rev. 0 | Page 68 of 88
ADV7320/ADV7321 APPENDIX 3--SD CLOSED CAPTIONING
[Subaddresses 0x51 to 0x54]
The ADV7320/ADV7321 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by Logic 1 start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in the SD closed captioning registers [Addresses 0x53 to 0x54]. The ADV7320/ADV7321 also support the extended closed captioning operation, which is active during even fields and encoded on Scan Line 284. The data for this operation is stored in the SD closed captioning registers [Addresses 0x51 to 0x52]. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7320/ ADV7321. All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled.
FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA608 describe the closed captioning information for Line 21 and Line 284. The ADV7320/ADV7321 use a single buffering method. This means that the closed captioning buffer is only 1 byte deep; therefore, there will be no frame delay in outputting the closed captioning data, unlike other 2-byte-deep buffering systems. The data must be loaded one line before it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn will load the new data (2 bytes) in every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes, on Line 21, or a TV will not recognize them. If there is a message such as "Hello World" that has an odd number of characters, it is important to add a blank character at the end so that the end-of-caption, 2-byte control code lands in the same field.
10.5 0.25s
12.91s 7 CYCLES OF 0.5035MHz CLOCK RUN-IN TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A R T P A R I T Y P A R I T Y
50 IRE
D0-D6
D0-D6
BYTE 0 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003s 27.382s 33.764 s
BYTE 1
Figure 98. Closed Captioning Waveform, NTSC
Rev. 0 | Page 69 of 88
05067-098
ADV7320/ADV7321 APPENDIX 4--TEST PATTERNS
The ADV7320/ADV7321 can generate SD and HD test patterns.
T
T
05067-099
2
CH2 200mV
M 10.0s A CH2 30.6000s T
1.20V
CH2 100mV
M 10.0s CH2 1.82600ms T
EVEN
Figure 99. NTSC Color Bars
Figure 102. PAL Black Bar (-21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)
T
T
05067-100
2
CH2 200mV
M 10.0s A CH2 30.6000s T
1.21V
CH2 200mV
M 4.0s CH2 1.82944ms T
EVEN
Figure 100. PAL Color Bars
T
Figure 103. 525p Hatch Pattern
T
05067-101
2
2
CH2 100mV
M 10.0s CH2 1.82380ms T
EVEN
CH2 200mV
M 4.0s CH2 1.84208ms T
EVEN
Figure 101. NTSC Black Bar (-21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV,18 mV, 23 mV)
Figure 104. 625p Hatch Pattern
Rev. 0 | Page 70 of 88
05067-104
05067-103
2
05067-102
2
ADV7320/ADV7321
T T
05067-105
2
2
CH2 200mV
M 4.0s CH2 1.82872ms T
EVEN
CH2 100mV
M 4.0s CH2 1.82936ms T
EVEN
Figure 105. 525p Field Pattern
T T
Figure 107. 525p Black Bar (-35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 35 mV)
2
05067-106
2
CH2 200mV
M 4.0s CH2 1.84176ms T
EVEN
CH2 100mV
M 4.0s CH2 1.84176ms T
EVEN
Figure 106. 625p Field Pattern
Figure 108. 625p Black Bar (-35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 5 mV)
Rev. 0 | Page 71 of 88
05067-108
05067-107
ADV7320/ADV7321
The register settings in Table 41 are used to generate an SD NTSC CVBS output on DAC A, S-video on DACs B and C, and YPrPb on DACs D, E, and F. Upon power-up, the subcarrier registers are programmed with the appropriate values for NTSC. All other registers are set as normal/default.
Table 41. NTSC Test Pattern Register Writes
Subaddress 0x00 0x40 0x42 0x44 0x4A Register Setting 0xFC 0x10 0x40 0x40 (internal test pattern on) 0x08
The register settings in Table 43 are used to generate a 525p hatch pattern on DAC D, E, and F. All other registers are set as normal/default.
Table 43. 525p Test Pattern Register Writes.
Subaddress Ox00 0x01 0x10 0x11 0x16 0x17 0x18 Register Setting 0xFC 0x10 0x00 0x05 0xA0 0x80 0x80
For PAL CVBS output on DAC A, the same settings are used, except that Subaddress 0x40 is programmed to 0x11 and the FSC registers are programmed as shown in Table 42.
Table 42. PAL FSC Register Writes
Subaddress 0x4C 0x4D 0x4E 0x4F Description FSC0 FSC1 FSC2 FSC3 Register Setting 0xCB 0x8A 0x09 0x2A
For 625p hatch pattern on DAC D, the same register settings are used except that Subaddress 0x10 = 0x18.
Note that when programming the FSC registers, the user must write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full FSC value to be written is only accepted after the FSC3 write is complete.
Rev. 0 | Page 72 of 88
ADV7320/ADV7321 APPENDIX 5--SD TIMING MODES
[Subaddress 0x4A]
MODE 0 (CCIR-656)--SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 0)
The ADV7320/ADV7321 are controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. If Pins S_VSYNC, S_HSYNC, and S_BLANK are not used, they should be tied high during this mode. Blank output is available.
ANALOG VIDEO
EAV CODE INPUT PIXELS C F00X818 1 Y Y r F00Y000 0 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 CLOCK 4 CLOCK PAL SYSTEM (625 LINES/50Hz) 280 CLOCK END OF ACTIVE VIDEO LINE
SAV CODE 8 1 8 1 F 0 0 X CY C YC Y CY C b r b 0000F00Yb r
4 CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz)
4 CLOCK 4 CLOCK
1440 CLOCK 1440 CLOCK
START OF ACTIVE VIDEO LINE
Figure 109. SD Slave Mode 0
Rev. 0 | Page 73 of 88
05067-109
ADV7320/ADV7321
MODE 0 (CCIR-656)--MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 1)
The ADV7320/ADV7321 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on S_HSYNC, the V bit is output on S_BLANK, and the F bit is output on S_VSYNC.
DISPLAY VERTICAL BLANK
DISPLAY
522 H V
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
F
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
260 H V
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
F
ODD FIELD
EVEN FIELD
Figure 110. SD Master Mode 0, NTSC
Rev. 0 | Page 74 of 88
05067-110
ADV7320/ADV7321
DISPLAY VERTICAL BLANK DISPLAY
622 H V
623
624
625
1
2
3
4
5
6
7
21
22
23
F
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
309 H
310
311
312
313
314
315
316
317
318
319
320
334
335
336
V F ODD FIELD EVEN FIELD
05067-111
Figure 111. SD Master Mode 0, PAL
ANALOG VIDEO
H
F
V
Figure 112. SD Master Mode 0, Data Transitions
Rev. 0 | Page 75 of 88
05067-112
ADV7320/ADV7321
MODE 1--SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 1 0)
In this mode, the ADV7320/ADV7321 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624. HSYNC, BLANK, and FIELD are input on S_HSYNC, S_BLANK, and S_VSYNC.
DISPLAY
DISPLAY VERTICAL BLANK
522 HSYNC BLANK FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
260 HSYNC BLANK FIELD
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 113. SD Slave Mode 1 (NTSC)
Rev. 0 | Page 76 of 88
05067-113
ADV7320/ADV7321
MODE 1--MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7320/ADV7321 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC, BLANK, and FIELD are output on S_HSYNC, S_BLANK, and S_VSYNC.
DISPLAY
DISPLAY VERTICAL BLANK
622 HSYNC BLANK FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 114. SD Slave Mode 1 (PAL)
HSYNC
FIELD
PAL = 12 x CLOCK/2 NTSC = 16 x CLOCK/2 BLANK
PIXEL DATA
Cb
Y
Cr
Y
05067-115
PAL = 132 x CLOCK/2 NTSC = 122 x CLOCK/2
Figure 115. SD Timing Mode 1--Odd/Even Field Transitions Master/Slave
Rev. 0 | Page 77 of 88
05067-114
ADV7320/ADV7321
MODE 2-- SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7320/ADV7321 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624. HSYNC, BLANK, and VSYNC are input on S_HSYNC, S_BLANK, and S_VSYNC, respectively.
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC BLANK VSYNC
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD DISPLAY
ODD FIELD DISPLAY VERTICAL BLANK
260 HSYNC BLANK VSYNC
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 116. SD Slave Mode 2 (NTSC)
DISPLAY
VERTICAL BLANK
DISPLAY
622 HSYNC BLANK VSYNC
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
309 HSYNC BLANK VSYNC
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 117. SD Slave Mode 2 (PAL)
Rev. 0 | Page 78 of 88
05067-117
05067-116
ADV7320/ADV7321
MODE 2--MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7320/ADV7321 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624. HSYNC, BLANK, and VSYNC are output on S_HSYNC, S_BLANK, and S_VSYNC, respectively.
HSYNC
VSYNC
PAL = 12 x CLOCK/2 NTSC = 16 x CLOCK/2 BLANK
PIXEL DATA PAL = 132 x CLOCK/2 NTSC = 122 x CLOCK/2
Cb
Y
Cr
Y
05067-118
Figure 118. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC PAL = 12 x CLOCK/2 NTSC = 16 x CLOCK/2 BLANK PAL = 864 x CLOCK/2 NTSC = 858 x CLOCK/2
PIXEL DATA PAL = 132 x CLOCK/2 NTSC = 122 x CLOCK/2
Cb
Y
Cr
Y
Cb
05067-119
Figure 119. SD Timing Mode 2 Odd-to-Even Field Transition
Rev. 0 | Page 79 of 88
ADV7320/ADV7321
MODE 3--MASTER/SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 1 0 OR X X X X X 1 1 1)
In this mode, the ADV7320/ADV7321 accept or generate horizontal sync and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624. HSYNC, BLANK, and VSYNC are output in master mode and input in slave mode on S_VSYNC, S_BLANK, and S_VSYNC, respectively.
DISPLAY DISPLAY VERTICAL BLANK
522 HSYNC BLANK FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
260 HSYNC BLANK FIELD
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 120. SD Timing Mode 3 (NTSC)
DISPLAY VERTICAL BLANK DISPLAY
622 HSYNC BLANK FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
EVEN FIELD
ODD FIELD
Figure 121. SD Timing Mode 3 (PAL)
Rev. 0 | Page 80 of 88
05067-121
05067-120
ADV7320/ADV7321 APPENDIX 6--HD TIMING
DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
P_VSYNC
P_HSYNC
DISPLAY
FIELD 2
VERTICAL BLANKING INTERVAL
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
P_VSYNC
05067-122
P_HSYNC
Figure 122. 1080i HSYNC and VSYNC Input Timing
Rev. 0 | Page 81 of 88
ADV7320/ADV7321 APPENDIX 7--VIDEO OUTPUT LEVELS
HD YPrPb OUTPUT LEVELS
INPUT CODE EIA-770.2, STANDARD FOR Y OUTPUT VOLTAGE
INPUT CODE EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE
940
940
700mV
700mV
64 300mV
64 300mV
EIA-770.3, STANDARD FOR Pr/Pb
EIA-770.2, STANDARD FOR Pr/Pb 960
OUTPUT VOLTAGE
OUTPUT VOLTAGE
960
600mV 512
512
700mV
700mV
05067-125
05067-123
64
64
Figure 123. EIA 770.2 Standard Output Signals (525p/625p)
INPUT CODE EIA-770.1, STANDARD FOR Y OUTPUT VOLTAGE 782mV
Figure 125. EIA 770.3 Standard Output Signals (1080i/720p)
INPUT CODE 1023 Y-OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE
940
700mV 714mV
64 64 286mV 300mV
EIA-770.1, STANDARD FOR Pr/Pb 960
INPUT CODE OUTPUT VOLTAGE 1023
Pr/Pb-OUTPUT LEVELS FOR FULL INPUT SELECTION
OUTPUT VOLTAGE
700mV 512 700mV
05067-124
64 300mV
05067-126
64
Figure 124. EIA 770.1 Standard Output Signals (525p/625p)
Figure 126. Output Levels for Full Input Selection
Rev. 0 | Page 82 of 88
ADV7320/ADV7321
RGB OUTPUT LEVELS
Pattern: 100%/75% Color Bars
700mV
525mV
700mV
525mV
300mV
300mV
700mV
525mV
700mV
525mV
300mV
300mV
700mV
525mV
05067-127
700mV
525mV
05067-129
300mV
300mV
Figure 127. PS RGB Output Levels
Figure 129. SD RGB Output Levels--RGB Sync Disabled
700mV
525mV
700mV
525mV
300mV
300mV
0mV
0mV
700mV
525mV
700mV
525mV
300mV
300mV
0mV
0mV
700mV
525mV
700mV
525mV
300mV
05067-128
300mV
05067-130
0mV
0mV
Figure 128. PS RGB Output Levels--RGB Sync Enabled
Figure 130. SD RGB Output Levels--RGB Sync Enabled
Rev. 0 | Page 83 of 88
ADV7320/ADV7321
Pattern: 100% Color Bars
YPrPb LEVELS--SMPTE/EBU N10
700mV
700mV
WHITE YELLOW CYAN GREEN CYAN GREEN YELLOW WHITE
700mV
WHITE YELLOW CYAN GREEN
MAGENTA RED BLUE BLACK
MAGENTA RED BLUE BLACK
05067-132
MAGENTA RED BLUE BLACK
05067-131
Figure 132. Pb Levels--PAL
Figure 131. Pb Levels--NTSC
Figure 133. Pr Levels--NTSC
05067-133
Rev. 0 | Page 84 of 88
700mV
300mV
300mV 700mV
WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
05067-135
WHITE
700mV
WHITE YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
05067-134
YELLOW CYAN GREEN
MAGENTA RED BLUE BLACK
Figure 134. Pr Levels--PAL
Figure 135. Y Levels--NTSC
Figure 136. Y Levels--PAL
05067-136
ADV7320/ADV7321
VOLTS IRE:FLT
VOLTS 0.6
100
0.4
0.5 50
0.2
0
0
0
-50
F1 L76
05067-137
L608 0 10 20 30 40 50 60
0 10 20 30 40 50 60 MICROSECONDS PRECISION MODE OFF APL = 44.5% SYNCHRONOUS SYNC = A 525 LINE NTSC FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00V AT 6.72s
MICROSECONDS NOISE REDUCTION: 0.00dB PRECISION MODE OFF APL = 39.1% SYNCHRONOUS SOUND-IN-SYNC OFF 625 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2, 3, 4 SLOW CLAMP TO 0.00 AT 6.72s
Figure 137. NTSC Color Bars 75%
VOLTS IRE:FLT 0.4 50 VOLTS 0.5
Figure 140. PAL Color Bars 75%
0.2
0
0 0
-0.2 -50 -0.4 F1 L76
05067-138
05067-141
-0.5 L575 10 20 30 40 50 60
0 10 20 30 40 50 60 NOISE REDUCTION: 15.05dB MICROSECONDS PRECISION MODE OFF APL NEEDS SYNC SOURCE. SYNCHRONOUS SYNC = B 525 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00 AT 6.72s
MICROSECONDS NO BUNCH SIGNAL APL NEEDS SYNC SOURCE. PRECISION MODE OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SOUND-IN-SYNC OFF SLOW CLAMP TO 0.00 AT 6.72s FRAMES SELECTED 1
Figure 138. NTSC Chroma
VOLTS IRE:FLT 0.6 0.5 0.4 50 0 0.2 0 0 0 VOLTS
Figure 141. PAL Chroma
F2 L238 10 20 30 40 50 60
05067-139
-0.2
L575 0 10 20 30 40 50 60 70
NOISE REDUCTION: 15.05dB MICROSECONDS PRECISION MODE OFF APL = 44.3% SYNCHRONOUS SYNC = SOURCE 525 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00 AT 6.72s
MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF APL NEEDS SYNC SOURCE. SYNCHRONOUS SOUND-IN-SYNC OFF 625 LINE PAL NO FILTERING FRAMES SELECTED 1 SLOW CLAMP TO 0.00 AT 6.72s
Figure 139. NTSC Luma
Figure 142. PAL Luma
Rev. 0 | Page 85 of 88
05067-142
05067-140
-0.2
ADV7320/ADV7321 APPENDIX 8--VIDEO STANDARDS
0HDATUM SMPTE 274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING *1 4T EAV CODE INPUT PIXELS F F 00F 00V H* 4 CLOCK SAMPLE NUMBER 2112 2116 2156 0 2199 44 188 272T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE 4T SAV CODE 1920T DIGITAL ACTIVE LINE CY r
F 0 0F C C V F 0 0 H* b Y r 4 CLOCK 192
2111
FOR A FRAME RATE OF 30Hz: 40 SAMPLES FOR A FRAME RATE OF 25Hz: 480 SAMPLES
Figure 143. EAV/SAV Input Data Timing Diagram--SMPTE 274M
SMPTE 293M
ANALOG WAVEFORM EAV CODE F F00V F 0 0 H* 4 CLOCK SAMPLE NUMBER 719 723 736 0HDATUM 799 DIGITAL HORIZONTAL BLANKING FVH* = FVH AND PARITY BITS SAV: LINE 43-525 = 200H SAV: LINE 1-42 = 2AC EAV: LINE 43-525 = 274H EAV: LINE 1-42 = 2D8 ANCILLARY DATA (OPTIONAL) SAV CODE F 0 0F V F 0 0 H* 4 CLOCK 853 857 0 719 DIGITAL ACTIVE LINE C C bYr C YrY
INPUT PIXELS
Figure 144. EAV/SAV Input Data Timing Diagram--SMPTE 293M
Rev. 0 | Page 86 of 88
05067-144
05067-143
FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1-562: F = 0 SAV/EAV: LINE 563-1125: F = 1 SAV/EAV: LINE 1-20; 561-583; 1124-1125: V = 1 SAV/EAV: LINE 21-560; 584-1123: V = 0
ADV7320/ADV7321
ACTIVE VIDEO VERTICAL BLANK ACTIVE VIDEO
522
523
524
525
1
2
5
6
7
8
9
12
13
14
15
16
42
43
44
Figure 145. SMPTE 293M (525p)
ACTIVE VIDEO
VERTICAL BLANK
ACTIVE VIDEO
05067-145
622
623
624
625
1
2
4
5
6
7
8
9
10
11
12
13
43
44
45
Figure 146. ITU-R BT.1358 (625p)
DISPLAY VERTICAL BLANKING INTERVAL
747
748
749
750
1
2
3
4
5
6
7
8
25
26
27
744
745
Figure 147. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
05067-148
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
Figure 148. SMPTE 274M (1080i)
Rev. 0 | Page 87 of 88
05067-147
05067-146
ADV7320/ADV7321 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
1
12.00 BSC SQ
64 49 48 PIN 1
SEATING PLANE
TOP VIEW
(PINS DOWN)
10.00 BSC SQ
1.45 1.40 1.35
10 6 2
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
VIEW A
16 17 32 33
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BCD
Figure 149. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADV7320KSTZ1 ADV7321KSTZ1 EVAL-ADV7320EB EVAL-ADV7321EB Temperature Range 0C to 70C 0C to 70C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Evaluation Board Package Option ST-64-2 ST-64-2
1
Z = Pb-free part.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05067-0-10/04(0)
Rev. 0 | Page 88 of 88

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