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Freescale Semiconductor, Inc.
MOTOROLA
Semiconductor Products Sector Engineering Bulletin
Order Number EB346/D: Rev. 2 4/20/2001
Functional Differences Between DSP56302 and DSP56309 (formerly DSP56302A)
Contents
1 2 3 4 5 6 Purpose of this Document .......... 1 Differences Overview ................. 1 Input Power Changes ................. 2 I/O Power Changes..................... 4 PLL Input Capacitor (CPCAP)... 4 Operating Modes ........................ 5
1
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Purpose of this Document
To meet the increasing demands for higher performance and lower power consumption, an advanced DSP56302 has been designed; it is was formerly known as DSP302A; it is now designated DSP56309. The new part is designed to be a functional replacement for the DSP56302. This document summarizes the differences between the DSP56302 and the DSP56309.
2
Differences Overview
The primary functional differences between the DSP56302 and the DSP56309 are due to inherent differences between the two design technologies. Table 1. compares the two chips.
(c) Motorola, Inc. 1996, 2001
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Functional Differences between DSP56302 and DSP56309 (formerly DSP56302A)
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Table 1. Functional Comparison of DSP56302 and DSP56309 Feature
Operating frequency Technology Input power
DSP56302
66 MHz down to 0 Hz 0.5 micron VCC = 3.0-3.6 V combined core and I/O power and ground
DSP56309
100 MHz down to 0 Hz Sub 0.4 micron Split power: Core VCC (3.0-3.6 V currently) I/O VCC (3.0-3.6 V currently) A pinout change is required to support the split power configuration. See Section 3 for more information and a description of the pinout change for the 144-pin TQFP package. Tolerant up to 3.6 V 144-pin TQFP or 196-pin PBGA Uses the following rules: For MF 4: CPCAP = [(680 x MF) - 120] pF For MF > 4: CPCAP = (1100 x MF) pF See Table 3 for details.
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I/O pins Package PLL input capacitor (CPCAP)
5 V tolerant (exceptions: see data sheet) 144-pin TQFP Uses the following rules: For MF 4: CPCAP = [(500 x MF) - 150] pF For MF > 4: CPCAP = (690 x MF) pF
Operating modes Other functionality
All memory, control functions, and peripherals are identical. Refer to the DSP56309 Technical Data Sheet (order by DSP56309/D) for a detailed description of these features.
3
Input Power Changes
One method to increase the operating frequency of an integrated circuit is to "shrink" the die (that is, reduce the die dimensions, both linearly and vertically). Reducing the die size can yield additional benefits, such as a reduction of power consumption, but can also result in other functional changes. The DSP56309 is a "shrink" of the DSP56302. This die size reduction enables the DSP56309 to achieve higher operating frequencies. Decreasing the die size, however, requires a reduction of the thickness of the oxide dielectrics, which also reduces the maximum allowable voltages across some oxides within the die. To support future "shrinks" of the DSP56309 while maximizing system level compatibility, Motorola has elected to separate the power supply networks on the die. This split allows the I/O pins to operate over a voltage range which is different from that used by the core digital logic. Although the initial release of this product specifies the same voltage ranges for the I/O pins and the core logic, future versions of the DSP56309 or its derivatives are likely to have reduced core logic VCC requirements (for example, 2.5 V and lower voltages) while the I/O levels use a higher level (for example, 3.3 V). This allows Motorola to continue aggressively to "shrink" the device, while preserving the ability to maintain system level compatibility. The split-power design requires a modification in the chip pinout. A top view of the DSP56309 TQFP package is shown in Figure 1. Table 2 lists the pin differences between the DSP56302 and the DSP56309.
Note:
The power input for the core logic is designated VCCQ for the DSP56302. For the DSP56309, the independent core logic input voltage is designated V CCQL, while the independent I/O input voltage is designated VCCQH. VCCQL should be connected to the core input power supply. VCCQH and all other input power (VCCA, VCCC, VCCD, VCCH, VCCP, and VCCS) should be connected to the external input power supply.
2
DSP56302 and DSP56309 Functional Differences
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D6 D5 D4 D3 GNDD VCCD D2 D1 D0 A17 A16 A15 GNDA VCCQH A14 A13 A12 VCCQL GNDQ A11 A10 GNDA VCCA A9 A8 A7 A6 GNDA VCCA A5 A4 A3 A2 GNDA VCCA A1
D7 D8 VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQL GNDQ D20 VCCD GNDD D21 D22 D23 MODD MODC MODB MODA TRST TDO TDI TCK TMS SC12 SC11
109
(Top View)
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Orientation Mark
1
37
A0 BG AA0 AA1 RD WR GNDC VCCC BB BR TA BCLK BCLK CLKOUT GNDC VCCC VCCQL EXTAL GNDQ XTAL CAS AA2 AA3 VCCQH GNDP1 GNDP PCAP VCCP RESET HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4
HACK HREQ
HDS
SRD1 STD1 SC02 SC01 DE PINIT SRD0 VCCS GNDS STD0 SC10 SC00 RXD TXD SCLK SCK1 SCK0 VCCQL GNDQ VCCQH
VCCS GNDS TIO2 TIO1 TIO0
HCS
HA9 HA8 HAS HAD7 HAD6 HAD5
HRW
AA1538
Note: Arrows () indicate the pins that are different from the DSP56302, as listed in Table 2. on page 4.
Figure 1. DSP56309 Thin Quad Flat Pack (TQFP), Top View
DSP56302 and DSP56309 Functional Differences
3
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Table 2. Pin Differences between DSP56302 and DSP56309 (144-pin TQFP package)
Pin Name Pin DSP56302 18 20 49 56 91 VCCQ NC NC VCCQ VCCQ VCCA VCCQ DSP56309 VCCQL VCCQH VCCQH VCCQL VCCQL VCCQH VCCQL
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95 126
VCCQ = input voltage for core logic VCCQL = independent input voltage for core logic NC = not connected VCCQH = independent input voltage for I/O lines VCCA = voltage for external address lines Unlisted pins are the same for both chips.
A pinout for the 196-pin PBGA package is included in the DSP56309 Technical Data Sheet. This package will include the split power configuration described for the 144-pin TQFP package.
4
I/O Power Changes
The DSP56302 supports 5 V inputs for its peripherals. Complete requirements are described in the DSP56302 Technical Data Sheet. The DSP56309 supports 3.3 V inputs. Detailed voltage requirements are included in the DSP56309 Technical Data Sheet.
5
PLL Input Capacitor (CPCAP)
The process change results in a changed requirement for computing the size of CPCAP, the capacitor used with the PCAP input. Table 1 lists the new formulas for computing the value of this input capacitor for the DSP56309.
4
DSP56302 and DSP56309 Functional Differences
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6
Operating Modes
The operating modes of the DSP56302 are documented in the DSP56302 User's Manual. Table 3. documents the operating modes of the DSP56309. Modes that differ from those of the DSP56302 are highlighted in the table.
Table 3. DSP56309 Operating Modes
Mode 0 1 2 3
MODD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
MODC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
MODB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
MODA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Reset Vector $C00000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $008000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000 $FF0000
Description Expanded mode Reserved Reserved Reserved Reserved Reserved Reserved Reserved Expanded mode Boot from byte-wide memory Boot from SCI Reserved HI08 bootstrap in ISA mode HI08 bootstrap in HC11 non-multiplexed mode HI08 bootstrap in 8051 multiplexed bus mode HI08 bootstrap in MC68302 mode
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4 5 6 7 8 9 A B C D E F
DSP56302 and DSP56309 Functional Differences
5
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Order Number EB346/D
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