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Rev 0; 4/03
Hex Nonvolatile Potentiometer with I/O and Memory
General Description
The DS3930 contains six 256-position nonvolatile (NV) potentiometers, 64 bytes of NV user EEPROM memory, and four programmable NV I/O pins. The six potentiometers all share a common low side. The potentiometers are separated into two groups of three 50k potentiometers in parallel. Each group of three potentiometers shares a common high side and forms an equivalent resistance of 16.6k (three 50k potentiometers in parallel). Six 256-Position NV Potentiometers Four General-Purpose NV I/O Pins 64 Bytes of User EEPROM Memory 0 to 5.5V on Any Potentiometer Terminal, Independent of VCC All Six Potentiometers Share a Common Low Side Potentiometers Separated into Two Groups of Three Potentiometers, Each Sharing a Common High Side 2-Wire Serial Interface Wide Supply Range (2.7V to 5.5V) Up to Eight DS3930s Can Share the Same 2-Wire Bus
Features
DS3930
Applications
RF Transceivers Voltage References Power Supply Calibration Mobile Phones and PDAs Fiber Optic Transceiver Modules Portable Electronics Radio Tuners Small, Low-Cost Replacement for Mechanical Potentiometers
Ordering Information
PART DS3930E PIN-PACKAGE 20 TSSOP
Pin Configuration
TOP VIEW
A0 1 A1 2 A2 3 SDA 4 SCL 5 I/O0 6 I/O1 7 I/O2 8 VCC 9 GND 10 20 HI0-2
VCC
Typical Operating Circuit
VCC A0 HI0-2 W0 W1 W2 LO0-5 WIPER TERMINALS
19 W0
A1
18 W1 17 W2
4.7k
4.7k A2
DS3930
16 LO0-5 15 HI3-5 14 W3 13 W4 12 W5 11 I/O3
2-WIRE INTERFACE
SDA SCL I/O0 DIGITAL NONVOLATILE I/O VCC I/O1 I/O2 VCC GND
DS3930
HI3-5 W3 W4 W5 I/O3 DIGITAL NONVOLATILE I/O WIPER TERMINALS
DECOUPLING CAP 0.1F
TSSOP
_____________________________________________ Maxim Integrated Products
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Hex Nonvolatile Potentiometer with I/O and Memory DS3930
ABSOLUTE MAXIMUM RATINGS
Voltage on VCC Relative to Ground...................... -0.5V to +6.0V Voltage on I/O0, I/O1, I/O2, I/O3, SDA, SCL, A0, A1, and A2 Relative to Ground* .............................. -0.5V to (VCC + 0.5V) Voltage on LO0-5, W0-5, HI0-2, and HI3-5 Relative to Ground ............................................-0.5V to +6.0V Current Through W0-5 ........................................................ 1mA *This voltage must not exceed 6.0V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range .......................... -40C to +85C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature.................. See IPC/JEDEC J-STD-020A
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40 to +85C)
PARAMETER Supply Voltage Input Logic 1 (SDA, SCL, A0, A1, A2, I/O0, I/O1, I/O2, I/O3) Input Logic 0 (SDA, SCL, A0, A1, A2, I/O0, I/O1, I/O2, I/O3) Wiper Current Potentiometer Terminals (LO0-5, W0-5, HI0-2, and HI3-5) SYMBOL VCC VIH VIL IW VCC = +2.7V to +5.5V (Note 1) CONDITIONS MIN +2.7 0.7 x VCC -0.3 -1 -0.3 TYP MAX +5.5 VCC + 0.3 0.3 x VCC +1 +5.5 UNITS V V V mA V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA = -40C to +85C, unless otherwise specified.)
PARAMETER Input Leakage Low-Level Output Voltage (SDA, I/O0, I/O1, I/O2, I/O3) I/O Capacitance I/O Pullup Resistor Value Standby Current SYMBOL IIL VOL1 VOL2 CI/O RI/O ISTBY 3V (Note 2) 5V (Note 2) 3.5 5 160 195 3mA sink current 6mA sink current CONDITIONS MIN -1 0 0 TYP MAX +1 0.4 0.6 10 7.0 300 350 UNITS A V V pF k A
2
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Hex Nonvolatile Potentiometer with I/O and Memory
ANALOG RESISTOR CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA = -40C to +85C, unless otherwise specified.)
PARAMETER End-to-End Resistance Wiper Resistance Factory Default Wiper Setting Factory Default I/O Setting POT-to-POT Matching Differential Linearity Integral Linearity End-to-End Temperature Coefficient Ratiometric Temperature Coefficient 3 potentiometers in parallel -1 -0.5 -1 -250 0 2 RW SYMBOL CONDITIONS TA = +25C (three 50k pots in parallel) MIN 13.2 TYP 16.5 400 FF 0F +1 +0.5 +1 +250 MAX 19.8 1000 UNITS k Hex Hex LSB LSB LSB ppm/C ppm/C
DS3930
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA = -40C to +85C, unless otherwise specified.)
PARAMETER SCL Clock Frequency (Note 3) Bus Free Time Between STOP and START Condition (Note 3) Hold Time (Repeated) START Condition (Notes 3 and 4) Low Period of SCL Clock (Note 3) High Period of SCL Clock (Note 3) SYMBOL fSCL tBUF tHD:STA tLOW tHIGH Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode CONDITIONS MIN 0 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 TYP MAX 400 100 UNITS kHz s s s s
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Hex Nonvolatile Potentiometer with I/O and Memory DS3930
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V; TA = -40C to +85C, unless otherwise specified.)
PARAMETER Data Hold Time (Notes 3, 5, 7) Data Setup Time (Note 3) Start Setup Time (Note 3) Rise Time of Both SDA and SCL Signals (Note 7) Fall Time of Both SDA and SCL Signals (Note 7) Setup Time for STOP Condition Capacitive Load for Each Bus EEPROM Write Time SYMBOL tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode (Note 7) (Note 8) 5 CONDITIONS MIN 0 0 100 250 0.6 4.7 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.0 400 20 300 1000 300 300 TYP MAX 0.9 0.9 UNITS s ns s ns ns s pF ms
EEPROM CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA = -40C to +85C, unless otherwise specified.)
PARAMETER Writes SYMBOL +70C CONDITIONS MIN 50,000 TYP MAX UNITS
Note 1: Note 2: Note 3:
Note 4: Note 5: Note 6: Note 7: Note 8:
All voltages are referenced to ground. ISTBY specified for VCC equal 3.0V and 5.0V, SDA = SCL = VCC, and I/O0 = I/O1 = I/O2 = I/O3 = A0 = A1 = A2 = GND. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns +250ns = 1250ns before the SCL line is released. After this period, the first clock pulse is generated. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. CB--total capacitance of one bus line in picofarads, timing referenced to 0.9VCC and 0.1VCC. EEPROM write begins after a STOP condition occurs.
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Hex Nonvolatile Potentiometer with I/O and Memory
Typical Operating Characteristics
(VCC = 5.0V; TA = +25C, unless otherwise specified.)
SUPPLY CURRENT vs. TEMPERATURE
DS3930 toc01
DS3930
WIPER VOLTAGE vs. WIPER SETTING
DS3930 toc02
ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY
680 SUPPLY CURRENT (A) 620 560 500 440 380 320 260 VCC = 3V VCC = 5V SDA = VCC
DS3930 toc03
220 SDA = SCL = 5V 200 SUPPLY CURRENT (A) VCC = 5V
6 5 4 3 2 HI = 5V LO = GND
740
180 VCC = 3V 160
140
VOLTAGE (V)
1 0 -40 -20 0 20 40 60 80 100 0 50 100 150 200 250 300 TEMPERATURE (C) SETTING (DEC)
120
200 0 100 200 300 400 SCL FREQUENCY (kHz)
WIPER VOLTAGE vs. POWER-UP VOLTAGE
DS3930 toc04
END-TO-END RESISTANCE % CHANGE FROM +25C vs. TEMPERATURE
DS3930 toc05
VOLTAGE DIVIDER % CHANGE FROM +25C vs. TEMPERATURE
RESISTANCE % CHANGE (FROM +25C) 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -40 -20 0 20 40 60 80 100 HI = VCC LO0-5 = GND POSITION 127
DS3930 toc06
3.0 2.5 WIPER VOLTAGE (V) 2.0 1.5 1.0 0.5 0 0
RESISTANCE % CHANGE (FROM +25C)
HI = 5V, LO = GND POSITION 127
1.00 0.80 0.60 0.40 0.20 0 -0.20 -0.40 -0.60 -0.80 -1.00 -40 -20 0 20 40 60 80 3 POTS IN PARALLEL MEASURED FROM HI0-2 TO LO0-5
0.20
EEPROM RECALL
FOLLOWS VCC
CHANGES TO PROGRAMMED VALUE ONCE EEPROM IS RECALLED
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 POWER-UP VOLTAGE (V)
100
TEMPERATURE (C)
TEMPERATURE (C)
ALL POTS DNL (LSB)
DS3930 toc08
POTS 0, 2, 4, INL (LSB)
DS3930 toc07
POTS 1, 3, 5 INL (LSB)
0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
DS3930 toc09
0.10 0.08 0.06 0.04 DNL (LSB)
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
0.5
0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 0 25 50 75 100 125 150 175 200 225 250 POSITION (DEC)
0 25 50 75 100 125 150 175 200 225 250 POSITION (DEC)
0 25 50 75 100 125 150 175 200 225 250 POSITION (DEC)
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Hex Nonvolatile Potentiometer with I/O and Memory DS3930
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME A0 A1 A2 SDA SCL I/O0 I/O1 I/O2 VCC GND I/O3 W5 W4 W3 HI3-5 LO0-5 W2 W1 W0 HI0-2 Address Input Address Input 2-Wire Serial Data I/O. This pin is for serial data transfer to and from the device. 2-Wire Serial Clock Input. The serial clock input is used to clock data into and out of the device. General-Purpose NV I/O Pin General-Purpose NV I/O Pin General-Purpose NV I/O Pin Supply Voltage Ground General-Purpose NV I/O Pin Wiper Terminal of Potentiometer 5 Wiper Terminal of Potentiometer 4 Wiper Terminal of Potentiometer 3 High-End Terminal of Potentiometers 3 to 5. This is the common high-side terminal of potentiometers 3, 4, and 5. Low-End Terminal of the Potentiometers. This is the common low-side terminal of all six potentiometers. Wiper Terminal of Potentiometer 2 Wiper Terminal of Potentiometer 1 Wiper Terminal of Potentiometer 0 High-End Terminal of Potentiometers 0 to 2. This is the common high-side terminal of potentiometers 0, 1, and 2. FUNCTION Address Input. The address input pins determine the 2-wire address of the device.
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Hex Nonvolatile Potentiometer with I/O and Memory DS3930
EEPROM VCC 00h 3Fh 40h EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h FFh 64 BYTES OF EEPROM RESERVED POT0 CONTROL POT1 CONTROL POT2 CONTROL POT3 CONTROL POT4 CONTROL POT5 CONTROL I/O CONTROL I/O STATE RESERVED 8 50k POT4 W4 8 50k POT3 LO0-5 HI3-5 W3 8 50k POT2 8 POT1 50k W1 8 POT0 HI0-2 W0
50k
W2
8 50k SDA SCL 8 A0 A1 A2 GND 2-WIRE INTERFACE 4 I/O CELL X 4
POT5
W5
I/O0 I/O1 I/O2 I/O3
DS3930
Figure 1. DS3930 Functional Diagram
Detailed Description
The DS3930 contains six NV potentiometers with 64 bytes of NV user memory (EEPROM), and four programmable NV I/O pins. Figure 1 is a functional diagram of the DS3930.
Potentiometers
The six potentiometers share a common low side and are separated into two groups of three potentiometers, each group sharing a common high side. The six 256position potentiometers are controllable using six 8-bit EEPROM registers through the 2-wire interface.
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Hex Nonvolatile Potentiometer with I/O and Memory DS3930
I/O Signals
The I/O pins can be used as general-purpose digital I/O signals. The I/O pins have CMOS outputs with an internal pullup resistor (see Figure 2). The I/O pins are configured with the I/O Control register (F6h) and monitored with the I/O State register (F7h). The I/O Control register controls the state of the internal pullup resistor (RI/O) with bits 7 to 4 and the I/O pin setting with bits 3 to 0 (see Table 1). The read-only values of the I/O State register contains the values of the I/O pin setting bits of the I/O Control register unless the I/O output is tri-stated. When the I/O is tri-stated the I/O State register will read high or low depending on the external source on the I/O pin. Since the I/O pins are controlled by EEPROM, the number of writes is limited.
Table 1. I/O Pin Truth Table
PULLUP CTRL (I/O CONTROL REGISTER) (BITS 7 TO 4) 0 0 1 1 I/O PIN SETTING (I/O CONTROL REGISTER) (BITS 3 TO 0) 0 1 0 1 I/O PIN OUTPUT
0 1 0 Pullup disabled (HI-Z)
Memory
The memory map is shown in Table 2.
Table 2. Memory Map
ADDRESS 00h to 3Fh 40h to EFh F0h F1h F2h F3h F4h F5h F6h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F7h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F8h to FFh FF 0X BIT DEFAULT (HEX) FF FF FF FF FF FF FF FF 0F FUNCTION 64 bytes of general-purpose EEPROM Reserved Controls potentiometer 0 Controls potentiometer 1 Controls potentiometer 2 Controls potentiometer 3 Controls potentiometer 4 Controls potentiometer 5 I/O Control Set to 0 to enable I/O3 pullup, set to 1 to disable pullup Set to 0 to enable I/O2 pullup, set to 1 to disable pullup Set to 0 to enable I/O1 pullup, set to 1 to disable pullup Set to 0 to enable I/O0 pullup, set to 1 to disable pullup Sets I/O3 to 0 or 1 Sets I/O2 to 0 or 1 Sets I/O1 to 0 or 1 Sets I/O0 to 0 or 1 I/O State 0 0 0 0 Contains state of I/O3 pin (read only) Contains state of I/O2 pin (read only) Contains state of I/O1 pin (read only) Contains state of I/O0 pin (read only) Reserved
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Hex Nonvolatile Potentiometer with I/O and Memory
VCC PULLUP CTRL
found in Figures 3 and 5. Timing information for the 2wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications. The following bus protocol has been defined: * Data transfer can be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy: Both data and clock lines remain high. Start Data Transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data Valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 3 and 5 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and
DS3930
I/O PIN SETTING
RI/O
I/O INPUT ESD
Figure 2. I/O Cell
2-Wire Serial Port Operation
The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a "master." The devices that are controlled by the master are "slaves." The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions. The DS3930 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. Timing diagrams for the 2-wire serial port can be
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 3. 2-Wire Data Transfer Protocol _____________________________________________________________________ 9
Hex Nonvolatile Potentiometer with I/O and Memory DS3930
byte, a not acknowledge can be returned. The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. The DS3930 can operate in the following three modes: Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3930 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. 3) Slave Address: This is the first byte received following the start condition from the master device. The slave address consists of a 4-bit control code. For the DS3930, this is set as 1010 binary for read/write operations. The next bits of the slave address are the device address (A2-A0). The last bit of the slave address (R/W) defines the operation to be performed. When set to a `1,' a read operation is selected, and when set to a `0,' a write operation is selected (see Figure 4). Following the start condition, the DS3930 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 1010 device identifier, the appropriate device address bit, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line. 1)
MSB 1 0 1 0 A2 A1 A0
LSB R/W
Figure 4. Slave Address
terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS3930 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received
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REA
D/W
RIT EB
DEVICE IDENTIFIER
DEVICE ADDRESS
IT
Hex Nonvolatile Potentiometer with I/O and Memory DS3930
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 5. 2-Wire AC Characteristics
TYPICAL 2-WIRE WRITE TRANSACTION MSB START 1 0 1 0 LSB A2* A1* A0* R/W DEVICE ADDRESS READ/ WRITE SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
DEVICE IDENTIFIER
REGISTER ADDRESS
DATA
EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) A0h F0h DATA SLAVE SLAVE A) SINGLE-BYTE WRITE POT SETTING 11110000 START 1 0 1 0 0 0 0 0 ACK ACK -WRITE TO POT 0 REGISTER A0h B) SINGLE-BYTE READ -READ FROM POT 0 REGISTER START 1 0 1 0 0 0 0 0 F0h SLAVE SLAVE 11110000 ACK ACK
SLAVE ACK A1h
STOP
REPEATED START
10100001
DATA SLAVE POT SETTING MASTER NACK ACK
STOP
A0h C) SINGLE-BYTE WRITE -SET I/O0 PIN TO A "1" START 1 0 1 0 0 0 0 0
F6h DATA SLAVE SLAVE XXX0XXX1 11110110 ACK ACK
SLAVE ACK
STOP
D) MULTIPLE BYTE WRITE -2 BYTE WRITE TO EEPROM
A0h 00h START 1 0 1 0 0 0 0 0 SLAVE 0 0 0 0 0 0 0 0 SLAVE ACK ACK A0h 00h START 1 0 1 0 0 0 0 0 SLAVE 0 0 0 0 0 0 0 0 SLAVE ACK ACK
DATA SLAVE ACK
DATA SLAVE ACK STOP
A1h REPEATED START 10100001 SLAVE ACK
DATA MASTER ACK
DATA MASTER NACK STOP
E) MULTIPLE BYTE READ -2 BYTE READ FROM EEPROM
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET BY THE ADDRESS PINS.
Figure 6. Example 2-Wire Transactions
Applications Information
Power Supply Decoupling
To achieve the best results when using the DS3930, decouple the power supply with a 0.1F high-quality, ceramic, surface-mount capacitor. Surface-mount com-
ponents minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. The capacitor should be placed as close as possible to the VCC and GND pins.
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Hex Nonvolatile Potentiometer with I/O and Memory DS3930
Wiper Resistance
One difference between digital potentiometers and mechanical potentiometers is the wiper resistance. The wiper resistance (RW) is a result of the interconnecting materials on the IC between the internal resistive elements and the wiper pin. This can be modeled by using an ideal potentiometer, with a resistance of RW connected between the ideal wiper and wiper terminal of the digital potentiometer.
Chip Information
TRANSISTOR COUNT: 27,000 SUBSTRATE CONNECTED TO GROUND.
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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