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| Preliminary DFBM-CS320 DFBM-CS320 Bluetooth TM Module Class 2 Wireless communication module TM compliant with Bluetooth Specification V2.0+EDR FEATURES: Suitable for Cellular Phones, PDAs, Digital Cameras, ......... Small size and Low Profile using high-density packaging technology for space critical applications. High sensitivity for better reception. Various interfaces: UART or USB. Wide operating temperature range: -40~+85J . Device diagram UART / USB SPI PIO/AIO PCM Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 General Specification Bluetooth Specification Frequency Modulation Transmission Rate Receive Sensitivity Maximum Output Power Operating Voltage Current Consumption Operating Temperature Antenna Impedance Package Size Version 2.0+EDR 2402~2480MHz GFSK/DQPSK/8DPSK 721K / 2M / 3M bps Typ. -78dBm +4dBm(Class 2) 2.7~3.6V 35 mA -40~+85J 50[ 7.5*6.5*1.6 (mm) Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 Interface Interface Antenna UART Interface SPI Interface USB Interface PCM Interface PIO Interface AIO Interface Description External Antenna 50[ TX, RX, RTS, CTS(9600bps~1.5Mbps) Synchronous Serial Interface for firmware download Full speed Universal Serial Bus interface Supports continuous transmission and reception of PCM encoded audio data over Bluetooth 8 terminals 1 terminals Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 External Reference Clock Input The DFBM-CS320 RF local oscillator and internal digital clocks are derived from the reference clock at DFBM-CS320 XTAL_IN input. This reference may be either an external clock or from a crystal connected between XTAL_IN and XTAL_OUT. The external clock can either be a digital level square wave or sinusoidal and this may be directly coupled to XTAL_IN without the need for additional components. If the peaks of the reference clock are below 0 V or above 1.8 V, it must be driven through a DC blocking capacitor (~33pF) connected to XTAL_IN. The external clock signal should meet the specifications as below table. Min Frequency Duty cycle Edge Jitter (At Zero Crossing) Signal Level 7.5 MHz 20 : 80 400mV pk-pk Typ 16 MHz 50 : 50 Max 40 MHz 80 : 20 15ps rms 1.8V * * If the external clock is driven through a DC blocking capacitor then maximum allowable amplitude is reduced from 1.8V to 800mV pk-pk. Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 Host transport selection The firmware configures itself when it boots by reading the values on a set of PIO pins. Pin Values PIO[0] PIO[1] PIO[4] Host Transport Features Auto System Clock Auto Baud Rate Adaptation Adaptation 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 BCSP (default) Available (*1) Available (*2) Available (*2) Not appropriate Not appropriate Available (*2) Available (*2) Available (*2) - BCSP with UATR configured to Available (*1) use 2 stop bits and no parity USB, 16 MHz crystal USB, 26 MHz crystal Three-wire UART H4DS UART (H4) Undefined Not available Not available Available (*1) Available (*1) Available (*1) - (*1) If a UART-based host transport is selected and the firmware does not know its clock frequency (because PSKEY_ANA_FREQ contains no value), then the firmware attempts to lock on to the available system clock signal. Use of this mechanism implies booting the firmware twice, as described in [AUTOBAUD]. PSKEY_ANA_FREQ has no default value. (*2) If a UART-based host transport is selected and the baud rate defined in PSKEY_UART_BAUDRATE is zero (the default value), then the baud rate adaptation process is invoked, as described in [AUTOBAUD]. If the PS Key contains a non-zero baud rate then the UART is configured with this value. If the system clock adaptation mechanism is used, it may result in the processor running slower than normal, so the consequent (measured) baud rate will also be affected. Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 Application Circuit Crystal mode circuit External mode circuit *****Note: The circuits are offered without warranty and Delta is unable to accept any liability for direct or consequential loss associated with their use. It is therefore important for designers to ensure that their design is properly evaluated in a Design Verification Test. Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 Pin description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Name Vdd_3.15V VREG_IN Vdd_1.8V PIO_1 PIO_0 PIO_10 AUX_DAC Gnd ANT Gnd PIO_9 PIO_2 PIO_3 SPI_MOSI SPI_MISO SPI_CLK SPI_CSB Description Supply Voltage (3.15V , 2.7~3.6), INPUT Supply Voltage (3.15V , 2.2~3.6V), INPUT Supply Voltage (1.8V), OUTPUT Programmable input/output line Programmable input/output line Programmable input/output line Voltage DAC Ground RF input/output Ground Programmable input/output line Programmable input/output line Programmable input/output line Serial Peripheral Interface data input Serial Peripheral Interface data output Serial Peripheral Interface clock Chip select for Serial Peripheral Interface, active low Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Gnd Reset B PIO_5 PIO_4 USB_DP USB_DN PCM_IN PCM_CLK PCM_SYNC PCM_OUT Gnd UART_RTS UART_TX UART_CTS UART_RX AIO_0 XTAL_OUT XTAL_IN Gnd Ground An active low reset Programmable input/output line Programmable input/output line USB data plus with selectable internal 1.5kohm pull-up resistor USB data minus Synchronous data input Synchronous data clock Synchronous data sync Synchronous data output Ground UART request to send active low UART data output active high UART clear to send active low UART data input active high Analogue Programmable input/output Drive for crystal For crystal or external clock input Ground Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 Dimensions (mm) Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change Preliminary DFBM-CS320 Record of changes Date May 18,2005 Content of change Preliminary document release Maker Susan Lin Contact information: Website: http://www.deltaww.com Email: Richard.Meng@delta.com.tw (Worldwide) Email: Data Sheet May 18, 2005 Proprietary Information and Specifications are Subject to Change |
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