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CS5540 Low-Power, Low-Voltage, 24 - Bit ADC
Features
l
Description
The CS5540 is a low-power and low-voltage analog-to-digital converter (ADC), which achieves highly accurate conversions using a simple non-programmable interface that is easy to understand and design-in. It is optimized to convert analog signals in DC measurement applications, such as temperature and pressure measurement, and various portable devices where low-power consumption is required. To accommodate these applications, the ADC integrates analog input and reference buffers for increased input impedance and a two-channel multiplexer. The CS5540 includes a digital filter, which achieves simultaneous rejection of 50/60 Hz signals and provides single conversion settling at 6.7 SPS throughput. Absolute accuracy is achieved via continuous internal self-calibration. The device draws a nominal 330 A. Low-power, low-voltage operation, and a simple serial interface make the CS5540 an ideal device for low-cost, power-conscious DC measurement applications. ORDERING INFORMATION CS5540-AS -40 C - +85 C 16-Pin SSOP
Analog-to-Digital Converter
- Linearity Error: 0.0015% FS - RMS Noise: 4 V
l Two
Channel Differential MUX l Buffered, Fully Differential Analog and Voltage Reference Inputs l Scalable VREF Input: 0.1 V to Analog Supply l High Absolute Accuracy via Self-Calibration l Fixed Digital Filter
- Single Conversion Settling at 6.7 SPS - Simultaneous 50/60 Hz Rejection
l Simple
Serial Interface
and MicrowireTM Compatible - Schmitt Trigger on Serial Clock (SCLK)
l Low
SPITM
Power
- Single +3.0 V Supply - 330 A Supply Current - 10 A in Sleep Mode
VA+
VREF+
VREF-
OSC1 OSC2
VD+
CHS
X1
X1
Clock Generator
Serial Interface CS
AIN1+ AIN1AIN2+ AIN2Input Mux
X1
Differential 4th Order
Modulator X1
Digital Filter
Calibration Register
SDO SCLK
Output Register
VA-
DGND
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
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TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 2. GENERAL DESCRIPTION ..................................................................................................... 10 2.1 Analog Input ..................................................................................................................... 10 2.1.1 Analog Input Model ............................................................................................. 10 2.2 Voltage Reference Input .................................................................................................. 11 2.2.1 Voltage Reference Input Model ........................................................................... 11 2.3 Power Supply Arrangements ........................................................................................... 12 2.4 Clock Generator ............................................................................................................... 12 2.5 Serial Port Interface ......................................................................................................... 12 2.6 Input Channel Selector .................................................................................................... 12 2.6.1 Switching Channels ............................................................................................. 13 2.7 Serial Port and Data Conversions .................................................................................... 13 2.7.1 Reading Conversions .......................................................................................... 14 2.7.2 Output Coding ..................................................................................................... 14 2.7.3 Digital Filter ......................................................................................................... 14 2.8 Sleep Mode ...................................................................................................................... 15 2.9 Power-Up and Initialization .............................................................................................. 16 2.10 PCB Layout .................................................................................................................... 16 3. PIN DESCRIPTIONS .............................................................................................................. 17 4. SPECIFICATION DEFINITIONS ............................................................................................. 19 5. PACKAGE DIMENSIONS ...................................................................................................... 20
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
SPI is a trademark of Motorola Inc. Microwire is a trademark of National Semiconductor Corp. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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LIST OF FIGURES
Figure 1. Continuous Running SCLK Timing (Not to Scale) ........................................................... 9 Figure 2. SDO Read Timing (Not to Scale)..................................................................................... 9 Figure 3. Multiplexer Configuration. .............................................................................................. 10 Figure 4. Input model for AIN+ and AIN- pins. .............................................................................. 10 Figure 5. Resolution vs. Voltage Reference.................................................................................. 11 Figure 6. Input model for VREF+ and VREF- pins........................................................................ 11 Figure 7. CS5540 Configured with a single +3.0 V Supply. .......................................................... 12 Figure 8. Command and Data Word Timing. ................................................................................ 13 Figure 9. Self Calibration of Offset. ............................................................................................... 13 Figure 10. Self Calibration of Gain. ............................................................................................... 14 Figure 11. Digital Filter Response................................................................................................. 15
LIST OF TABLES
Table 1. Output Conversion Data Register Description (24 bits + flags) ...................................... 15 Table 2. CS5540 24-Bit Bipolar Output Coding ............................................................................ 15
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1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 C; VA+ = +3.0 V 5%, VA- = 0 V, VD+ = 3.0 V 5%, DGND = 0 V, VREF+ = 2.5 V, VREF- = 0 V, MCLK = 32.768 kHz, OWR (Output Word Rate) = 6.7 SPS, Input Range = 2.5 V Differential, Vcm=1.25 V. (See Note 1.)
Parameter Accuracy Linearity Error No Missing Codes Offset Error Offset Drift Full Scale Error Full Scale Drift RMS Noise Bandwidth (-3 dB) (Note 3) (Notes 4 and 5) (Note 2) (Notes 2 and 3) 24 0.0015 16 20 8 1 4 11.96 0.003 TBD 31 %FS Bits LSB24 nV/C ppm ppm/C V Hz Min Typ Max Units
Notes: 1. Specifications guaranteed by design, characterization, and/or test. 2. Specification applies to the device only and does not include any effects caused by external parasitic thermocouples. 3. Drift over specified temperature range after power-up at 25 C. 4. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 C. 5. For peak-to-peak noise multiply the RMS value by 6.6.
* Specifications are subject to change without notice.
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ANALOG CHARACTERISTICS (Continued)
Parameter Analog Input Common Mode + Signal on AIN+ or AINSingle Supply Dual Supplies CVF Current on AIN+, AINInput Leakage for MUX when off Common Mode Rejection Input Capacitance Voltage Reference Input Range (VREF+) - (VREF-) (Note 8) (Note 7) 0.1 (Note 9) 1/OWR s 2.5 20 120 120 12 MCLK/2 (VA+) (VA-) V nA dB dB pF Hz dc 50, 60Hz (Note 6) 0.0 VA12 10 120 120 8 VA+ VA+ V V nA pA dB dB pF Min Typ Max Units
CVF Current on VREF+ and VREFCommon Mode Rejection Input Capacitance Dynamic Characteristics Modulator Sampling Frequency Filter Settling to 1/2 LSB (Full Scale Step) 6.7 SPS OWR Power Supplies DC Power Supply Currents (Normal Mode) IA+ ID+ Normal Mode Sleep Mode dc Positive Supplies dc Negative Supplies dc 50, 60 Hz
(Note 10) -
225 25 750 30 80 80
280 36 1000 -
A A W W dB dB
Power Consumption Power Supply Rejection
Notes: 6. See Section 2.1, "Analog Input". 7. See Section 2.2, "Voltage Reference Input". 8. Absolute voltages on VREF+ and VREF- must be less than or equal to the supply voltages. 9. The CS5540 includes a digital filter. The filter which achieves simultaneous rejection of 50/60 Hz provides single conversion settling at a 6.7 SPS throughput. 10. All outputs unloaded. All inputs at CMOS levels.
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5%, VA- = 0 V, VD+ = 3.0 V 5%, DGND = 0 V.) (See Notes 1 and 11.) All voltage levels measured relative to DGND. Parameter High-Level Input Voltage: All Pins Except OSC1, SCLK OSC1 SCLK OSC1, SCLK OSC1 SCLK SDO, Iout = -1.0 mA SDO, Iout = 1.6mA Symbol VIH VIH VIH VIL VIL VIL VOH VOL Iin IOZ Cout Min 0.6VD+ TBD (VD+)-0.45 (VD+)-.25 Typ 1 9 Max 0.16VD+ TBD 0.6 0.4 10 10 Units V V V V V V V V A A pF
3 V DIGITAL CHARACTERISTICS (TA = 25 C; VA+ = 3.0 V
Low-Level Input Voltage:
All Pins Except
High-Level Output Voltage: Low-Level Output Voltage: Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance
Notes: 11. All measurements performed under static conditions.
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ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 12.)
Parameter DC Power Supplies (Notes 13 and 14) Positive Digital Positive Analog Negative Analog (Notes 15 and 16) (Note 17) AIN and VREF pins Symbol VD+ VA+ VAIIN IOUT PDN VINA VIND TA Tstg Min -0.3 -0.3 -0.3 (VA-) + (-0.3) -0.3 -40 -65 Typ Max +4.0 +4.0 +0.3 10 25 500 (VA+)+0.3 (VD+)+0.3 +85 +150 Units V V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 12. All voltages are measured with respect to the digital ground pin (DGND). 13. VA+ and VA- must satisfy {(VA+) - (VA-)} +4.0 V. 14. VD+ and VA- must satisfy {(VD+) - (VA-)} +4.0 V. 15. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 16. Transient current of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 17. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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SWITCHING CHARACTERISTICS (TA = 25 C; VA+ = +3.0 V 5% VA- = 0 V, VD+ = 3.0 V 5%,
DGND = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50pF) Parameter Master Clock Frequency: Master Clock Duty Cycle Rise Times (Note 19) Any Digital Input Except SCLK SCLK SDO Output (Note 19) Any Digital Input Except SCLK SCLK SDO Output XTAL = 32.768 kHz (Note 20) trise trise tost tpor 50 500 490 1.0 100 s s ns ms MCLK cycles MHz ns ns ns ns ns ns ns 50 1.0 100 s s ns Symbol External Clock MCLK Internal Oscillator (Note 18) Min 5 40 Typ 32.768 Max 40 60 Units kHz %
Fall Times
Start-up Oscillator Start-up Time Power-on Reset Period Serial Port Timing Serial Clock Frequency Serial Clock CS Enabled to SCLK Rising SCLK falling prior to Chip Select Disabled SDO Read Timing CS to Data Valid SCLK Falling to New Data Bit CS Rising to SDO Hi-Z t5 t6 t7 150 150 150 Pulse Width High Pulse Width Low SCLK t1 t2 t3 t4 0 250 250 50 100 2 -
Notes: 18. Device parameters are specified with 32.768 kHz clock; however, clocks up to 40 kHz can be used for increased throughput. 19. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 20. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.
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CS
t3
t1
t4
SCLK
t2
Figure 1. Continuous Running SCLK Timing (Not to Scale)
CS
t5 t7
SDO
MSB
t6
MSB-1
t2
LSB
SCLK
t1
Figure 2. SDO Read Timing (Not to Scale)
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2. GENERAL DESCRIPTION
The CS5540 is a low-power and low-voltage 24-bit - analog-to-digital converter (ADC). It is optimized to convert analog signals in DC measurement applications such as temperature and pressure measurement, and various portable devices where low power consumption is required. To accommodate these applications, the ADC integrates analog input and reference buffers for increased input impedance and includes a two-channel multiplexer. Absolute accuracy is accomplished via self-calibration. The device also operates with a variety of supply configurations while drawing a nominal 330 A. The CS5540 includes a digital filter which achieves simultaneous rejection of 50/60 Hz and provides single conversion settling at a 6.7 SPS throughput. The filter's output word rate can be increased by approximately 1.22X by using a 40 kHz master clock, although the 50/60 Hz rejection will be sacrificed. To ease communications between the ADC and a microcontroller, the converter includes a simple three-wire serial interface which is SPI and Microwire compatible. A Schmitt Trigger input is provided on the serial clock (SCLK) input.
2.1 Analog Input
Figure 3 illustrates a block diagram of the CS5540. The device consists of a multiplexer, a unity gain coarse/fine charge input buffer, a fourth order - modulator, and a digital filter.
2.1.1 Analog Input Model
Figure 4 illustrates the input models for the AIN pins. The model includes a coarse/fine charge buffer which reduces the dynamic current demands from the analog input signal. The buffer is designed to accommodate rail to rail (common-mode plus signal) input voltages. Typical CVF (sampling) current is about 8 nA (MCLK = 32.768 kHz). Application Note 30, "Switched-Capacitor A/D Input Structures", details various input architectures.
1 Fine in = CV os f AIN Vos 25mV 2 Coarse C = 8 pF f = 2*MCLK = 65.536 kHz
Figure 4. Input model for AIN+ and AIN- pins
VREF+ VREFX1 X1
AIN1+ X1 AIN1AIN2+ AIN2CHS M U X X1 Differential 4 th Order
Modulator
Sinc Digital Filter
4
Serial Port
CS SDO SCLK
Figure 3. Multiplexer Configuration 10 DS503PP1
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2.2 Voltage Reference Input
The differential voltage between VREF+ and VREF- sets the nominal full scale input span of the converter. For a single-ended reference voltage, the reference output is connected to the VREF+ pin of the CS5540 and the ground reference is connected to the VREF- pin. Note that the differential reference voltage can be from 0.1 V to ((VA+)- (VA-)). The noise-free resolution of a single sample from the ADC is directly proportional to the voltage reference as depicted in Figure 5.
Note: When a lower reference voltage is used, the resulting code widths are smaller. Since the output codes exhibit more changing codes for a fixed amount of noise, the converter appears noisier.
2.2.1 Voltage Reference Input Model
Figure 6 illustrates the input models for the VREF pins. It includes a coarse/fine charge buffer which reduces the dynamic current demand of the external reference. The reference's buffer is designed to accommodate rail-to-rail (common-mode plus signal) input voltages. Typical CVF (sampling) current is about 16 nA (MCLK = 32.768 kHz).
1 Fine in = CVosf VREF 2 Coarse C = 12 pF f = 2*MCLK = 65.536 kHz
Figure 6. Input model for VREF+ and VREF- pins
19 Noise-Free Resolution (Bits) 18 17 16 15 14 13 0 0.5 1 1.5 VREF (V) 2 2.5 3
Vos 25mV
Figure 5. Typical Noise-Free Resolution vs. Voltage Reference Noise-Free Res. = log2 (Bipolar Span/6.6*RMS Noise)
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2.3 Power Supply Arrangements
The CS5540 is designed to operate with a total supply voltage of 3.0 V 5%. For maximum flexibility, separate pins are provided for VA+, VA-, VD+, and DGND, which is especially useful with ground-referenced input signals. Figure 7 illustrates the CS5540 connected with a single +3.0 V supply for both the analog and digital sections.
2.5 Serial Port Interface
The CS5540's serial interface consists of three control lines: CS, SDO, and SCLK. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied to logic 0, the port can function as a three wire interface. SDO, Serial Data Out, is the data signal used to transfer output data from the converters. The SDO output will be held at high impedance any time CS is at logic 1. SCLK, Serial Clock, is the serial bit-clock which controls the shifting of data to or from the ADC's serial port. The CS pin must be held at logic 0 before SCLK transitions can be recognized by the port logic. To accommodate opto-isolators, SCLK is designed with a Schmitt-trigger input.
2.4 Clock Generator
The CS5540 includes an oscillator circuit which can be connected with an external crystal to provide the master clock for the chip. The chip is designed to operate using a low-cost 32.768 kHz "tuning fork" type crystal. One lead of the crystal should be connected to OSC1 and the other to OSC2. A 10 megohm resistor is required in parallel with the crystal. Lead lengths should be minimized to reduce stray capacitance. Note that the converter will operate with an external (CMOS compatible) clock with frequencies up to 40kHz, applied to the OSC1 pin.
2.6 Input Channel Selector
CHS, the Channel Select input, permits the user to select between AIN1 and AIN2 for data conversions. When CHS = 0, AIN1 is converted. When CHS = 1, AIN2 is converted. Note that since the converter continuously converts the input selected
10
+3.0 V Analog
Supply
0.1 F
0.1 F
4 VA+ 14 VREF+ VREF13
11 VD+ 9 OSC2 8 5 10 6
5 kHz ~ 40 kHz
Voltage Reference
+ -
10 M
OSC1 Optional Clock Source Serial Data Interface
CS5540
1 2 AIN1+ AIN1CS SDO SCLK
Analog Signal Sources
16 15
AIN2+ CHS AIN2VA3 DGND 12
7
Channel Selection
Figure 7. CS5540 Configured with a single +3.0 V Supply
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by CHS, the channel being converted can be switched at any time. The conversion in-process when CHS is switched will be aborted and a new conversion will begin on the selected channel. The indicator bits in the SDO output will indicate which channel was converted. decode the conversion word into the respective flag and data bits.
Note: The CS5540 offers self calibration, in which the ADC calibrates out offset and gain errors due to the ADC itself. Calibration in the CS5540 is used to set the zero and gain slope of the ADC's transfer function. For the self-calibration of offset, the converter internally ties the inputs of the modulator together and routes them to the VREF- pin as shown in Figure 9. VREF- must be tied to a fixed voltage between VA+ and VA-. For self-calibration of gain, the differential inputs of the modulator are connected to VREF+ and VREF- as shown in Figure10. Further note that each calibration step (offset or gain) is transparent to the user and is included in the specified 6.7 SPS output rate.
2.6.1 Switching Channels
7358 clock cycles after CHS is toggled, SDO will fall (indicating new data present). All subsequent data will be presented to the serial port every 4884 clock cycles, as portrayed in Figure 8.
2.7 Serial Port and Data Conversions
When power is applied to the CS5540, it is reset by the power-on reset circuit. Then the converter enters the data mode where the ADC continuously converts the analog input channel selected by the channel select pin (CHS). After a conversion is complete, the SDO pin falls to logic 0 to indicate an end of conversion and the next 32 serial clock pulses shift data out of the serial port. Figure 8 illustrates the sequence necessary to read output data from the data conversion register. The CS5540 operates in a self-calibration mode which allows the converter to calibrate continuously between each conversion (if a user requires system calibration, this can be accommodated in the system microcontroller). The sections that follow detail the conversion mode and also explain how to
SCLK
AIN+
+
AINVREF-
-
Figure 9. Self Calibration of Offset
CHS td * SDO * td = 7358 clock cycles to = 4884 clock cycles
0
SDI set low while reading status & data
to *
1 1 1 1 CH OD OF MSB LSB
8 SCLKs to read status Data Time 24 SCLKs
Figure 8. Command and Data Word Timing
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3) If the channel is switched when SDO is low, SDO will remain low, and the previous conversion result will remain in the serial port. SDO will rise one MCLK cycle before the new channel's data is ready, then fall to indicate that the conversion data is available.
AIN+
+
AINVREF+ Reference + VREF-
-
2.7.2 Output Coding
The CS5540 outputs a 24-bit two's-complement data conversion word. To read a conversion word the user must read the conversion data register, which is 24 bits long and outputs the conversions MSB first. Once a conversion is complete, SDO falls and 32 SCLK's are required to read a conversion. The first 8 SCLKs are used to clear an internal SDO flag and clock out status flags. The CH (CHannel indicator) bit keeps track of which input channel was converted (0=AIN1; 1=AIN2). The OD (Oscillation Detect) bit is set to a logic 1 any time that an oscillatory condition is detected in the modulator. This does not occur under normal operating conditions, but may occur whenever the input to the converter is extremely overranged. If the OD bit is set, the conversion data bits can be completely erroneous. The OD flag bit will be cleared to logic 0 when the modulator becomes stable. The OF (Overrange Flag) bit is set to a logic 1 any time the input signal is: 1) more positive than positive full scale, or 2) more negative than negative full scale. It is cleared back to logic 0 whenever a conversion word occurs which is not overranged. The last 24 SCLKs are used to clock the actual data out of the conversion data register. Table 1 and Table 2 illustrate the output coding for the CS5540. Conversion data is output in two's complement format.
Figure 10. Self Calibration of Gain
2.7.1 Reading Conversions
At the completion of a conversion, SDO will fall to logic 0 to indicate that the conversion is complete. Calibration will be transparent to the user. Nevertheless, to read a conversion word, the user must issue 32 SCLK's. The first 8 SCLKs clear the SDO flag and read the status flags. Upon the falling edge of the 8th SCLK, the SDO pin will present the first bit (MSB) of the conversion word. 24 SCLKs (high, then low) are then required to read the conversion word from the port. Upon the falling edge of the 32nd SCLK, SDO will return high, waiting till the next conversion is complete before it falls again. The user is not required to read every conversion. If the user chooses not to read a conversion after SDO falls, SDO will rise one MCLK clock cycle before the next conversion is completed and then fall to signal that another conversion word is available (assuming CS is kept low).
Note: 1) If the user begins to clear the SDO flag and read the conversion data, this action must be finished before the conversion cycle which is occurring in the background is complete if the user wants to be able to read the new conversion data. 2) If the multiplexer CHS input of the converter is switched while it is performing a conversion, the filter will abort the current conversion and start a new conversion on the new channel.
2.7.3 Digital Filter
The CS5540 filter achieves simultaneous rejection of 50/60 Hz and provides single conversion settling at a 6.7 SPS throughput, including auto-calibration.
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The filter is optimized to yield better than 80 dB rejection between 47 Hz to 63 Hz (i.e. 80 dB minimum rejection for both 50 Hz and 60 Hz) when the master clock is 32.768 kHz. The filter's output word rate can be increased by approximately 1.22X by using a 40 kHz master clock, although the 50/60 Hz rejection will be sacrificed. The filter has a response as shown in Figure 11.
Note: The converter's digital filter linearly scales with MCLK.
0 -20 -40
Magnitude (dB)
-60 -80 -100
47 Hz
-120 -140 0 20 40 60
63 Hz
80
100
120
Frequency (Hz)
Figure 11. Filter Response (MCLK = 32.768 kHz)
D23 MSB D11 11
D22 22 D10 10
D21 21 D9 9
D20 20 D8 8
D31 0 D19 19 D7 7
D30 1 D18 18 D6 6
D29 1 D17 17 D5 5
D28 1 D16 16 D4 4
D27 1 D15 15 D3 3
D26 CH D14 14 D2 2
D25 OD D13 13 D1 1
D24 OF D12 12 D0 LSB
Table 1. Output Conversion Data Register Description (24 bits + flags)
Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFFFF 7FFFFF ----7FFFFE 000000 ----FFFFFF 800001 ----800000 800000
-0.5 LSB
-VFS+0.5 LSB <(-VFS+0.5 LSB)
Table 2. CS5540 24-Bit Bipolar Output Coding Note: Plus or minus VFS is defined as a differential input signal equal in magnitude to the voltage between the VREF+ and VREF- pins. See the text about error flags for overrange and underrange conditions.
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2.8 Sleep Mode
The CS5540 features two power consumption modes: normal and sleep. The normal mode, the default mode, is entered after a power-on-reset. In normal mode, the CS5540 performs conversions and typically consumes 750 W. To enter sleep, transmit 8 SCLK's (low-high transitions) after SDO falls, indicating that a conversion is complete (32 SCLK's would be needed to read the conversion). One conversion cycle later, when SDO falls again, the part enters sleep, reducing the consumed power to around 30 W. During sleep, most of the analog portion of the chip is powered down and filter convolutions are halted. While the part is in the sleep mode, the SDO pin will remain in a logic high state, as long as the Chip Select is enabled. To exit the sleep mode, transmit 8 more SCLK's. Since the sleep mode disables the oscillator, approximately a 500 ms crystal oscillator start-up delay period is required before the ADC returns to the normal mode. If an external clock is used, the ADC will return to normal power mode within 3 milliseconds. In either case, the SDO pin will go low to indicate when new data is available and can be read. delay is being used to drive the ADC, then conversions will begin immediately.
Note: The CS5540 includes an on-chip power on reset circuit to automatically reset the ADC shortly after power-up. When power to the CS5540 is applied, the ADC is held in a reset condition until the master clock has started and a counter-timer elapses (i.e. the counter-timer counts 490 clock cycles to make sure the oscillator is fully stable).
After a valid reset, the ADC is initialized into the data state where it begins to continuously calibrate the ADC and convert the analog input. Once a valid conversion is complete, monitor the SDO pin for a falling edge to indicate that the data is ready to be read.
2.10 PCB Layout
The CS5540 should be placed entirely over an analog ground plane with the DGND pin of the device connected to the analog ground plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip See the CDB5540/41 data sheet for suggested layout details and refer to Applications Note 18 for more detailed layout guidelines. Applications engineering provides a Free and Confidential Schematic Review Service.
2.9 Power-Up and Initialization
Care must be exercised to insure that no pins are ever taken below the negative analog supply (VA-) potential. The analog and digital supplies should be applied simultaneously to assure that the power-on reset circuit will automatically reset the ADC when both supplies are at acceptable levels. Conversions will begin once a stable clock is available to the ADC. If a 32.768 kHz crystal is being used, it will take approximately 500 ms for the oscillator to stabilize and to begin conversions after power has been applied to the converter. If a CMOS compatible clock source with no start-up
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3. PIN DESCRIPTIONS
AIN1+ AIN1VAVA+ CS SCLK CHS OSC1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
AIN2+ AIN2VREF+ VREFDGND VD+ SDO OSC2
Clock Generator OSC1; OSC2 - Master Clock. An inverting amplifier inside the chip is connected between these pins and can be used with a crystal or resonator to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock (powered relative to VD+) can be supplied into the OSC1 pin to provide the master clock for the device and the OSC2 pin can be left unconnected. Control Pins and Serial Data I/O CS - Chip Select. When active low, the port will recognize SCLK. When high the SDO pin will output a high impedance state. CS should only be changed when SCLK = 0. SDO - Serial Data Output. SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK - Serial Clock Input. A clock signal on this pin determines the output rate of the data for the SDO pins respectively. This input is a Schmitt trigger to allow for slow rise-time signals. The SCLK pin will recognize clocks only when CS is low. CHS - Channel Select Input. CHS permits the user to select between AIN1 and AIN2 for data conversions. When CHS = 0, AIN1 is converted. When CHS = 1, AIN2 is converted. Note that since the converter continuously converts the input selected by CHS, the channel being converted can be switched at any time. The current conversion will be aborted and a new one started on the newly selected channel. The serial data status flags will indicate which channel was converted.
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Measurement and Reference Inputs AIN1+, AIN1-, AIN2+, AIN2- - Differential Analog Inputs. Differential input pins into the device. VREF+, VREF- - Voltage Reference Inputs. Fully differential inputs which establish the voltage reference for the on-chip modulator. Power Supply Connections VA+ - Positive Analog Power. Positive analog supply voltage. VA- - Negative Analog Power. Negative analog supply voltage. VD+ - Positive Digital Power. Positive digital supply voltage. DGND - Digital Ground. Ground return for the digital supply.
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CS5540
4. SPECIFICATION DEFINITIONS
Linearity Error The deviation of a code from a straight line which connects the two end points of the A/D Converter transfer function. One end point is located 1/2 LSB below the first code transition and the other end point is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below zero volts differential between the AIN+ and AIN- pins). Units are in LSBs.
DS503PP1
19
CS5540
5. PACKAGE DIMENSIONS
16L SSOP PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW
123
END VIEW
SEATING PLANE
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.232 0.291 0.197 0.022 0.025 0 NOM -0.005 0.069 0.012 0.244 0.307 0.209 0.026 0.0295 4 MAX 0.084 0.010 0.074 0.015 0.256 0.323 0.220 0.030 0.041 8 MIN -0.05 1.68 0.22 5.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.75 -6.20 7.80 5.30 0.65 0.75 4 MAX 2.13 0.25 1.88 0.38 6.50 8.20 5.60 0.75 1.03 8
NOTE
2,3 1 1
JEDEC #: MO-150 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
20
DS503PP1
* Notes *

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